74HC03-Q100; 74HCT03-Q100
Quad 2-input NAND gate
Rev. 1 — 4 July 2013
Product data sheet
1. General description
The 74HC03-Q100; 74HCT03-Q100 is a quad 2-input NAND gate with open-drain
outputs. Inputs include clamp diodes that enable the use of current limiting resistors to
interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC03-Q100: CMOS level
For 74HCT03-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1.
Ordering information
Type number
74HC03D-Q100
Package
Temperature range
Name
Description
Version
40 C to +125 C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
40 C to +125 C
SSOP14
plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
40 C to +125 C
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74HCT03D-Q100
74HC03DB-Q100
74HCT03DB-Q100
74HC03PW-Q100
74HCT03PW-Q100
SOT402-1
74HC03-Q100; 74HCT03-Q100
Nexperia
Quad 2-input NAND gate
4. Functional diagram
1 1A
2 1B
1Y 3
4 2A
5 2B
2Y 6
9 3A
10 3B
3Y 8
12 4A
13 4B
4Y 11
mna212
Fig 1.
Y
A
B
GND
DDD
Logic symbol
Fig 2.
001aab715
IEC logic symbol
Fig 3.
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
+&4
+&74
+&4
+&74
$
9&&
%
%
$
9&&
<
$
%
%
<
<
$
$
<
%
%
%
<
$
*1'
<
$
%
<
*1'
$
<
DDD
Fig 4.
DDD
Pin configuration SO14
Fig 5.
Pin configuration (T)SSOP14
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A to 4A
1, 4, 9, 12
data input
1B to 4B
2, 5, 10, 13
data input
1Y to 4Y
3, 6, 8, 11
data output
GND
7
ground (0 V)
VCC
14
supply voltage
74HC_HCT03_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 July 2013
©
Nexperia B.V. 2017. All rights reserved
2 of 14
74HC03-Q100; 74HCT03-Q100
Nexperia
Quad 2-input NAND gate
6. Functional description
Function table[1]
Table 3.
Input
Output
nA
nB
nY
L
L
Z
L
H
Z
H
L
Z
H
H
L
[1]
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
VO
output voltage
IIK
input clamping current
IOK
Conditions
Min
Max
Unit
0.5
+7
V
[1]
0.5
+7
V
VI < 0.5 V or VI > VCC + 0.5 V
[1]
-
20
mA
output clamping current
VO < 0.5 V
[1]
-
20
mA
IO
output current
0.5 V < VO
-
25
mA
ICC
supply current
-
50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
-
500
mW
[2]
total power dissipation
Ptot
SO14 and (T)SSOP14
packages
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
VCC
supply voltage
Conditions
74HC03-Q100
74HCT03-Q100
Unit
Min
Typ
Max
Min
Typ
Max
2.0
5.0
6.0
4.5
5.0
5.5
V
VI
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
40
+25
+125
40
+25
+125
C
t/V
input transition rise and fall rate
-
-
625
-
-
-
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
74HC_HCT03_Q100
Product data sheet
VCC = 2.0 V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 July 2013
©
ns/V
Nexperia B.V. 2017. All rights reserved
3 of 14
74HC03-Q100; 74HCT03-Q100
Nexperia
Quad 2-input NAND gate
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
1.2
-
1.5
-
1.5
-
V
VCC = 4.5 V
3.15
2.4
-
3.15
-
3.15
-
V
VCC = 6.0 V
4.2
3.2
-
4.2
-
4.2
-
V
74HC03-Q100
VIH
VIL
VOL
HIGH-level
input voltage
LOW-level
input voltage
LOW-level
output voltage
VCC = 2.0 V
-
0.8
0.5
-
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
-
1.8
V
IO = 20 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
0.15
0.26
-
0.33
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
VI = VIH or VIL
-
0.16
0.26
-
0.33
-
0.4
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
-
-
1
-
1
A
IOZ
OFF-state
output current
per input pin; VI = VIL;
VO = VCC or GND;
other inputs at VCC or GND;
VCC = 6.0 V; IO = 0 A
-
-
±0.5
-
±5.0
-
±10
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
2.0
-
-
20
-
40
A
CI
input
capacitance
-
3.5
-
-
-
-
-
pF
74HCT03-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
-
0.8
V
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA
-
0.15
0.26
-
0.33
-
0.4
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
-
0.1
-
1
-
1
A
IOZ
OFF-state
output current
per input pin; VI = VIL;
VO = VCC or GND;
other inputs at VCC or GND;
VCC = 5.5 V; IO = 0 A
-
-
±0.5
-
±5.0
-
±10
A
74HC_HCT03_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 July 2013
©
Nexperia B.V. 2017. All rights reserved
4 of 14
74HC03-Q100; 74HCT03-Q100
Nexperia
Quad 2-input NAND gate
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
2.0
-
20
-
40
A
ICC
additional
supply current
per input pin;
VI = VCC 2.1 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
-
100
360
-
450
-
490
A
CI
input
capacitance
-
3.5
-
-
-
-
-
pF
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; CL = 50 pF; for load circuit, see Figure 7.
Symbol Parameter
25 C
Conditions
40 C to +125 C Unit
Min
Typ
Max
Max
(85 C)
Max
(125 C)
74HC03-Q100
tpd
propagation delay nA, nB to nY; see Figure 6
[1]
VCC = 2.0 V
-
28
95
120
145
ns
VCC = 4.5 V
-
10
19
24
29
ns
VCC = 5.0 V; CL = 15 pF
-
8
-
-
-
ns
-
8
16
20
25
ns
VCC = 2.0 V
-
19
75
95
110
ns
VCC = 4.5 V
-
7
15
19
22
ns
-
6
13
16
19
ns
-
4
-
-
-
pF
VCC = 6.0 V
tt
transition time
[2]
see Figure 6
VCC = 6.0 V
CPD
power dissipation
capacitance
74HC_HCT03_Q100
Product data sheet
per package; VI = GND to VCC
[3]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 July 2013
©
Nexperia B.V. 2017. All rights reserved
5 of 14
74HC03-Q100; 74HCT03-Q100
Nexperia
Quad 2-input NAND gate
Table 7.
Dynamic characteristics …continued
GND = 0 V; CL = 50 pF; for load circuit, see Figure 7.
Symbol Parameter
25 C
Conditions
40 C to +125 C Unit
Min
Typ
Max
Max
(85 C)
Max
(125 C)
-
12
24
30
36
ns
-
10
-
-
-
ns
74HCT03-Q100
[1]
propagation delay nA, nB to nY; see Figure 6
tpd
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
tt
transition time
VCC = 4.5 V; see Figure 6
[2]
CPD
power dissipation
capacitance
per package;
VI = GND to VCC 1.5 V
[3]
[1]
-
7
15
19
22
ns
-
4
-
-
-
pF
tpd is the same as tPLZ and tPZL.
[2]
tt is the same as tTHL.
[3]
CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
9,
90
Q$Q%LQSXW
*1'
W3/=
W3=/
9&&
Q
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