74ALVCH16646DGGS

74ALVCH16646 16-bit bus transceiver/register; 3-state Rev. 3 — 11 September 2018 Product data sheet 1. General description The 74ALVCH16646 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal registers, as the appropriate clock (nCPAB or nCPBA) goes to a HIGH logic level. Output enable (nOE) and direction (nDIR) inputs are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the ‘A’ or ‘B’ register, or in both. The select source inputs (nSAB and nSBA) can multiplex stored and real-time (transparent mode) data. The direction (nDIR) input determines which bus will receive data when nOE is active (LOW). In the isolation mode (nOE = HIGH), ‘A’ data may be stored in the ‘B’ register and/or ‘B’ data may be stored in the ‘A’ register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, ‘A’ or ‘B’ may be driven at a time. To ensure the high impedance state during power up or power down, nOE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/ current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 2. Features and benefits • • • • • • • • • • Wide supply voltage range of 2.3 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Current drive ±24 mA at VCC = 3.0 V. MULTIBYTE flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimize noise and ground bounce All data inputs have bushold Output drive capability 50 Ω transmission lines at 85 °C Complies with JEDEC standards: • JESD8-5 (2.3 V to 2.7 V) • JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: • HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V • CDM JESD22-C101E exceeds 1000 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74ALVCH16646DGG −40 °C to +85 °C TSSOP56 Description Version plastic thin shrink small outline package; 56 leads; SOT364-1 body width 6.1 mm 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state 4. Functional diagram 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1OE 1DIR 1SAB 1SBA 1CPAB 1CPBA 5 52 6 51 8 49 9 48 10 47 12 45 13 44 14 43 1B0 2A0 1B1 2A1 1B2 2A2 1B3 2A3 1B4 2A4 1B5 2A5 1B6 2A6 1B7 2A7 56 19 38 20 37 21 36 23 34 24 33 2B1 2B2 2B3 2B4 VCC 2B5 2B6 2B7 data input to internal circuit 27 2CPAB 55 40 31 2SBA 2 17 2B0 26 2SAB 54 41 29 2DIR 3 42 16 28 2OE 1 15 30 2CPBA 001aad245 aaa-029016 Fig. 1. Logic symbol 1OE 1DIR 1CPBA 1SBA 1CPAB 1SAB 1A0 56 1 55 54 2 3 5 Fig. 2. G3 2OE 3EN1[BA] 2DIR 3EN2[AB] C4 2CPBA G5 2SBA C6 2CPAB G7 1 2SAB ≥1 5 6D 1A1 1A2 1A3 1A4 1A5 1A6 1A7 6 5 7 1 7 4D 52 1B0 1 ≥1 2A0 29 28 30 31 27 26 15 G10 10EN8[BA] 10EN9[AB] C11 G12 C13 G14 8 ≥1 13D 2 51 8 49 9 48 10 47 12 45 13 44 14 43 1B1 2A1 1B2 2A2 1B3 2A3 1B4 2A4 1B5 2A5 1B6 2A6 1B7 2A7 Bus hold circuit 16 12 11D 42 2B0 12 1 14 1 14 ≥1 9 41 17 40 19 38 20 37 21 36 23 34 24 33 2B1 2B2 2B3 2B4 2B5 2B6 2B7 aaa-029017 Fig. 3. IEEE logic symbol 74ALVCH16646 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 2 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state nOE nDIR nSBA nCPBA nSAB nCPAB VCC S Y D1 MUX D2 nAn Q D FFn CP VCC D Q FFn CP S D1 Y MUX D2 nBn 8 IDENTICAL CHANNELS aaa-029018 Fig. 4. Logic diagram (one section) 74ALVCH16646 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 3 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state 5. Pinning information 5.1. Pinning 74ALVCH16646 1DIR 1 56 1OE 1CPAB 2 55 1CPBA 1SAB 3 54 1SBA GND 4 53 GND 1A0 5 52 1B0 1A1 6 51 1B1 VCC 7 50 VCC 1A2 8 49 1B2 1A3 9 48 1B3 1A4 10 47 1B4 GND 11 46 GND 1A5 12 45 1B5 1A6 13 44 1B6 1A7 14 43 1B7 2A0 15 42 2B0 2A1 16 41 2B1 2A2 17 40 2B2 GND 18 39 GND 2A3 19 38 2B3 2A4 20 37 2B4 2A5 21 36 2B5 VCC 22 35 VCC 2A6 23 34 2B6 2A7 24 33 2B7 GND 25 32 GND 2SAB 26 31 2SBA 2CPAB 27 30 2CPBA 2DIR 28 29 2OE aaa-029019 Fig. 5. Pin configuration for TSSOP56 (SOT364-1) 74ALVCH16646 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 4 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A0, 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7 5, 6, 8, 9, 10, 12, 13, 14 data input/output 2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7 15, 16, 17, 19, 20, 21, 23, 24 data input/output 1B0, 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7 52, 51, 49, 48, 47, 45, 44, 43 data output/input 2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6, 2B7 42, 41, 40, 38, 37, 36, 34, 33 data output/input 1OE, 2OE 56, 29 output enable input (active-LOW) 1DIR, 2DIR 1, 28 direction control input 1SAB, 2SAB 3, 26 delect input A-to-B 1CPAB, 2CPAB 2, 27 clock input A-to-B 1SBA, 2SBA 54, 31 select input B-to-A 1CPBA, 2CPBA 55, 30 clock input B-to-A GND 4, 11, 18, 25, 32, 39, 46, 53 ground (0 V) VCC 7, 22, 35, 50 supply voltage 6. Functional description Table 3. Function selection H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; Operating mode Inputs Data I/O nOE nDIR nCPAB nCPBA nSAB nSBA nAn nBn store A, B unspecified[1] X X ↑ X X X input unspecified[1] store B, A unspecified[1] X X X ↑ X X unspecified[1] input store A and B data, isolation H X ↑ ↑ X X input input hold storage H X H or L H or L X X input input real-time B data to A bus L L X X X L output input stored B data to A bus L L X H or L X H output input real-time A data to B bus L H X X L X input output stored A data to B bus L H H or L X H X input output [1] The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs. 74ALVCH16646 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 5 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage IIK input clamping current VI < 0 V IOK output clamping current IO (sink/source) output sink or source current ICC IGND Min Max Unit -0.5 +4.6 V data inputs [1] -0.5 control inputs [1] -0.5 [1] -0.5 VCC + 0.5 V +4.6 V VCC + 0.5 V -50 - mA VO > VCC or VO < 0 V - ±50 mA VO = 0 V to VCC - ±50 mA supply current - 100 mA ground current -100 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 600 mW [1] [2] Tamb = −40 °C to +85 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP56 packages: above 55 °C derate linearly with 8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage Min Max Unit for maximum speed performance; 30 pF output load 2.3 2.7 V for maximum speed performance; 50 pF output load 3.0 3.6 V VI input voltage 0 VCC V VO output voltage 0 VCC V Tamb ambient temperature in free air -40 +85 °C Δt/ΔV input transition rise and fall rate VCC = 2.3 V to 3.0 V - 20 ns/V VCC = 3.0 V to 3.6 V - 10 ns/V 74ALVCH16646 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 6 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = -40 °C to +85 °C Symbol Parameter Conditions Min Typ[1] Max VIH HIGH-level input voltage VCC = 2.3 V to 2.7 V 1.7 1.2 - V VCC = 2.7 V to 3.6 V 2.0 1.5 - V LOW-level input voltage VCC = 2.3 V to 2.7 V - 1.2 0.7 V VCC = 2.7 V to 3.6 V - 1.5 0.8 V HIGH-level output voltage VI = VIH or VIL IO = -100 μA; VCC = 2.3 V to 3.6 V VCC - 0.2 VCC - V IO = -6 mA; VCC = 2.3 V VCC - 0.3 VCC - 0.08 - V IO = -12 mA; VCC = 2.3 V VCC - 0.6 VCC - 0.26 - V IO = -12 mA; VCC = 2.7 V VCC - 0.5 VCC - 0.14 - V IO = -12 mA; VCC = 3.0 V VCC - 0.6 VCC - 0.09 - V IO = -24 mA; VCC = 3.0 V VCC - 1.0 VCC - 0.28 - V IO = 100 μA; VCC = 2.3 V to 3.6 V - GND 0.20 V IO = 6 mA; VCC = 2.3 V - 0.07 0.40 V IO = 12 mA; VCC = 2.3 V - 0.15 0.70 V IO = 12 mA; VCC = 2.7 V - 0.14 0.40 V IO = 24 mA; VCC = 3.0 V - 0.27 0.55 V VIL VOH VOL LOW-level output voltage Unit VI = VIH or VIL II input leakage current VCC = 2.3 V to 3.6 V; VI = VCC or GND - 0.1 5 μA IOZ OFF-state output current VCC = 2.7 V to 3.6 V; VI = VIH or VIL; VO = VCC or GND - 0.1 10 μA ICC supply current VCC = 2.3 V to 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 40 μA ΔICC additional supply current VCC = 2.3 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 150 750 μA IBHL bus hold LOW current VCC = 2.3 V; VI = 0.7 V 45 - - μA VCC = 3.0 V; VI = 0.8 V 75 150 - μA bus hold HIGH current VCC = 2.3 V; VI = 1.7 V -45 - - μA VCC = 3.0 V; VI = 2.0 V -75 -175 - μA IBHLO bus hold LOW overdrive current VCC = 3.6 V 500 - - μA IBHHO bus hold HIGH overdrive current VCC = 3.6 V -500 - - μA CI input capacitance - 3.0 - pF IBHH [1] All typical values are measured at Tamb = 25 °C. 74ALVCH16646 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 7 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit, see Fig. 11. Symbol Parameter Conditions tpd nAn to nBn; nBn to nAn; see Fig. 6 propagation delay Min Typ [1] Max Unit VCC = 2.3 V to 2.7 V 1.0 2.7 4.8 ns VCC = 2.7 V 1.0 2.8 4.5 ns VCC = 3.0 V to 3.6 V 1.0 2.6 3.9 ns VCC = 2.3 V to 2.7 V 1.0 3.4 5.6 ns VCC = 2.7 V 1.4 3.1 5.2 ns VCC = 3.0 V to 3.6 V 1.4 2.9 4.5 ns VCC = 2.3 V to 2.7 V 1.0 3.4 6.8 ns VCC = 2.7 V 1.3 3.5 6.4 ns VCC = 3.0 V to 3.6 V 1.3 3.1 5.3 ns VCC = 2.3 V to 2.7 V 1.0 3.3 6.5 ns VCC = 2.7 V 1.0 3.2 6.2 ns VCC = 3.0 V to 3.6 V 1.0 2.3 5.1 ns VCC = 2.3 V to 2.7 V 1.0 3.4 7.8 ns VCC = 2.7 V 1.4 3.4 6.2 ns VCC = 3.0 V to 3.6 V 1.4 3.0 5.1 ns VCC = 2.3 V to 2.7 V 1.6 2.8 5.7 ns VCC = 2.7 V 1.0 3.1 5.0 ns VCC = 3.0 V to 3.6 V 1.0 2.9 4.7 ns VCC = 2.3 V to 2.7 V 1.5 3.0 6.5 ns VCC = 2.7 V 1.4 3.3 6.0 ns VCC = 3.0 V to 3.6 V 1.4 2.5 5.3 ns VCC = 2.3 V to 2.7 V 3.3 1.2 - ns VCC = 2.7 V 3.3 1.0 - ns VCC = 3.0 V to 3.6 V 3.3 0.7 - ns VCC = 2.3 V to 2.7 V 1.6 0.2 - ns VCC = 2.7 V 1.7 0.2 - ns VCC = 3.0 V to 3.6 V 1.4 0.3 - ns [2] nCPAB to nBn; nCPBA to nAn; see Fig. 7 nSAB to nBn; nSBA to nAn; see Fig. 8 ten enable time nOE to nAn; nOE to nBn; see Fig. 10 nDIR to nAn; nDIR to nBn; see Fig. 10 tdis disable time nOE to nAn; nOE to nBn; see Fig. 10 nDIR to nAn; nDIR to nBn; see Fig. 10 tw tsu pulse width set-up time 74ALVCH16646 Product data sheet [3] [3] [4] [4] nCPAB HIGH or LOW; nCPBA HIGH or LOW; see Fig. 7 nAn to nCPAB; nBn to nCPBA; see Fig. 9 All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 8 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state Symbol Parameter Conditions th nAn to nCPAB; nBn to nCPBA; see Fig. 9 hold time fmax maximum frequency Min Typ [1] Max VCC = 2.3 V to 2.7 V 0.6 0.1 - ns VCC = 2.7 V 0.4 0.1 - ns VCC = 3.0 V to 3.6 V 0.7 0.2 - ns VCC = 2.3 V to 2.7 V 150 300 - MHz VCC = 2.7 V 150 320 - MHz 150 320 - MHz output enabled - 36 - pF output disabled - 4 - pF nCPAB; nCPBA; see Fig. 7 VCC = 3.0 V to 3.6 V CPD [1] [2] [3] [4] [5] power dissipation capacitance Unit per channel; VI = GND to VCC [5] Typical values are measured at Tamb = 25 °C Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V tpd is the same as tPHL and tPLH. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. CPD is used to determine the dynamic power dissipation (PD in μW): 2 2 PD = CPD × VCC × fi × N +∑(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL × VCC × fo) = sum of outputs. 10.1. Waveforms and test circuit VI nAn, nBn input VM VM tPHL tPLH GND VOH nBn, nAn output VM VOL VM aaa-027928 See Table 8 for measurement points. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. Input (nAn, nBn) to output (nBn, nAn) propagation delays 74ALVCH16646 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 9 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state 1/fmax VI nCPAB, nCPBA input VM VM VM GND tW tPHL tPLH VOH nBn, nAn output VM VM VOL aaa-029020 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 7. Clock input (nCPAB; nCPBA) to data output (nBn; nAn) propagation delays, clock pulse width (nCPAB; nCPBA) and maximum clock frequency (nCPAB; nCPBA) VI nSAB, nSBA input VM VM tPHL tPLH GND VOH nBn, nAn output VM VM VOL aaa-029021 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. Select source inputs (nSAB; nSBA) to data output (nBn; nAn) propagation delays VI nAn, nBn input VM VM VM VM GND VI tsu th VM nCPBA, nCPAB input GND tsu th VM aaa-029022 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 9. Data set-up and hold times for nAn, nBn inputs to nCPAB and nCPBA inputs 74ALVCH16646 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 10 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state nOE, nDIR input nDIR VI VM GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCC VM VX VOL tPHZ output HIGH-to-OFF OFF-to-HIGH VOH tPZH VY VM GND outputs enabled outputs disabled outputs enabled aaa-029023 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 10. 3-state enable and disable times. Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 2.3 V to 2.7 V VCC 0.5 x VCC 0.5 x VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74ALVCH16646 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 11 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 11. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 74ALVCH16646 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 12 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state BUS B BUS A BUS B BUS A 11. Application information aaa-028366 aaa-028367 nOE nDIR nCPAB nCPBA nSAB nSBA nOE nDIR nCPAB nCPBA nSAB nSBA L L X X X L L H X X L X BUS A BUS B Fig. 13. Real time bus transfer bus A to bus B BUS B BUS A Fig. 12. Real time bus transfer bus B to bus A aaa-028368 aaa-028369 nOE nDIR nCPAB nCPBA nSAB nSBA X X ↑ X X X nOE X X X ↑ X X L H X ↑ ↑ X X L Fig. 14. Storage from bus A, B or A and B 74ALVCH16646 Product data sheet nDIR nCPAB nCPBA nSAB nSBA L X H H or L H or L X H X H X Fig. 15. Transfer stored data to bus A or B All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 13 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state 12. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3 ) A1 pin 1 index A θ Lp L 1 28 w M bp e detail X 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig. 16. Package outline SOT364-1 (TSSOP56) 74ALVCH16646 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 14 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVCH16646 v.3 20180911 Product data sheet - 74ALVCH16646 v.2 Modifications: • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. 74ALVCH16646 v.2 19980903 Product specification - 74ALVCH16646 v.1 74ALVCH16646 v.1 19980903 Product specification - - 74ALVCH16646 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 15 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state 15. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74ALVCH16646 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 16 / 17 74ALVCH16646 Nexperia 16-bit bus transceiver/register; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................4 5.1. Pinning.........................................................................4 5.2. Pin description............................................................. 5 6. Functional description................................................. 5 7. Limiting values............................................................. 6 8. Recommended operating conditions..........................6 9. Static characteristics....................................................7 10. Dynamic characteristics............................................ 8 10.1. Waveforms and test circuit........................................ 9 11. Application information............................................13 12. Package outline........................................................ 14 13. Abbreviations............................................................ 15 14. Revision history........................................................15 15. Legal information......................................................16 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 11 September 2018 74ALVCH16646 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 September 2018 © Nexperia B.V. 2018. All rights reserved 17 / 17