74LVC2G16GFH

74LVC2G16 Dual buffer gate Rev. 2 — 12 October 2016 Product data sheet 1. General description The 74LVC2G16 provides two buffers. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits            Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard:  JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Multiple package options Specified from 40 C to +85 C and 40 C to +125 C. 74LVC2G16 Nexperia Dual buffer gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G16GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74LVC2G16GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1  1.45  0.5 mm 74LVC2G16GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1  1  0.5 mm 4. Marking Table 2. Marking Type number Marking code[1] 74LVC2G16GW YU 74LVC2G16GM YU 74LVC2G16GF YU [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram  $ <   $ <       $ < PQE PQE Fig 1.  Logic symbol Fig 2. DDF IEC logic symbol Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning /9&* /9&* $   < *1'   9&& $   < $   < *1'   9&& $   < DDD 7UDQVSDUHQWWRSYLHZ DDD Fig 4. Pin configuration SOT363 74LVC2G16 Product data sheet Fig 5. Pin configuration SOT886 and SOT891 All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2016 © Nexperia B.V. 2017. All rights reserved 2 of 14 74LVC2G16 Nexperia Dual buffer gate 6.2 Pin description Table 3. Pin description Symbol Pin Description 1A 1 data input GND 2 ground (0 V) 2A 3 data input 2Y 4 data output VCC 5 supply voltage 1Y 6 data output 7. Functional description Table 4. Function table[1] Input Output nA nY L L H H [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature [1] Conditions VI < 0 V [1] Min Max Unit 0.5 +6.5 50 - 0.5 +6.5 V mA V mA - 50 Active mode [1][2] 0.5 VCC + 0.5 V Power-down mode [1][2] 0.5 +6.5 V - 50 mA - 100 mA 100 - mA - 250 mW 65 +150 C VO > VCC or VO < 0 V VO = 0 V to VCC Tamb = 40 C to +125 C [3] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 74LVC2G16 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2016 © Nexperia B.V. 2017. All rights reserved 3 of 14 74LVC2G16 Nexperia Dual buffer gate 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature t/V input transition rise and fall rate Min Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V Active mode 0 - VCC V Power-down mode; VCC = 0 V 0 - 5.5 V 40 - +125 C VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 5.5 V - - 10 ns/V 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage 40 C to +85 C Conditions Max Min Max 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.65 V to 1.95 V - - 0.35VCC - VCC = 1.65 V to 1.95 V Product data sheet 0.35VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V VCC  0.1 - - VCC  0.1 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 0.95 - V IO = 8 mA; VCC = 2.3 V 1.9 - - 1.7 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 1.9 - V IO = 24 mA; VCC = 3.0 V 2.3 - - 2.0 - V IO = 32 mA; VCC = 4.5 V 3.8 - - 3.4 - V - - 0.10 - 0.10 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.30 - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.40 - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.55 - 0.80 V - 0.1 5 - 20 A LOW-level VI = VIH or VIL output voltage IO = 100 A; VCC = 1.65 V to 5.5 V 74LVC2G16 Unit Min HIGH-level VI = VIH or VIL output voltage IO = 100 A; VCC = 1.65 V to 5.5 V input leakage current 40 C to +125 C Typ[1] VI = 5.5 V or GND; VCC = 0 V to 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2016 © Nexperia B.V. 2017. All rights reserved 4 of 14 74LVC2G16 Nexperia Dual buffer gate Table 7. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Unit Min Max Min Max - 0.1 10 - 20 A IOFF power-off leakage current ICC supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V - 0.1 10 - 40 A ICC additional per pin; VCC = 2.3 V to 5.5 V; supply current VI = VCC  0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance - 2.5 - - - pF [1] VCC = 0 V; VI or VO = 5.5 V 40 C to +125 C Typ[1] VCC = 3.3 V; VI = GND to VCC All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 7. Symbol Parameter 40 C to +85 C Conditions Max Min Max VCC = 1.65 V to 1.95 V 1.0 3.8 8.6 1.0 10.8 ns [2] VCC = 2.3 V to 2.7 V 0.5 2.4 4.4 0.5 5.5 ns VCC = 2.7 V 0.5 2.5 5.0 0.5 6.3 ns VCC = 3.0 V to 3.6 V 0.5 2.2 4.1 0.5 5.1 ns 0.5 1.9 3.2 0.5 4.0 ns - 20 - - - pF VCC = 4.5 V to 5.5 V power dissipation capacitance CPD [1] Unit Typ[1] propagation delay nA to nY; see Figure 6 tpd 40 C to +125 C Min VI = GND to VCC; VCC = 3.3 V [3] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 74LVC2G16 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 12 October 2016 © Nexperia B.V. 2017. All rights reserved 5 of 14 74LVC2G16 Nexperia Dual buffer gate 12. Waveforms 9, Q$LQSXW 90 90 *1' W3/+ W3+/ 92+ 90 Q