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TPS54040-Q1
SLVSA26E – JANUARY 2010 – REVISED JUNE 2015
TPS54040-Q1 0.5-A 42-V Step-Down DC-DC Converter
With Eco-Mode™
1 Features
3 Description
•
•
•
•
The TPS54040-Q1 device is a 42-V 0.5-A step-down
regulator with an integrated high-side MOSFET.
Current mode control provides simple external
compensation and flexible component selection. A
low-ripple pulse-skip mode reduces the no load, input
supply current to 116 μA. Using the enable pin,
shutdown supply current is reduced to 1.3 μA, when
the enable pin is low.
1
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
3.5-V to 42-V Input Voltage Range
200-mΩ High-Side MOSFET
High Efficiency at Light Loads with a Pulse
Skipping Eco-Mode™ Control Scheme
116-μA Operating Quiescent Current
1.3-μA Shutdown Current
100-kHz to 2.5-MHz Switching Frequency
Synchronizes to External Clock
Adjustable Slow Start and Sequencing
Undervoltage and Overvoltage Power-good
Output
Adjustable Undervoltage Lockout Voltage and
Hysteresis
0.8-V Internal Voltage Reference
Supported by SwitcherPro™ Software Tool
(http://focus.ti.com/docs/toolsw/folders/print/switch
erpro.html)
2 Applications
•
•
•
•
12-V and 24-V Industrial and Commercial Low
Power Systems
Automotive Infotainment, Head Unit, Display
Navigation, Audio and Clusters
Automotive Body applications, HVAC, Wireless
Charging
Advanced Driver Assistance System (ADAS),
Rear View Camera Module, Blind Spot Radar
SPACE
Simplified Schematic
Undervoltage lockout is internally set at 2.5 V, but
can be increased using the enable pin. The output
voltage startup ramp is controlled by the slow start
pin that can also be configured for sequencing or
tracking. An open drain power-good signal indicates
the output is within 92% to 109% of its nominal
voltage.
A wide switching frequency range allows efficiency
and external component size to be optimized.
Frequency fold back and thermal shutdown protects
the part during an overload condition.
The TPS54040-Q1 is available in a 10-pin thermally
enhanced MSOP PowerPAD™ package (DGQ) and a
10-pin SON package (DRC).
Device Information(1)
PART NUMBER
TPS54040-Q1
PACKAGE
BODY SIZE (NOM)
MSOP PowerPAD (10)
3.00 mm × 3.00 mm
VSON (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Efficiency vs Load Current
100
VIN
PWRGD
90
80
EN
BOOT
PH
Efficiency - %
TPS54040
70
60
50
40
30
SS /TR
RT /CLK
COMP
VI = 12 V,
20
VO = 5.0 V,
10
VSENSE
0
0
0.1
0.2
0.3
Load Current - A
0.4
0.5
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54040-Q1
SLVSA26E – JANUARY 2010 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
12
12
22
8
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Application .................................................. 30
9 Power Supply Recommendations...................... 39
10 Layout................................................................... 39
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Power Dissipation Estimate ..................................
Estimated Circuit Area ..........................................
39
39
40
40
11 Device and Documentation Support ................. 42
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
42
42
42
42
42
12 Mechanical, Packaging, and Orderable
Information ........................................................... 42
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (June 2012) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Moved "Operating junction temperature row" from Absolute Maximum Ratings to Recommended Operating
Conditions .............................................................................................................................................................................. 4
•
Changed title "How to Interface to RT/CLK Pin" to External Clock Synchronization Using RT/CLK Pin ............................ 23
•
Deleted Capacitor Types table ............................................................................................................................................ 34
Changes from Revision C (January 2012) to Revision D
Page
•
Changed "regulated output supply current" to "input supply current"..................................................................................... 1
•
Changed 107% to 109% in description .................................................................................................................................. 1
•
Addded (fault) and (good) to VSENSE rising and falling........................................................................................................ 6
•
Changed "UVLO adjust registers" to "UVLO adjust resistors" ............................................................................................. 14
•
Removed "and the power pad", changed power pad to PowerPAD where applicable ........................................................ 39
2
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SLVSA26E – JANUARY 2010 – REVISED JUNE 2015
5 Pin Configuration and Functions
DGQ Package
10-Pin MSOP-PowerPAD
Top View
BOOT
VIN
EN
SS/TR
RT/CLK
1
10
2
9
Thermal
Pad
(11)
3
4
8
7
6
5
DRC Package
10-Pin VSON With Thermal Pad
Top View
PH
GND
COMP
VSENSE
PWRGD
BOOT
1
10
PH
VIN
EN
SS/TR
RT/CLK
2
9
GND
COMP
VSENSE
PWRGD
3
4
5
Thermal
Pad
(11)
8
7
6
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BOOT
1
O
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
COMP
8
O
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
components to this pin.
EN
3
I
Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors.
GND
9
–
Ground
PH
10
I
The source of the internal high-side power MOSFET.
PWRGD
6
O
An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or
EN shut down.
RT/CLK
5
I
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is reenabled and the mode returns to a resistor set function.
SS/TR
4
I
Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
VIN
2
I
Input supply voltage, 3.5 V to 42 V.
VSENSE
7
I
Inverting node of the transconductance ( gm) error amplifier.
Thermal Pad
11
–
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VIN
–0.3
47
EN (2)
–0.3
5
BOOT
Input voltage
55
VSENSE
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
6
SS/TR
–0.3
3
RT/CLK
–0.3
3.6
–0.6
47
–1
47
–2
47
BOOT-PH
200 ns Transient Pulse
PH
30 ns Transient Pulse
DC voltage, TJ = –40°C
Voltage difference
Source current
PAD to GND
±200
EN
100
μA
BOOT
100
mA
VSENSE
10
μA
100
μA
VIN
Current Limit
100
μA
PWRGD
10
mA
SS/TR
200
μA
150
°C
COMP
Storage temperature
(2)
mV
Current Limit
RT/CLK
(1)
V
–0.85
PH
Sink current
V
8
DC Voltage
Output voltage
UNIT
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See Enable and Adjusting Undervoltage Lockout for details.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002
(1)
±500
Charged-device model (CDM), per AEC Q100-011
UNIT
V
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN supply voltage
3.5
Output current capability
Output voltage range for adjustable voltage
0.8
Effective input capacitance
MAX
–40
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UNIT
42
V
0.5
A
VIN
3
Operating junction temperature, TJ
4
NOM
V
µF
150
°C
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SLVSA26E – JANUARY 2010 – REVISED JUNE 2015
6.4 Thermal Information
TPS54040-Q1
THERMAL METRIC (1) (2)
DGQ (HVSSOP)
DRC (VSON)
10 PINS
10 PINS
UNIT
62.5
56.5
°C/W
RθJA
Junction-to-ambient thermal resistance (standard board)
RθJA
Junction-to-case (top) thermal resistance
83
52.1
°C/W
RθJC(top)
Junction-to-ambient thermal resistance (custom board) (3)
57
61.5
°C/W
RθJB
Junction-to-board thermal resistance
28
20.6
°C/W
ψJT
Junction-to-top characterization parameter
1.7
0.9
°C/W
ψJB
Junction-to-board characterization parameter
20.1
20.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
21
5.2
°C/W
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
Test boards conditions:
(a) 3 inches x 3 inches, 2 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground plane, bottom layer
(d) 6 thermal vias (13 mil) located under the device package
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 3.5 to 42 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
Internal undervoltage lockout
threshold
Shutdown supply current
Operating : nonswitching supply
current
3.5
42
No voltage hysteresis, rising and falling
2.5
EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 42 V
1.3
4
EN = 0 V, 125°C, 3.5 V ≤ VIN ≤ 42 V
1.9
6.5
VSENSE = 0.83 V, VIN = 12 V, 25°C
116
136
1.25
1.55
V
V
μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
Input current
No voltage hysteresis, rising and falling, 25°C
0.9
Enable threshold 50 mV
–3.8
Enable threshold –50 mV
–0.9
Hysteresis current
V
μA
μA
–2.9
VOLTAGE REFERENCE
Voltage reference
TJ = 25°C
0.792
0.8
0.808
0.784
0.8
0.816
V
HIGH-SIDE MOSFET
On-resistance
VIN = 3.5 V, BOOT-PH = 3 V
300
VIN = 12 V, BOOT-PH = 6 V
200
410
mΩ
ERROR AMPLIFIER
Input current
50
nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V
97
μMhos
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V,
during slow start
VVSENSE = 0.4 V
26
μMhos
Error amplifier DC gain
VVSENSE = 0.8 V
Error amplifier bandwidth
Error amplifier source/sink
V(COMP) = 1 V, 100-mV overdrive
COMP to switch current
transconductance
10,000
V/V
2700
kHz
±7
μA
1.9
A/V
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Electrical Characteristics (continued)
TJ = –40°C to 150°C, VIN = 3.5 to 42 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.6
0.94
A
182
°C
CURRENT LIMIT
Current limit threshold
VIN = 12 V, TJ = 25°C
THERMAL SHUTDOWN
Thermal shutdown
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
fSW
Switching frequency using RT mode
VIN = 12 V
100
Switching frequency
VIN = 12 V, RT = 200 kΩ
450
Switching frequency using CLK mode VIN = 12 V
581
300
Minimum CLK input pulse width
2500
kHz
720
kHz
2200
kHz
40
RT/CLK high threshold
VIN = 12 V
1.9
RT/CLK low threshold
VIN = 12 V
RT/CLK falling edge to PH rising
edge delay
Measured at 500 kHz with RT resistor in series
PLL lock in time
Measured at 500 kHz
0.45
ns
2.2
V
0.7
V
60
ns
100
μs
SLOW START AND TRACKING (SS/TR)
Charge current
VSS/TR = 0.4 V
2
μA
SS/TR-to-VSENSE matching
VSS/TR = 0.4 V
45
mV
SS/TR-to-reference crossover
98% nominal
SS/TR discharge current (overload)
VSENSE = 0 V, V(SS/TR) = 0.4 V
SS/TR discharge voltage
VSENSE = 0 V
1
V
112
μA
54
mV
POWER-GOOD (PWRGD PIN)
VSENSE falling (fault)
VVSENSE
6
VSENSE threshold
92%
VSENSE rising (good)
94%
VSENSE rising (fault)
109%
VSENSE falling (good)
107%
Hysteresis
VSENSE falling
Output high leakage
VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C
On resistance
I(PWRGD) = 3 mA, VSENSE < 0.79 V
Minimum VIN for defined output
V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA
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2%
10
nA
Ω
50
0.95
1.5
V
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0.816
500
VI = 12 V
VI = 12 V
375
Vref - Voltage Reference - V
RDSON - Static Drain-Source On-State Resistance - mW
6.6 Typical Characteristics
BOOT-PH = 3 V
250
BOOT-PH = 6 V
125
0
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 1. On Resistance vs Junction Temperature
0.808
0.800
0.792
0.784
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 2. Voltage Reference vs Junction Temperature
1.1
610
VI = 12 V,
RT = 200 kW
VI = 12 V
fs - Switching Frequency - kHz
600
Switch Current - A
1
0.9
0.8
590
580
570
560
0.7
-50
-25
0
25
50
75
100
125
550
-50
150
-25
0
TJ - Junction Temperature - °C
Figure 3. Switch Current Limit vs Junction Temperature
25
50
75
100
TJ - Junction Temperature - °C
150
Figure 4. Switching Frequency vs Junction Temperature
2500
500
VI = 12 V,
TJ = 25°C
2000
fs - Switching Frequency - kHz
fs - Switching Frequency - kHz
125
1500
1000
500
0
0
25
50
75
100
125
RT/CLK - Resistance - kW
150
175
200
Figure 5. Switching Frequency vs RT/CLK Resistance High
Frequency Range
VI = 12 V,
TJ = 25°C
400
300
200
100
0
200
300
400
500
600 700
800
900
RT/CLK - Resistance - kW
1000 1100
1200
Figure 6. Switching Frequency vs RT/CLK Resistance Low
Frequency Range
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Typical Characteristics (continued)
150
40
VI = 12 V
VI = 12 V
130
110
gm - mA/V
gm - mA/V
30
90
20
70
10
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
50
-50
150
-25
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
Figure 7. EA Transconductance During Slow Start vs
Junction Temperature
Figure 8. EA Transconductance vs Junction Temperature
1.40
-3.25
VI = 12 V,
VI(EN) = Threshold +50 mV
VI = 12 V
-3.5
I(EN) - mA
EN - Threshold - V
1.30
-3.75
1.20
-4
1.10
-50
-25
0
25
50
75
100
125
150
-4.25
-50
-25
0
Figure 9. EN Pin Voltage vs Junction Temperature
75
100
125
150
Figure 10. EN Pin Current vs Junction Temperature
VI = 12 V,
VI(EN) = Threshold -50 mV
VI = 12 V
-0.85
-1.5
I(SS/TR) - mA
I(EN) - mA
50
-1
-0.8
-0.9
-0.95
-2
-2.5
-1
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 11. EN Pin Current vs Junction Temperature
8
25
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
-3
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 12. SS/TR Charge Current vs Junction Temperature
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Typical Characteristics (continued)
120
100
VI = 12 V
VI = 12 V,
TJ = 25°C
80
% of Nominal fsw
II(SS/TR) - mA
115
110
60
40
105
20
100
-50
0
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
0
Figure 13. SS/TR Discharge Current vs Junction
Temperature
0.6
0.8
2
VI = 12 V
TJ = 25°C
1.5
1.5
I(VIN) - mA
I(VIN) - mA
0.4
VSENSE - V
Figure 14. Switching Frequency vs VSENSE
2
1
0.5
1
0.5
0
-50
0
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 15. Shutdown Supply Current vs Junction
Temperature
0
20
VI - Input Voltage - V
30
40
140
o
TJ = 25 C,
VI(VSENSE) = 0.83 V
VI = 12 V,
VI(VSENSE) = 0.83 V
130
120
120
I(VIN) - mA
130
110
100
90
-50
10
Figure 16. Shutdown Supply Current vs Input Voltage (Vin)
140
I(VIN) - mA
0.2
110
100
90
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 17. VIN Supply Current vs Junction Temperature
0
20
VI - Input Voltage - V
40
Figure 18. VIN Supply Current vs Input Voltage
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Typical Characteristics (continued)
115
100
VI = 12 V
PWRGD Threshold - % of Vref
VI = 12 V
RDSON - W
80
60
40
VSENSE Rising
110
VSENSE Falling
105
100
VSENSE Rising
95
VSENSE Falling
90
20
85
-50
0
-50
-25
0
25
50
75
100
125
-25
0
150
25
50
75
100
TJ - Junction Temperature - °C
125
150
TJ - Junction Temperature - °C
Figure 20. PWRGD Threshold vs Junction Temperature
Figure 19. PWRGD ON Resistance vs Junction Temperature
3
2.3
2.1
VI(VIN) - V
VI(BOOT-PH) - V
2.75
2.50
1.9
2.25
1.7
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
2
-50
150
Figure 21. Boot-PH UVLO vs Junction Temperature
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 22. Input Voltage (UVLO) vs Junction Temperature
60
500
V(SS/TR) = 0.2 V
VI = 12 V
VI = 12 V,
o
TJ = 25 C
55
400
Offset - mV
Offset - mV
50
300
200
45
40
100
0
0
35
100
200
300
400
500
600
700
800
30
-50
-25
Figure 23. SS/TR to VSENSE Offset vs VSENSE
10
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
VSENSE - mV
Figure 24. SS/TR to VSENSE Offset vs Temperature
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7 Detailed Description
7.1 Overview
The TPS54040-Q1 device is a 42-V, 0.5-A, step-down (buck) regulator with an integrated high-side N-channel
MOSFET. To improve performance during line and load transients the device implements a constant frequency,
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin.
The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power
switch turn on to a falling edge of an external system clock.
The EN pin of TPS54040-Q1 has an internal pull-up current source to Vin and with EN pin floating, device will
turn on when input voltage reaches approximately 2.5 V. But this undervoltage lockout (UVLO) threshold can be
adjusted with external voltage divider resistors connected to input voltage. The operating current is 116 μA when
not switching and under no load. When the device is disabled, the supply current is 1.3 μA.
The integrated 200-mΩ high-side MOSFET allows for high efficiency power supply designs capable of delivering
0.5 amperes of continuous current to a load. The TPS54040-Q1 reduces the external component count by
integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a
capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the
high-side MOSFET off when the boot voltage falls below a preset threshold. The TPS54040-Q1 can operate at
high duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8-V
reference.
The TPS54040-Q1 has a power-good comparator (PWRGD) which asserts when the regulated output voltage is
less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output
which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage
allowing the pin to transition high when a pull-up resistor is used.
The TPS54040-Q1 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV
power-good comparator. When the OV comparator is activated, the high-side MOSFET is turned off and masked
from turning on until the output voltage is lower than 107%.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor
divider can be coupled to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged
before the output powers up. This discharging ensures a repeatable restart after an overtemperature fault, UVLO
fault or a disabled condition.
The TPS54040-Q1 discharges the slow start capacitor during overload conditions with an overload recovery
circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation
voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during
startup and overcurrent fault conditions to help control the inductor current.
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7.2 Functional Block Diagram
PWRGD
6
EN
3
VIN
2
Shutdown
UV
Thermal
Shutdown
Enable
Comparator
Logic
UVLO
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
ERROR
AMPLIFIER
PWM
Comparator
VSENSE 7
Current
Sense
1 BOOT
Logic
And
PWM Latch
SS/TR 4
Shutdown
Slope
Compensation
10 PH
COMP 8
11 POWERPAD
Frequency
Shift
Overload
Recovery
Maximum
Clamp
Oscillator
with PLL
TPS54040 Block Diagram
9 GND
5
RT/CLK
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54040-Q1 uses an adjustable fixed frequency, peak current mode control. The output voltage is
compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier
which drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error
amplifier output is compared to the high-side power switch current. When the power switch current reaches the
level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease
as the output current increases and decreases. The device implements a current limit by clamping the COMP pin
voltage to a maximum level. The Eco-Mode is implemented with a minimum clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54040-Q1 adds a compensating ramp to the switch current signal. This slope compensation prevents
sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.
7.3.3 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54040-Q1 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT
and PH pins to provide the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when
the high-side MOSFET is off and the low-side diode conducts. The value of this ceramic capacitor should be 0.1
μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended because of the stable characteristics overtemperature and voltage.
12
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Feature Description (continued)
To improve drop out, the TPS54040-Q1 is designed to operate at 100% duty cycle as long as the BOOT to PH
pin voltage is greater than 2.1 V. When the voltage from BOOT to PH drops below 2.1 V, the high-side MOSFET
is turned off using an UVLO circuit which allows the low-side diode to conduct and refresh the charge on the
BOOT capacitor. Since the supply current sourced from the BOOT capacitor is low, the high-side MOSFET can
remain on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the
switching regulator is high.
The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the
power MOSFET, inductor resistance, low-side diode and printed-circuit-board resistance. During operating
conditions in which the input voltage drops and the regulator is operating in continuous conduction mode, the
high-side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT to PH
voltage falls below 2.1 V.
Attention must be taken in maximum duty cycle applications which experience extended time periods with light
loads or no load. When the voltage across the BOOT capacitor falls below the 2.1-V UVLO threshold, the highside MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the
BOOT capacitor. The high-side MOSFET of the regulator stops switching because the voltage across the BOOT
capacitor is less than 2.1 V. The output capacitor then decays until the difference in the input voltage and output
voltage is greater than 2.1 V, at which point the BOOT UVLO threshold is exceeded, and the device starts
switching again until the desired output voltage is reached. This operating condition persists until the input
voltage and/or the load current increases. It is recommended to adjust the VIN stop voltage greater than the
BOOT UVLO trigger condition at the minimum load of the application using the adjustable VIN UVLO feature with
resistors on the EN pin.
The start and stop voltages for typical 3.3-V and 5-V output applications are shown in Figure 25 and Figure 26.
The voltages are plotted versus load current. The start voltage is defined as the input voltage needed to regulate
the output within 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops
switching.
During high duty cycle conditions, the inductor current ripple increases while the BOOT capacitor is being
recharged resulting in an increase in ripple voltage on the output. This is due to the recharge time of the boot
capacitor being longer than the typical high-side OFF-time when switching occurs every cycle.
4
5.6
VO = 3.3 V
VO = 5 V
5.4
VI - Input Voltage - V
VI - Input Voltage - V
3.8
3.6
Start
3.4
Stop
3.2
5.2
Start
5
Stop
4.8
3
4.6
0
0.05
0.10
IO - Output Current - A
0.15
0.20
0
Figure 25. 3.3-V Start and Stop Voltage
0.05
0.10
IO - Output Current - A
0.15
Figure 26. 5-V Start and Stop Voltage
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Feature Description (continued)
7.3.4 Error Amplifier
The TPS54040-Q1 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The
transconductance (gm) of the error amplifier is 97 μA/V during normal operation. During the slow start operation,
the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below 0.8
V and the device is regulating using the SS/TR voltage, the gm is 25 μA/V.
The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin
to ground.
7.3.5 Voltage Reference
The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit.
7.3.6 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use 1% tolerance or better divider resistors. Start with a 10 kΩ for the R2 resistor and use the Equation 1 to
calculate R1. To improve efficiency at light loads consider using larger value resistors. If the values are too high
the regulator will be more susceptible to noise and voltage errors from the VSENSE input current will be
noticeable
æ Vout - 0.8V ö
R1 = R2 ´ ç
÷
0.8 V
è
ø
(1)
7.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54040-Q1 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by using
the two external resistors. Though it is not necessary to use the UVLO adjust resistors, for operation it is highly
recommended to provide consistent power up behavior. The EN pin has an internal pull-up current source, I1, of
0.9 μA that provides the default condition of the TPS54040-Q1 operating when the EN pin floats. Once the EN
pin voltage exceeds 1.25 V, an additional 2.9 μA of hysteresis, IHYS, is added. This additional current facilitates
input voltage hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use Equation 3 to
set the input start voltage.
TPS54040
VIN
Ihys
I1
0.9 mA
R1
2.9 mA
+
R2
EN
1.25 V
-
Figure 27. Adjustable Undervoltage Lockout (UVLO)
V
- VSTOP
R1 = START
IHYS
(2)
SPACE
14
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Feature Description (continued)
R2 =
VENA
VSTART - VENA
+ I1
R1
(3)
Another technique to add input voltage hysteresis is shown in Figure 28. This method may be used, if the
resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3
sources additional hysteresis current into the EN pin.
TPS54040
VIN
R1
Ihys
I1
0.9 mA
2.9 mA
+
R2
EN
1.25 V
R3
-
VOUT
Figure 28. Adding Additional Hysteresis
R1 =
VSTART - VSTOP
V
IHYS + OUT
R3
(4)
SPACE
R2 =
VENA
VSTART - VENA
V
+ I1 - ENA
R1
R3
(5)
7.3.8 Slow Start/Tracking Pin (SS/TR)
The TPS54040-Q1 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage
as the reference voltage of the power-supply and regulates the output accordingly. A capacitor on the SS/TR pin
to ground implements a slow start time. The TPS54040-Q1 has an internal pull-up current source of 2 μA that
charges the external slow start capacitor. The calculations for the slow start time (10% to 90%) are shown in
Equation 6. The voltage reference (VREF) is 0.8 V and the slow start current (ISS) is 2 μA. The slow start capacitor
should remain lower than 0.47 μF and greater than 0.47 nF.
Tss(ms) ´ Iss(m A)
Css(nF) =
Vref (V) ´ 0.8
(6)
At power up, the TPS54040-Q1 will not start switching until the slow start pin is discharged to less than 40 mV to
ensure a proper power up, see Figure 29.
Also, during normal operation, the TPS54040-Q1 will stop switching and the SS/TR must be discharged to 40
mV, when the VIN UVLO is exceeded, EN pin pulled below 1.25 V, or a thermal shutdown event occurs.
The VSENSE voltage will follow the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage
reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as
the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see
Figure 23). The SS/TR voltage will ramp linearly until clamped at 1.7 V.
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Feature Description (continued)
EN
SS/TR
VSENSE
VOUT
Figure 29. Operation of SS/TR Pin When Starting
7.3.9 Overload Recovery Circuit
The TPS54040-Q1 has an overload recovery (OLR) circuit. The OLR circuit will slow start the output from the
overload voltage to the nominal regulation voltage once the fault condition is removed. The OLR circuit will
discharge the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pull down of
100 μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is
removed, the output will slow start from the fault voltage to nominal output voltage.
7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54040-Q1 is adjustable over a wide range from approximately 100 kHz to
2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a
resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 7 or the curves in Figure 30 or Figure 31. To reduce the solution size one would
typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input
voltage and minimum controllable on time should be considered.
The minimum controllable on time is typically 130 ns and limits the maximum operating input voltage.
The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of
the maximum switching frequency is located below.
206033
RT (kOhm ) =
¦ sw (kHz )1.0888
(7)
16
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Feature Description (continued)
2500
500
2000
fs - Switching Frequency - kHz
fs - Switching Frequency - kHz
VI = 12 V,
TJ = 25°C
1500
1000
500
0
0
25
50
75
100
125
150
RT/CLK - Clock Resistance - kW
175
200
Figure 30. Switching Frequency vs RT/CLK Resistance
High Frequency Range –High Range RT
VI = 12 V,
TJ = 25°C
400
300
200
100
0
200
300
400
500
600 700
800
900
RT/CLK - Resistance - kW
1000 1100
1200
Figure 31. Switching Frequency vs RT/CLK Resistance
Low Frequency Range –Low Range RT
7.3.11 Overcurrent Protection and Frequency Shift
The TPS54040-Q1 implements current mode control which uses the COMP pin voltage to turn off the high- side
MOSFET on a cycle by cycle basis. Each cycle the switch current and COMP pin voltage are compared, when
the peak switch current intersects the COMP voltage, the high-side switch is turned off. During overcurrent
conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high,
increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current
limit.
To increase the maximum operating switching frequency at high input voltages the TPS54040-Q1 implements a
frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on
VSENSE pin.
The device implements a digital frequency shift to enable synchronizing to an external clock during normal
startup and fault conditions. Since the device can only divide the switching frequency by 8, there is a maximum
input voltage limit in which the device operates and still have frequency shift protection.
During short-circuit events (particularly with high input voltage applications), the control loop has a finite minimum
controllable on time and the output has a low voltage. During the switch on time, the inductor current ramps to
the peak current limit because of the high input voltage and minimum on time. During the switch off time, the
inductor would normally not have enough off time and output voltage for the inductor to ramp down by the ramp
up amount. The frequency shift effectively increases the off time allowing the current to ramp down.
7.3.12 Selecting the Switching Frequency
The switching frequency that is selected should be the lower value of the two equations, Equation 8 and
Equation 9. Equation 8 is the maximum switching frequency limitation set by the minimum controllable on time.
Setting the switching frequency above this value will cause the regulator to skip switching pulses.
Equation 9 is the maximum switching frequency limit set by the frequency shift protection. To have adequate
output short circuit protection at high input voltages, the switching frequency should be set to be less than the
ƒSW(maxshift) frequency. In Equation 9, to calculate the maximum switching frequency one must take into account
that the output voltage decreases from the nominal voltage to 0 V, the ƒDIV integer increases from 1 to 8
corresponding to the frequency shift.
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Feature Description (continued)
In Figure 32, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the
output voltage is zero volts, and the resistance of the inductor is 0.130 Ω, FET on resistance of 0.2 Ω and the
diode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter
these equations in a spreadsheet or other software or use the SwitcherPro design software to determine the
switching frequency.
æ 1 ö æ (IL ´ Rdc + VOUT + Vd) ö
fSW (max skip ) = ç
÷
÷ ´ çç
÷
è tON ø è (VIN - IL ´ Rhs + Vd) ø
(8)
SPACE
fSW (hift ) =
fdiv æ (IL ´ Rdc + VOUTSC + Vd) ö
´ç
÷
t ON çè (VIN - IL x Rhs + Vd ) ÷ø
(9)
IL
inductor current
Rdc
inductor resistance
VIN
maximum input voltage
VOUT
output voltage
VOUTSC
output voltage during short
Vd
diode voltage drop
RDS(ON)
switch on resistance
tON
controllable on time
ƒDIV
frequency divide equals (1, 2, 4, or 8)
fs - Switching Frequency - kHz
2500
Skip
2000
1500
Shift
1000
500
VO = 5.0 V
0
10
20
30
VI - Input Voltage - V
40
Figure 32. Maximum Switching Frequency vs. Input Voltage
7.3.13 Power-good (PWRGD Pin)
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal
voltage reference the PWRGD pin is deasserted and the pin floats. It is recommended to use a pullup resistor
between the values of 1 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined
state once the VIN input voltage is greater than 1.5 V but with reduced current sinking capability. The PWRGD
will achieve full current sinking capability as VIN input voltage approaches 3 V.
The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin
pulled low.
18
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Feature Description (continued)
7.3.14 Overvoltage Transient Protection
The TPS54040-Q1 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients on power supply designs with low value
output capacitance. For example, when the power supply output is overloaded the error amplifier compares the
actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal
reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error
amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed,
the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In some
applications, the power supply output voltage can respond faster than the error amplifier output can respond, this
actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when
using a low value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP
threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP
threshold, the high-side MOSFET is disabled preventing current from flowing to the output and minimizing output
overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET is allowed
to turn on at the next clock cycle.
7.3.15 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 182°C, the device reinitiates the power up sequence
by discharging the SS/TR pin.
7.3.16 Small Signal Model for Loop Response
Figure 33 shows an equivalent model for the TPS54040-Q1 control loop which can be modeled in a circuit
simulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gmEA of 97 μA/V. The error amplifier can be modeled using an ideal voltage
controlled current source. The resistor Ro and capacitor Co model the open loop gain and frequency response of
the amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the control loop for the
frequency response measurements. Plotting c/a shows the small signal response of the frequency compensation.
Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by
replacing RL with a current source with the appropriate load step amplitude and step rate in a time domain
analysis. This equivalent model is only valid for continuous conduction mode designs.
PH
VO
Power Stage
gmps 1.9 A/V
a
b
RESR
R1
RL
COMP
c
0.8 V
R3
CO
C2
RO
VSENSE
COUT
gmea
97 mA/V
R2
C1
Figure 33. Small Signal Model for Loop Response
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Feature Description (continued)
7.3.17 Simple Small Signal Model for Peak Current Mode Control
Figure 34 describes a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54040-Q1 power stage can be approximated to a voltage-controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 10 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 33) is the power stage
transconductance. The gmPS for the TPS54040-Q1 is 1.9 A/V. The low-frequency gain of the power stage
frequency response is the product of the transconductance and the load resistance as shown in Equation 11.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 12). The combined effect is highlighted by the dashed line in the right half of
Figure 34. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions which makes it easier to design the frequency
compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on
the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number
frequency compensation components needed to stabilize the overall loop because the phase margin increases
from the ESR zero at the lower frequencies (see Equation 13).
VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 34. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
VOUT
VC
æ
s
ç1 +
2
p
´ fZ
= Adc ´ è
æ
s
ç1 +
2p ´ fP
è
ö
÷
ø
ö
÷
ø
(10)
SPACE
Adc = gmps ´ RL
(11)
SPACE
fP =
1
COUT ´ RL ´ 2p
(12)
1
COUT ´ RESR ´ 2p
(13)
SPACE
fZ =
20
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Feature Description (continued)
7.3.18 Small Signal Model for Frequency Compensation
The TPS54040-Q1 uses a transconductance amplifier for the error amplifier and readily supports three of the
commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are
shown in Figure 35. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low
ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum
electrolytic or tantalum capacitors.. Equation 14 and Equation 15 show how to relate the frequency response of
the amplifier to the small signal model in Figure 35. The open-loop gain and bandwidth are modeled using the RO
and CO shown in Figure 35. See the application section for a design example using a Type 2A network with a
low ESR output capacitor.
Equation 14 through Equation 23 are provided as a reference for those who prefer to compensate using the
preferred methods. Those who prefer to use prescribed method use the method outlined in the application
section or use switched information.
VO
R1
VSENSE
gmea
Type 2A
COMP
Type 2B
Type 1
Vref
R2
RO
R3
CO
C2
C1
R3
C2
C1
Figure 35. Types of Frequency Compensation
Aol
A0
P1
Z1
P2
A1
BW
Figure 36. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Ro =
Aol(V/V)
gmea
(14)
gmea
2p ´ BW (Hz)
(15)
SPACE
CO =
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Feature Description (continued)
SPACE
æ
ö
s
ç1 +
÷
2p ´ fZ1 ø
è
EA = A0 ´
æ
ö æ
ö
s
s
ç1 +
÷ ´ ç1 +
÷
2p ´ fP1 ø è
2p ´ fP2 ø
è
(16)
SPACE
A0 = gmea ´ Ro ´
R2
R1 + R2
(17)
SPACE
A1 = gmea ´ Ro| | R3 ´
R2
R1 + R2
(18)
SPACE
P1 =
1
2p ´ Ro ´ C1
(19)
SPACE
Z1 =
1
2p ´ R3 ´ C1
(20)
SPACE
P2 =
1
type 2a
2p ´ R3 | | RO ´ (C2 + CO )
(21)
1
type 2b
2p ´ R3 | | RO ´ CO
(22)
1
type 1
2 p ´ R O ´ (C2 + C O )
(23)
SPACE
P2 =
SPACE
P2 =
7.4 Device Functional Modes
7.4.1 Pulse-Skip Eco-Mode
The TPS54040-Q1 operates in a pulse-skip Eco-Mode at light load currents to improve efficiency by reducing
switching and gate drive losses. The TPS54040-Q1 is designed so that if the output voltage is within regulation
and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the
device enters Eco-Mode. This current threshold is the current level corresponding to a nominal COMP voltage or
500 mV.
When in Eco-Mode, the COMP pin voltage is clamped at 500 mV and the high-side MOSFET is inhibited. Further
decreases in load current or in output voltage can not drive the COMP pin below this clamp voltage level.
Since the device is not switching, the output voltage begins to decay. As the voltage control loop compensates
for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high-side MOSFET is enabled
and a switching pulse initiates on the next switching cycle. The peak current is set by the COMP pin voltage. The
output voltage re-charges the regulated value (see Figure 37), then the peak switch current starts to decrease,
and eventually falls below the Eco-Mode threshold at which time the device again enters Eco-Mode.
22
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Device Functional Modes (continued)
For Eco-Mode operation, the TPS54040-Q1 senses peak current, not average or load current, so the load
current where the device enters Eco-Mode is dependent on the output inductor value. For example, the circuit in
Figure 50 enters Eco-Mode at about 20 mA of output current. When the load current is low and the output
voltage is within regulation, the device enters a sleep mode and draws only 116-μA input quiescent current. The
internal PLL remains operating when in sleep mode. When operating at light load currents in the pulse skip
mode, the switching transitions occur synchronously with the external clock signal.
VOUT(ac)
IL
PH
Figure 37. Pulse Skip Mode Operation
7.4.2 External Clock Synchronization Using RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in
Figure 38. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin
and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range
is 300 kHz to 2200 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal.
The external synchronization circuit should be designed in such a way that the device will have the default
frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is
recommended to use a frequency set resistor connected as shown in Figure 38 through a 50-Ω resistor to
ground. The resistor should set the switching frequency close to the external CLK frequency. It is recommended
to ac couple the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin and a 4-kΩ series
resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock
and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the
CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage
source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal.
Since there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with
the external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or
decrease the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds.
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Device Functional Modes (continued)
When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK
frequency to 150 kHz, then reapply the 0.5-V voltage and the resistor will then set the switching frequency. The
switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The
device implements a digital frequency shift to enable synchronizing to an external clock during normal startup
and fault conditions. Figure 39, Figure 40 and Figure 41 show the device synchronized to an external system
clock in continuous conduction mode (CCM) discontinuous conduction (DCM) and pulse skip mode (PSM).
TPS54040
10 pF
4 kW
PLL
Rfset
EXT
Clock
Source
50 W
RT/CLK
Figure 38. Synchronizing to a System Clock
PH
PH
EXT
EXT
IL
IL
Figure 39. Plot of Synchronizing in CCM
24
Figure 40. Plot of Synchronizing in DCM
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Device Functional Modes (continued)
PH
EXT
IL
Figure 41. Plot of Synchronizing in PSM
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54040-Q1 device is a wide input voltage (3.5 V to 42 V), step-down, DC-DC converter with an
adjustable output voltage and an output current of up to 0.5 A. Switching frequency is adjustable between 100kHz to 2.5-MHz and hence efficiency and external component size can be optimized for each application.
8.1.1 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins. The sequential method can be implemented using an open drain output of a power-on reset pin of another
device. The sequential method is illustrated in Figure 42 using two TPS54040-Q1 devices. The power-good is
coupled to the EN pin on the TPS54040-Q1 which will enable the second power supply once the primary supply
reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply will provide a
1-ms start-up delay. Figure 43 shows the results of Figure 42.
TPS54040
EN
PWRGD
EN
EN1
SS /TR
SS /TR
PWRGD1
PWRGD
VOUT1
VOUT2
Figure 42. Schematic for Sequential Start-Up
Sequence
26
Figure 43. Sequential Start-Up Using EN and
PWRGD
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Application Information (continued)
TPS54160
TPS54040
3
EN
4
SS/TR
6
PWRGD
EN1, EN2
VOUT1
TPS54040
TPS54160
VOUT2
3
EN
4
SS/TR
6
PWRGD
Figure 44. Schematic for Ratiometric Start-up
Using Coupled SS/TR Pins
Figure 45. Ratiometric Start-up Using Coupled
SS/TR Pins
Figure 44 shows a method for ratiometric start-up sequence by connecting the SS/TR pins together. The
regulator outputs will ramp up and reach regulation at the same time. When calculating the slow start time the
pullup current source must be doubled in Equation 6. Figure 45 shows the results of Figure 44.
TPS54040
EN
VOUT 1
SS/TR
PWRGD
TPS54040
VOUT 2
EN
R1
SS/ TR
R2
PWRGD
R3
R4
Figure 46. Schematic for Ratiometric and Simultaneous Start-up Sequence
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Application Information (continued)
Ratiometric and simultaneous power-supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 46 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 24 and Equation 25, the tracking resistors can be calculated to initiate the
VOUT2 slightly before, after or at the same time as VOUT1. Equation 26 is the voltage difference between VOUT1
and VOUT2 at the 95% of nominal output regulation.
The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
VSENSE offset (VSSOFFSET) in the slow start circuit and the offset created by the pullup current source (ISS) and
tracking resistors, the VSSOFFSET and ISS are included as variables in the equations.
To design a ratiometric start-up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2
reaches regulation, use a negative number in Equation 24 through Equation 26 for ΔV. Equation 26 will result in
a positive number for applications which the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved.
Since the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO or thermal shutdown fault,
careful selection of the tracking resistors is needed to ensure the device will restart after a fault. Make sure the
calculated R1 value from Equation 24 is greater than the value calculated in Equation 27 to ensure the device
can recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage the VSSOFFSET becomes larger
as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR
pin voltage needs to be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in
Figure 23.
Vout2 + deltaV
Vssoffset
R1 =
´
VREF
Iss
(24)
SPACE
R2 =
VREF ´ R1
Vout2 + deltaV - VREF
(25)
SPACE
deltaV = Vout1 - Vout2
(26)
SPACE
R1 > 2800 ´ Vout1 - 180 ´ deltaV
(27)
28
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Application Information (continued)
EN
EN
VOUT1
VOUT1
VOUT2
Figure 47. Ratiometric Start-up With VOUT2 Leading VOUT1
VOUT2
Figure 48. Ratiometric Start-Up with VOUT1 Leading VOUT2
EN
VOUT1
VOUT2
Figure 49. Simultaneous Start-up With Tracking Resistor
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8.2 Typical Application
Figure 50. High Frequency, 3.3-V Output Power Supply Design With Adjusted UVLO
8.2.1 Design Requirements
The input voltage for this device must be from 3.5 V to 42 V. The output voltage must be set using an external
voltage divider. Schottky diode must be used at PH pin to GND as there is no integrated recirculation path in the
device. Switching frequency has to be set as per the requirement by calculating pull down resistor value at
RT/CLK pin. Compensation network component have to be calculated as explained in Detailed Design
Procedure. Low-ESR ceramic capacitors should be used at the input and output for better filtering and ripple
performance and effective input capacitance has to be at least 3 uF.
The Detailed Design Procedure section provides the necessary equations and guidelines for selecting external
components for this regulator.
8.2.2 Detailed Design Procedure
This example details the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These parameters are typically determined at the
system level. Table 1 shows the known parameters for this example.
Table 1. Known Parameters for This Regulator Design
Example
30
PARAMETER
VALUE
Output Voltage
5V
Transient Response 0 to 1.5A
load step
ΔVOUT = 4%
Maximum Output Current
0.5 A
Input Voltage
34 V nom. 12 V to 42 V
Output Voltage Ripple
1% of VOUT
Start Input Voltage (rising VIN)
8.9 V
Stop Input Voltage (falling VIN)
7.9 V
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8.2.2.1 Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the
highest switching frequency possible since this will produce the smallest solution size. The high switching
frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that
switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of
the internal power switch, the input voltage and the output voltage and the frequency shift limitation.
Equation 8 and Equation 9 must be used to find the maximum switching frequency for the regulator, choose the
lower value of the two equations. Switching frequencies higher than these values will result in pulse skipping or
the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 130 ns for the TPS54040-Q1. For this example, the output voltage is 5 V
and the maximum input voltage is 42 V, which allows for a maximum switch frequency up to 1012 kHz when
including the inductor resistance, on resistance and diode voltage in Equation 8. To ensure overcurrent runaway
is not a concern during short circuits in your design use Equation 9 or the solid curve in Figure 32 to determine
the maximum switching frequency. With a maximum input voltage of 42 V, assuming a diode voltage of 0.5 V,
inductor resistance of 130 mΩ, switch resistance of 400 mΩ, a current limit value of 0.94 A and a short circuit
output voltage of 0.1 V. The maximum switching frequency is approximately 1055 kHz.
Choosing the lower of the two values and adding some margin a switching frequency of 700 kHz is used. To
determine the timing resistance for a given switching frequency, use Equation 7 or the curve in Figure 30.
The switching frequency is set by resistor R3 shown in Figure 50.
8.2.2.2 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 28.
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high inductor ripple
currents will impact the selection of the output capacitor since the output capacitor must have a ripple current
rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion
of the designer; however, the following guidelines may be used.
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is
part of the PWM control system, the inductor ripple current should always be greater than 30 mA for dependable
operation. In a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side. This
allows the inductor to still have a measurable ripple current with the input voltage at its minimum.
For this design example, use KIND = 0.3 and the minimum inductor value is calculated to be 42 μH. For this
design, a nearest standard value was chosen: 47 μH. For the output filter inductor, it is important that the RMS
current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 30 and Equation 31.
For this design, the RMS inductor current is 0.501 A and the peak inductor current is 0.567 A. The chosen
inductor is a MSS1048-473ML. It has a saturation current rating of 1.44 A and an RMS current rating of 1.83 A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
Vinmax - Vout
Vout
Lo min =
´
Io ´ KIND
Vinmax ´ ƒsw
(28)
SPACE
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IRIPPLE =
VOUT ´
(Vin max
www.ti.com
- VOUT )
Vin max ´ L O ´ fSW
(29)
SPACE
IL(rms) =
(IO ) +
2
1 æ VOUT ´ (Vinmax - VOUT ) ö
´ç
÷
÷
12 çè
Vinmax ´ LO ´ fSW
ø
2
(30)
SPACE
ILpeak = Iout +
Iripple
2
(31)
8.2.2.3 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor will
determine the modulator pole, the output voltage ripple, and how the regulators responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator also will temporarily not be able to
supply sufficient output current if there is a large, fast increase in the current needs of the load such as
transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop
to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output
capacitor must be sized to supply the extra current to the load until the control loop responds to the load change.
The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only
allowing a tolerable amount of droop in the output voltage. Equation 32 shows the minimum output capacitance
necessary to accomplish this.
Where ΔIOUT is the change in output current, ƒsw is the regulators switching frequency and ΔVOUT is the allowable
change in the output voltage. For this example, the transient load response is specified as a 4% change in VOUT
for a load step from 0 A (no load) to 0.5 A (full load). For this example, ΔIOUT = 0.5-0 = 0.5 A and ΔVOUT = 0.04 ×
5 = 0.2 V. Using these numbers gives a minimum capacitance of 7.14 μF. This value does not take the ESR of
the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small
enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should
be taken into account.
The catch diode of the regulator can not sink current so any stored energy in the inductor will produce an output
voltage overshoot when the load current rapidly decreases, see Figure 51. The output capacitor must also be
sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current.
The excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. The
capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 33 is
used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where L is
the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the
final peak output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step will be
from 0.5 A to 0 A. The output voltage will increase during this load transition and the stated maximum in our
specification is 4% of the output voltage. This will make Vf = 1.04 × 5 = 5.2 V. Vi is the initial capacitor voltage
which is the nominal output voltage of 5 V. Using these numbers in Equation 33 yields a minimum capacitance of
5.7 μF.
Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where ƒsw is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. Equation 34 yields 0.49 μF.
Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 35 indicates the ESR should be less than 248 mΩ.
The most stringent criteria for the output capacitor is 7.14 μF of capacitance to keep the output voltage in
regulation during an load transient.
32
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Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which will increase
this minimum value. For this example, a 47-μF 10-V X5R ceramic capacitor with 5 mΩ of ESR will be used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 36 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 36 yields
39 mA.
2 ´ DIout
Cout >
¦ sw ´ DVout
(32)
SPACE
((I ) - (I ) )
´
((V ) - (V ) )
2
OH
COUT > LO
2
OL
2
f
2
i
(33)
SPACE
Cout >
1
8 ´ ¦ sw
´
(
1
VORIPPLE
IRIPPLE
)
(34)
SPACE
V
RESR < ORIPPLE
IRIPPLE
(35)
SPACE
Icorms =
Vout ´ (Vin max - Vout)
12 ´ Vin max ´ Lo ´ ¦ sw
(36)
8.2.2.4 Catch Diode
The TPS54040-Q1 requires an external catch diode between the PH pin and GND. The selected diode must
have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be
greater than the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes
are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of
the diode, the higher the efficiency of the regulator.
Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage will be. Since
the design example has an input voltage up to 42 V, a diode with a minimum of 42-V reverse voltage will be
selected.
For the example design, the B160A Schottky diode is selected for its lower forward voltage and it comes in a
larger package size which has good thermal characteristics over small devices. The typical forward voltage of the
B160A is 0.50 volts.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies,
the ac losses of the diode need to be taken into account. The ac losses of the diode are due to the charging and
discharging of the junction capacitance and reverse recovery. Equation 37 is used to calculate the total power
dissipation, conduction losses plus ac losses, of the diode.
The B160A has a junction capacitance of 110 pF. Using Equation 37, the selected diode will dissipate 0.290
Watts. This power dissipation, depending on mounting techniques, should produce a 5.9°C temperature rise in
the diode when the input voltage is 42 V and the load current is 0.5 A.
If the power supply spends a significant amount of time at light load currents or in sleep mode consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
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2
Pd =
(Vin max - Vout) ´ Iout ´ Vƒd Cj ´ ƒsw ´ (Vin + Vƒd)
+
2
Vin max
(37)
8.2.2.5 Input Capacitor
The TPS54040-Q1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF
of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc
bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54040Q1. The input ripple current can be calculated using Equation 38.
The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor
decreases as the dc bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 60-V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V or 100 V so a 100-V capacitor should be selected. For this example, two 2.2-μF, 100-V capacitors in
parallel have been selected. The input capacitance value determines the input ripple voltage of the regulator. The
input voltage ripple can be calculated using Equation 39. Using the design example values, IOUT(max) = 0.5 A, CIN
= 4.4 μF, ƒsw = 500 kHz, yields an input voltage ripple of 40.6 mV and an RMS input ripple current of 0.247 A.
Icirms = Iout ´
Vout
´
Vin min
(Vin min
- Vout )
Vin min
(38)
SPACE
ΔVin =
Iout max ´ 0.25
Cin ´ ¦ sw
(39)
8.2.2.6 Slow Start Capacitor
The slow start capacitor determines the minimum amount of time it will take for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is large and would require large amounts of current to quickly charge the
capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54040-Q1 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, TSS,
necessary to charge the output capacitor, COUT, from 10% to 90% of the output voltage, VOUT, with an average
slow start current of ISSAVG. In the example, to charge the 47-μF output capacitor up to 5 V while only allowing
the average input current to be 0.125 A would require a 1.5-ms slow start time.
Once the slow start time is known, the slow start capacitor value can be calculated using Equation 6. For the
example circuit, the slow start time is not too critical since the output capacitor value is 47 μF which does not
require much current to charge to 5 V. The example circuit has the slow start time set to an arbitrary value of 3.2
ms which requires a 0.01-μF capacitor.
SPACE
Tss >
Cout ´ Vout ´ 0.8
Issavg
(40)
8.2.2.7 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V
or higher voltage rating.
34
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8.2.2.8 Undervoltage Lockout Set Point
The undervoltage lock out (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54040-Q1. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. For the example design, the supply should turn on
and start switching once the input voltage increases above 8.9 V (enabled). After the regulator starts switching, it
should continue to do so until the input voltage falls below 7.9 V (UVLO stop).
The programmable UVLO and enable voltages are set using a resistor divider between VIN and ground to the EN
pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example
application, a 332 kΩ between VIN and EN and a 56.2 kΩ between EN and ground are required to produce the
8.9- and 7.9-V start and stop voltages.
8.2.2.9 Output Voltage and Feedback Resistors Selection
For the example design, 10 kΩ was selected for R2. Using Equation 1, R1 is calculated as 52.5 kΩ. The nearest
standard 1% resistor is 52.3 kΩ. Due to current leakage of the VSENSE pin, the current flowing through the
feedback network should be greater than 1 μA in order to maintain the output voltage accuracy. This requirement
makes the maximum value of R2 equal to 800 kΩ. Choosing higher resistor values will decrease quiescent
current and improve efficiency at low output currents but may introduce noise immunity problems.
8.2.2.10 Compensation
There are several methods used to compensate DC/DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual cross over frequency will usually be lower than the cross over frequency
used in the calculations. This method assume the crossover frequency is between the modulator pole and the
ESR zero and the ESR zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more
accurate design.
To get started, the modulator pole, fpmod, and the ESR zero, fz1 must be calculated using Equation 41 and
Equation 42. For COUT, use a derated value of 21.2 μf. Use equations Equation 43 and Equation 44, to estimate
a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is 753
Hz and fzmod is 1505 kHz. Equation 43 is the geometric mean of the modulator pole and the ESR zero and
Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 33.7 kHz and
Equation 44 gives 16.2 kHz. Use the lower value of Equation 43 or Equation 44 for an initial crossover frequency.
For this example, fco is 16.2 kHz. Next, the compensation components are calculated. A resistor in series with a
capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the
compensating pole.
Ioutmax
¦p mod =
2 × p × Vout × Cout
(41)
SPACE
¦ z mod =
1
2 ´ p ´ Resr × Cout
(42)
SPACE
fco =
f p mod ´ f z mod
(43)
SPACE
fco =
f p mod ´
f sw
2
(44)
To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance,
gmps, is 1.9A/V. The output voltage, VOUT, reference voltage, VREF, and amplifier transconductance, gmEA, are
3.3 V, 0.8 V and 97 μA/V, respectively. R4 is calculated to be 77.1 kΩ, use the nearest standard value of 76.8
kΩ. Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 2754 pF
for compensating capacitor C5, a 2700 pF is used on the board.
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æ 2 ´ p ´ fco ´ Cout
R4 = ç
gmps
è
www.ti.com
ö
ö æ
Vout
÷
÷´ç
´
V
gmea
ø è ref
ø
1
C5 =
2 ´ p ´ R4 ´ f p m od
(45)
(46)
Use the larger value of Equation 47 and Equation 48 to calculate the C6, to set the compensation pole.
Equation 48 yields 5.9 pF so the nearest standard of 5.6 pF is used.
C6 =
C o ´ Re sr
R4
(47)
1
C6 =
R4 ´ f sw ´ p
(48)
8.2.2.11 Discontinuous Mode and Eco-Mode Boundary
With an input voltage of 34 V, the power supply enters discontinuous mode when the output current is less than
50 mA. The power supply enters Eco-Mode when the output current is lower than 30 mA.
The input current draw at no load is 235 μA.
36
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8.2.3 Application Curves
Figure 51. Load Transient
Figure 52. Startup With VIN
Figure 53. Output Ripple CCM
Figure 54. Output Ripple, DCM
Figure 55. Output Ripple, PSM
Figure 56. Input Ripple CCM
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100
90
80
VIN = 24 V
70
VIN = 15 V
VIN = 12 V
Efficiency - %
VIN = 34 V
60
VIN = 42
50
40
30
20
10
VOUT = 5.0 V
0
0
0.05
Figure 57. Input Ripple DCM
0.10
0.15
0.20 0.25 0.30 0.35
IO - Output Current - A
0.40
0.45
0.50
Figure 58. Efficiency vs Load Current
100
60
180
40
120
150
90
80
Phase
90
70
Vin = 15 V
Vin = 34 V
50
Vin = 12 V
30
Gain - dB
Efficiency - %
60
Vin = 24 V
Vin = 42 V
40
Gain
0
0
-30
-60
-20
30
Phase - o
60
20
-90
20
-40
-120
-60
-180
VOUT = 5.0 V
10
0
0
0.02
0.04
0.06
IO - Output Current - A
-150
0.10
0.08
1-103
100
Figure 59. Light Load Efficiency
0.1
0.04
0.04
Regulation (%)
Regulation (%)
IO = 0.2 A
0.06
0.02
0
-0.02
0.02
0
-0.02
-0.04
-0.04
-0.06
-0.06
-0.08
-0.08
-0.1
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
12
18
24
30
36
42
VI - Input Voltage - V
Load Current - A
Figure 61. Regulation vs Load Current
38
1-106
0.08
VI = 24 V
0.06
-0.1
0.00
1-105
Figure 60. Overall Loop Frequency Response
0.1
0.08
1-104
f - Frequency - Hz
Figure 62. Regulation vs Input Voltage
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9 Power Supply Recommendations
The TPS54040-Q1 device is designed to operate from an input voltage up to 42 V. The TPS54040-Q1 requires a
high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF of effective capacitance and in
some applications a bulk capacitance. Capacitance derating for aging, temperature, and DC bias must be taken
into account while determining the capacitor value.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signals paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed
to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch
diode. See Figure 63 for a PCB layout example. The GND pin should be tied directly to the PowerPAD under the
IC.
The PowerPAD should be connected to any internal PCB ground planes using multiple vias directly under the IC.
The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH
connection is the switching node, the catch diode and output inductor should be located close to the PH pins,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling. PH and Vin traces
should be wide to minimize the trace inductance. For operation at full rated load, the top side ground area must
provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT resistor should be
located as close as possible to the IC and routed with minimal lengths of trace. The additional external
components can be placed approximately as shown. It may be possible to obtain acceptable performance with
alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.
10.2 Layout Example
Vout
Output
Capacitor
Topside
Ground
Area
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
Input
Bypass
Capacitor
BOOT
Vin
UVLO
Adjust
Resistors
Slow Start
Capacitor
Output
Inductor
Catch
Diode
PH
VIN
GND
EN
COMP
SS/TR
VSENSE
RT/CLK
PWRGD
Frequency
Set Resistor
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Figure 63. PCB Layout Example
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10.3 Power Dissipation Estimate
The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM)
operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM).
The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and
supply current (Pq).
Vout
Pcon = Io2 ´ RDS(on) ´
Vin
(49)
SPACE
Psw = Vin 2 ´ ¦ sw ´ lo ´ 0.25 ´ 10-9
(50)
SPACE
Pgd = Vin ´ 3 ´ 10 -9 ´ ¦ sw
(51)
SPACE
Pq = 116 ´ 10-6 ´ Vin
(52)
Where:
IOUT is the output current (A).
RDS(ON) is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
ƒsw is the switching frequency (Hz).
So
Ptot = Pcon + Psw + Pgd + Pq
(53)
For given TA,
TJ = TA + Rth ´ Ptot
(54)
For given TJMAX = 150°C
TAmax = TJmax - Rth ´ Ptot
(55)
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
Rth is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and trace resistance that will impact the overall efficiency of the regulator.
10.4 Estimated Circuit Area
The estimated printed circuit board area for the components used in the design of Figure 50 is 0.55 in2. This area
does not include test points or connectors.
40
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Estimated Circuit Area (continued)
VIN
+
CIN
Cboot
Lo
BOOT
VIN
PH
GND
R1
Cd
+ Co
GND
R2
VOUT
VSENSE
EN
SS/TR
COMP
Rcomp
RT/CLK
Css
Cpole
RT
Czero
Figure 64. 24 V to –12 V Inverting Power Supply from SLVA317 Application Note
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For the SwitcherPro™ Software Tool, go to http://focus.ti.com/docs/toolsw/folders/print/switcherpro.html.
11.2 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
Eco-Mode, SwitcherPro, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Feb-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS54040QDGQRQ1
OBSOLETE
Package Type Package Pins Package
Drawing
Qty
MSOPPowerPAD
DGQ
10
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
5404Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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1-Feb-2017
OTHER QUALIFIED VERSIONS OF TPS54040-Q1 :
• Catalog: TPS54040
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
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