ADG732BCP

a 16-/32-Channel, 4
+1.8 V to +5.5 V, 2.5 V Analog Multiplexers ADG726/ADG732 FEATURES 1.8 V to 5.5 V Single Supply 2.5 V Dual-Supply Operation 4
On Resistance 0.5
On Resistance Flatness 48-Lead TQFP or 48-Lead 7 mm  7 mm CSP Packages Rail-to-Rail Operation 30 ns Switching Times Single 32-to-1 Channel Multiplexer Dual/Differential 16-to-1 Channel Multiplexer TTL/CMOS Compatible Inputs For Functionally Equivalent Devices with Serial Interface See ADG725/ADG731 APPLICATIONS Optical Applications Data Acquisition Systems Communication Systems Relay Replacement Audio and Video Switching Battery-Powered Systems Medical Instrumentation Automatic Test Equipment FUNCTIONAL BLOCK DIAGRAMS ADG726 ADG732 S1 S1A DA S16A D S1B DB S32 S16B WR CSA 1-OF-16 DECODER CSB A0 A1 A2 A3 EN WR CS 1-OF-32 DECODER A0 A1 A2 A3 A4 EN GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG726/ADG732 are monolithic CMOS 32-channel/dual 16-channel analog multiplexers. The ADG732 switches one of 32 inputs (S1-S32) to a common output, D, as determined by the 5-bit binary address lines A0, A1, A2, A3, and A4. The ADG726 switches one of 16 inputs as determined by the 4-bit binary address lines A0, A1, A2, and A3. 1. +1.8 V to +5.5 V single- or ± 2.5 V dual-supply operation. These parts are specified and guaranteed with +5 V ± 10%, +3 V ± 10% single-supply, and ± 2.5 V ± 10% dualsupply rails. On-chip latches facilitate microprocessor interfacing. The ADG726 device may also be configured for differential operation by tying CSA and CSB together. An EN input is used to enable or disable the devices. When disabled, all channels are switched OFF. 2. On resistance of 4 Ω 3. Guaranteed break-before-make switching action 4. 7 mm × 7 mm 48-lead chip scale package (CSP) or 48-lead TQFP package These multiplexers are designed on an enhanced submicron process that provides low power dissipation yet gives high switching speed, very low on resistance, and leakage currents. They operate from a single supply of +1.8 V to +5.5 V and a ±2.5 V dual supply, making them ideally suited to a variety of applications. On resistance is in the region of a few ohms and is closely matched between switches and very flat over the full signal range. These parts can operate equally well as either multiplexers or demultiplexers and have an input signal range that extends to the supplies. In the OFF condition, signal levels up to the supplies are blocked. All channels exhibit break-before-make switching action, preventing momentary shorting when switching channels. They are available in either 48-lead CSP or TQFP packages. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 ADG726/ADG732–SPECIFICATIONS1 (V DD = 5 V  Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) ADG726 ADG732 Channel ON Leakage ID, IS (ON) ADG726 ADG732 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS2 tTRANSITION +25C B Version –40C to +85C 0 V to VDD 4 5.5 6 0.3 0.8 0.5 1 ± 0.01 ± 0.25 ± 0.05 ± 0.5 ±1 ± 0.05 ± 0.5 ±1 Unit V Ω typ Ω max Ω typ Ω max Ω typ Ω max 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.) Test Conditions/Comments VS = 0 V to VDD, IDS = 10 mA; Test Circuit 1 VS = 0 V to VDD, IDS = 10 mA VS = 0 V to VDD, IDS = 10 mA VDD = 5.5 V VD = 4.5 V/1 V, VS = 1 V/4.5 V; Test Circuit 2 VD = 4.5 V/1 V, VS = 1 V/4.5 V; Test Circuit 3 ± 2.5 ±5 nA typ nA max nA typ nA max nA max nA typ nA max nA max 2.4 0.8 V min V max ± 0.5 µA typ µA max pF typ VIN = VINL or VINH ns typ ns max ns typ ns min ns typ ns max ns typ ns max ns typ ns max ns typ ns max pC typ RL = 300 Ω, CL = 35 pF, Test Circuit 5 VS1 = 3 V/0 V, VS32 = 0 V/3 V RL = 300 Ω, CL = 35 pF; VS = 3 V; Test Circuit 6 VS = 3 V; Test Circuit 7 RL = 300 Ω, CL = 35 pF; VS = 3 V; Test Circuit 7 RL = 300 Ω, CL = 35 pF; RL = 300 Ω, CL = 35 pF; VS = 3 V; Test Circuit 8 RL = 300 Ω, CL = 35 pF; VS = 3 V; Test Circuit 8 VS = 2.5 V, RS = 0 Ω, CL = 1 nF; Test Circuit 9 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 10 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 11 RL = 50 Ω, CL = 5 pF; Test Circuit 12 ±1 ± 2.5 ±5 0.005 5 VD = VS = 1 V, or 4.5 V; Test Circuit 4 Charge Injection 23 34 18 1 18 25 17 23 24 32 16 22 5 OFF Isolation –72 dB typ Channel-to-Channel Crosstalk –72 dB typ 34 18 13 MHz typ MHz typ pF typ f = 1 MHz 170 340 pF typ pF typ f = 1 MHz f = 1 MHz 175 350 pF typ pF typ f = 1 MHz f = 1 MHz 10 µA typ µA max Break-Before-Make Time Delay, tD tON(CS, WR) tOFF(CS, WR) tON(EN) tOFF(EN) –3 dB Bandwidth ADG726 ADG732 CS (OFF) CD (OFF) ADG726 ADG732 CD, CS (ON) ADG726 ADG732 POWER REQUIREMENTS IDD 40 32 29 40 25 20 VDD = 5.5 V Digital Inputs = 0 V or 5.5 V NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. Guaranteed by design; not subject to production test. Specifications subject to change without notice. 2 –2– REV. 0 ADG726/ADG732 SPECIFICATIONS1 (V DD = 3 V  10%, VSS = 0 V, GND = 0 V, unless otherwise noted.) B Version –40C +25C to +85C Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) 0 V to VDD 7 11 On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) ADG726 ADG732 Channel ON Leakage ID, IS (ON) ADG726 ADG732 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH ± 0.01 ± 0.25 ± 0.05 ± 0.5 ±1 ± 0.05 ± 0.5 ±1 12 0.35 1 3 V Ω typ Ω max Ω typ Ω max Ω typ Test Conditions/Comments VS = 0 V to VDD, IDS = 10 mA; Test Circuit 1 VS = 0 V to VDD, IDS = 10 mA VS = 0 V to VDD, IDS = 10 mA VDD = 3.3 V VS = 3 V/1 V, VD = 1 V/3 V; Test Circuit 2 VS = 1 V/3 V, VD = 3 V/1 V; Test Circuit 3 ± 2.5 ±5 nA typ nA max nA max nA max nA max nA typ nA max nA max 2.0 0.7 V min V max ± 0.5 µA typ µA max pF typ VIN = VINL or VINH ns typ ns max ns typ ns min ns typ ns max ns typ ns max ns typ ns max ns typ ns max pC typ RL = 300 Ω, CL = 35 pF; Test Circuit 5 VS1 = 2 V/0 V, VS32 = 0 V/2 V RL = 300 Ω, CL = 35 pF; VS = 2 V; Test Circuit 6 VS = 2 V; Test Circuit 7 RL = 300 Ω, CL = 35 pF; VS = 2 V; Test Circuit 7 RL = 300 Ω, CL = 35 pF; RL = 300 Ω, CL = 35 pF; VS = 3 V; Test Circuit 8 RL = 300 Ω, CL = 35 pF; VS = 2 V; Test Circuit 8 VS = 1.5 V, RS = 0 Ω, CL = 1 nF; Test Circuit 9 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 10 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 11 RL = 50 Ω, CL = 5 pF; Test Circuit 12 ±1 ± 2.5 ±5 0.005 CIN, Digital Input Capacitance Unit 5 VS = VD = 1 V or 3 V; Test Circuit 4 2 DYNAMIC CHARACTERISTICS tTRANSITION Charge Injection 34 52 26 1 29 43 26 38 33 48 19 25 1 Off Isolation –72 dB typ Channel-to-Channel Crosstalk –72 dB typ 34 18 13 MHz typ MHz typ pF typ f = 1 MHz 170 340 pF typ pF typ f = 1 MHz f = 1 MHz 175 350 pF typ pF typ f = 1 MHz f = 1 MHz 5 µA typ µA max Break-Before-Make Time Delay, tD tON(WR, CS) tOFF(WR, CS) tON(EN, WR) tOFF(EN) –3 dB Bandwidth ADG726 ADG732 CS (OFF) CD (OFF) ADG726 ADG732 CD, CS (ON) ADG726 ADG732 POWER REQUIREMENTS IDD 62 52 42 55 28 10 NOTES 1 Temperature ranges are as follows: B Version: –40°C to +85°C. 2 Guaranteed by design; not subject to production test. Specifications subject to change without notice. REV. 0 –3– VDD = 3.3 V Digital Inputs = 0 V or 3.3 V ADG726/ADG732 SPECIFICATIONS1 DUAL SUPPLY (V DD = +2.5 V ⴞ 10%, VSS = –2.5 V ⴞ 10%, GND = 0 V, unless otherwise noted.) Parameter +25ⴗC ANALOG SWITCH Analog Signal Range On Resistance (RON) B Version –40ⴗC to +85ⴗC VSS to VDD 4 5.5 On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) 6 0.3 0.8 0.5 1 LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) ADG726 ADG732 Channel ON Leakage ID, IS (ON) ADG726 ADG732 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH ± 0.01 ± 0.25 ± 0.05 ± 0.5 ±1 ± 0.05 ± 0.5 ±1 V Ω typ Ω max Ω typ Ω max Ω typ Ω max Test Conditions/Comments VS = VSS to VDD, IDS = 10 mA; Test Circuit 1 VS = VSS to VDD, IDS = 10 mA VS = VSS to VDD, IDS = 10 mA VDD = +2.75 V, VSS = –2.75 V VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V; Test Circuit 2 VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V; Test Circuit 3 ± 2.5 ±5 nA typ nA max nA max nA max nA max nA typ nA max nA max 1.7 0.7 V min V max ± 0.5 µA typ µA max pF typ VIN = VINL or VINH ns typ ns max ns typ ns min ns typ ns max ns typ ns max ns typ ns max ns typ ns max pC typ RL = 300 ⍀, CL = 35 pF; Test Circuit 5 VS1 = 1.5 V/0 V, VS32 = 0 V/1.5 V RL = 300 ⍀, CL = 35 pF; VS = 1.5 V; Test Circuit 6 VS = 1.5 V; Test Circuit 7 RL = 300 ⍀, CL = 35 pF; VS = 1.5 V; Test Circuit 7 RL = 300 ⍀, CL = 35 pF; RL = 300 ⍀, CL = 35 pF; VS = 1.5 V; Test Circuit 8 RL = 300 ⍀, CL = 35 pF; VS = 1.5 V; Test Circuit 8 VS = 0 V, RS = 0 ⍀, CL = 1 nF; Test Circuit 9 RL = 50 ⍀, CL = 5 pF, f = 1 MHz; Test Circuit 10 RL = 50 ⍀, CL = 5 pF, f = 1 MHz; Test Circuit 11 RL = 50 ⍀, CL = 5 pF; Test Circuit 12 ± 0.5 ± 2.5 ±5 0.005 CIN, Digital Input Capacitance Unit 5 VS = VD = +2.25 V/–1.25 V; Test Circuit 4 2 DYNAMIC CHARACTERISTICS tTRANSITION Charge Injection 33 45 15 1 21 30 20 29 26 37 18 26 1 OFF Isolation –72 dB typ Channel-to-Channel Crosstalk –72 dB typ 34 18 13 MHz typ MHz typ pF typ 137 275 pF typ pF typ f = 1 MHz f = 1 MHz 150 300 pF typ pF typ f = 1 MHz f = 1 MHz µA typ µA max µA typ µA max VDD = +2.75 V Digital Inputs = 0 V or +2.75 V VSS = –2.75 V Digital Inputs = 0 V or +2.75 V Break-Before-Make Time Delay, tD tON(CS, WR) tOFF(CS, WR) tON(EN, WR) tOFF(EN) –3 dB Bandwidth ADG726 ADG732 CS (OFF) CD (OFF) ADG726 ADG732 CD, CS (ON) ADG726 ADG732 POWER REQUIREMENTS IDD 51 37 35 29 10 20 ISS 10 20 NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. 2 Guaranteed by design; not subject to production test. Specifications subject to change without notice. –4– REV. 0 ADG726/ADG732 TIMING CHARACTERISTICS1, 2, 3 Parameter Limit at TMIN, TMAX Unit Conditions/Comments t1 t2 t3 t4 t5 t6 0 0 10 10 5 2 ns min ns min ns min ns min ns min ns min CS to WR Setup Time CS to WR Hold Time WR Pulsewidth Time between WR Cycles Address, Enable Setup Time Address, Enable Hold Time NOTES 1 See Figure 1. 2 All input signals are specified with tr = tf = 1 ns (10% to 90% of V DD). 3 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. CS t1 t2 t3 t4 WR t5 t6 A0, A1, A2, A3, (A4) EN Figure 1. Timing Diagram Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to changing the address and enable the inputs. REV. 0 Input data is latched on the rising edge of WR. The ADG726 has two CS inputs. This enables the part to be used either as a dual 16-1 channel multiplexer or a differential 16-channel multiplexer. If a differential output is required, tie CSA and CSB together. –5– ADG726/ADG732 ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C, unless otherwise noted.) VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V Analog Inputs2 . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V or 30 mA, Whichever Occurs First Digital Inputs2 . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V or 30 mA, Whichever Occurs First Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA (Pulsed at 1 ms, 10% Duty Cycle Max) Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Thermal Impedence (Four-layer board) 48-Lead LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . 25⬚C/W 48-Lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . 54.6⬚C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C IR Reflow, Peak Temperature (H X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Retains Previous Switch Condition No Change in Switch Condition NONE S1A–DA, S1B–DB S2A–DA, S2B–DB S3A–DA, S3B–DB S4A–DA, S4B–DB S5A–DA, S5B–DB S6A–DA, S6B–DB S7A–DA, S7B–DB S8A–DA, S8B–DB S9A–DA, S9B–DB S10A–DA, S10B–DB S11A–DA, S11B–DB S12A–DA, S12B–DB S13A–DA, S13B–DB S14A–DA, S14B–DB S15A–DA, S15B–DB S16A–DA, S16B–DB X = Don’t Care Table II. ADG732 Truth Table A4 A3 A2 A1 A0 EN CS WR Switch Condition X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L->H X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Retains Previous Switch Condition No Change in Switch Condition NONE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 X = Don’t Care REV. 0 –7– ADG726/ADG732 TERMINOLOGY VDD Most Positive Power Supply Potential VSS IDD ISS GND S D IN VD (VS) RON ∆RON RFLAT(ON) Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect to GND. Positive Supply Current Negative Supply Current Ground (0 V) Reference Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input Analog Voltage on Terminals D and S Ohmic Resistance between D and S On Resistance Match between any two channels, i.e., RONmax – RONmin Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. Source Leakage Current with the Switch OFF Drain Leakage Current with the Switch OFF Channel Leakage Current with the Switch ON Maximum Input Voltage for Logic “0” Minimum Input Voltage for Logic “1” Input Current of the Digital Input OFF Switch Source Capacitance. Measured with reference to ground. OFF Switch Drain Capacitance. Measured with reference to ground. ON Switch Capacitance. Measured with reference to ground. Digital Input Capacitance Delay Time Measured between the 50% and 90% Points of the Digital Inputs and the Switch ON Condition when Switching from One Address State to Another Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch ON Condition Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch OFF Condition OFF Time Measured between the 80% Points of Both Switches when Switching from One Address State to Another A Measure of the Glitch Impulse Transferred from the Digital Input to the Analog Output During Switching IS (OFF) ID (OFF) ID, IS (ON) VINL VINH IINL(IINH) CS (OFF) CD (OFF) CD, CS(ON) CIN tTRANSITION tON(EN) tOFF(EN) tOPEN Charge Injection OFF Isolation Crosstalk A Measure of Unwanted Signal Coupling through an OFF Switch A Measure of Unwanted Signal Coupling from One Channel to Another as a Result of Parasitic Capacitance ON Response The Frequency Response of the ON Switch Insertion Loss The Loss Due to the On Resistance of the Switch –8– REV. 0 Typical Performance Characteristics—ADG726/ADG732 8 7 RESISTANCE –
RESISTANCE –
VDD = 5.5V 5 VDD = 3.3V 4 8 7 7 3 VDD = 4.5V 2 VDD = 5V 1 5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VD, VS – V 6 4 VDD = +2.75V VSS = –2.75V 3 8 1.25 2.25 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VD, VS – V 0.5 VDD = 5V VSS = 0V 0.4 0.3 +85C 6 5 –40C 3 CURRENT – nA 6 RESISTANCE –
RESISTANCE –
0 TPC 3. On Resistance vs. VD(VS) for Different Temperatures, Single Supply 7 4 –40C 0 –0.75 0.25 VD, VS – V 8 +25C 3 1 VSS = 0V 7 +25C 1 –1.75 +85C 4 2 TPC 2. On Resistance vs. VD(VS), Dual Supply TPC 1. On Resistance vs. VD(VS), Single Supply 5 2 0 –2.75 0 TA = +25C VDD = +2.5V VSS = –2.5V VDD = +2.25V VSS = –2.25V 6 VDD = 3.0V 6 8 VSS = 0V TA = +25C VSS = 0V RESISTANCE –
VDD = 2.7V 5 +85C 4 +25C 3 0.2 0.1 0 –0.1 –0.2 –40C 2 2 1 1 –0.4 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VD, VS – V 0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 VD, VS – V –0.5 TPC 4. On Resistance vs. VD(VS), Single Supply TPC 5. On Resistance vs. VD(VS), Dual Supply –0.3 0 0 25 45 20 40 15 5 25 35 45 55 65 TEMPERATURE – C 75 85 TPC 6. Leakage Currents vs. Temperature 1.8 35 15 30 TIME – ns QINJ – pC 10 5 0 VDD = 3V 25 t ON VDD = 5V 20 15 –5 VDD = 3V VDD = 5V tOFF 10 –10 5 TA = +25C –15 LOGIC THRESHOLD VOLTAGE – V VSS = 0V –3 –2 –1 0 1 2 VD, VS – V 3 4 5 TPC 7. ADG732 Charge Injection vs. Source Voltage REV. 0 0 –40 –20 0 20 40 TEMPERATURE – C 60 80 TPC 8. tON/tOFF Times vs. Temperature –9– 1.6 1.4 1.2 RISING 1.0 FALLING 0.8 0.6 0.4 0.2 0 TA = 25C 0 1 2 3 4 5 6 VDD – V TPC 9. Logic Threshold Voltage vs. Supply Voltage ADG726/ADG732 0 0 VDD = 5V TA = 25C –10 –10 –30 –40 –50 –60 –70 –30 –40 –50 –60 –70 –80 –80 –90 –90 0.1 1 10 FREQUENCY – MHz –4 ADG732 –6 –8 –10 –12 –100 0.03 100 TPC 10. OFF Isolation vs. Frequency Test Circuits ATTENUATION – dB ATTENUATION – dB ATTENUATION – dB ADG726 VDD = 5V TA = 25C –2 –20 –20 –100 0.03 0 VDD = 3V, 5V TA = 25C 0.1 1 10 FREQUENCY – MHz –14 0.03 100 0.1 S1 V1 VDD VSS VDD VSS D S2 D ID(OFF) A S32 VS VS 100 TPC 12. ON Response vs. Frequency TPC 11. Crosstalk vs. Frequency IDS S 1 10 FREQUENCY – MHz EN GND VD LOGIC “1” RON = V1 /IDS Test Circuit 1. On Resistance IS(OFF) S1 A VDD VSS VDD VSS D S2 VS Test Circuit 3. ID (OFF) VSS VDD VSS D S1 ID(ON) A S32 S32 EN VS GND LOGIC “1” VS VD GND Test Circuit 2. IS (OFF) VDD VSS VDD VSS A4 VIN VDD 50
VD LOGIC “ 0” Test Circuit 4. ID (ON) 3V S1 ADDRESS DRIVE (VIN) VS1 50% 50% 0V S2 THRU S31 A0 VS1 VS32 S32 ADG732* EN D RL 300
EN CS GND WR CL 35pF 90% VOUT VOUT 90% VS32 tTRANSITION tTRANSITION *SIMILAR CONNECTION FOR ADG726 Test Circuit 5. Switching Time of Multiplexer, tTRANSITION VDD VSS VDD VSS A4 VIN 50
3V S1 VS ADDRESS DRIVE (VIN) S2 THRU S31 A0 0V S32 ADG732* VS D EN CS GND WR RL 300
CL 35pF VOUT VOUT 80% 80% tOPEN *SIMILAR CONNECTION FOR ADG726 Test Circuit 6. Break-Before-Make Delay, tOPEN –10– REV. 0 ADG726/ADG732 VDD VSS VDD VSS 3V A4 WR S1 50% 0V VS S2 THRU S32 A0 CS ADG732* VCS WR EN D CL 35pF RL 300
GND VWR SWITCH OUTPUT VOUT VO tON (WR) 20% 0V tOFF (WR) 20% *SIMILAR CONNECTION FOR ADG726 Test Circuit 7. Write Turn-ON and Turn-OFF Time, tON, tOFF (WR) VDD VSS VDD VSS A4 3V S1 VS 50% EN A0 tON (EN) EN VEN ADG732* CS 50% 0V S2 THRU S32 GND D CL 35pF RL 300
WR VOUT SWITCH OUTPUT VO tOFF (EN) 10% 90% 0V *SIMILAR CONNECTION FOR ADG726 Test Circuit 8. Enable Delay, tON (EN), tOFF (EN) A4 VDD VSS VDD VSS 3V A0 LOGIC INPUT (VIN) ADG732* RS S D CL 1nF EN VS VIN CS 0V VOUT VOUT GND WR QINJ = C L  V OUT *SIMILAR CONNECTION FOR ADG726 Test Circuit 9. Charge Injection VDD VSS 0.1F 0.1F VDD VSS NETWORK ANALYZER 50
A4 A0 S 50
D LOGIC “ 1” VS VOUT RL 50
EN ADG732* GND OFF ISOLATION = 20 LOG *SIMILAR CONNECTION FOR ADG726 Test Circuit 10. OFF Isolation REV. 0 –11– VOUT VS VOUT ADG726/ADG732 VDD VSS 0.1F VSS VDD VSS S1 50
A4 S2 A0 VDD NETWORK ANALYZER 50
VSS NETWORK ANALYZER 50
A4 A0 S VS VS S32 ADG732* 0.1F D VOUT RL 50
EN VOUT D ADG732* RL 50
C02765–0–7/02(0) VDD GND EN CS GND WR INSERTION LOSS = 20 LOG *SIMILAR CONNECTION FOR ADG726 CHANNEL-TO-CHANNEL CROSSTALK = 20LOG10 (VOUT/VS) VOUT WITH SWITCH VOUT WITHOUT SWITCH *SIMILAR CONNECTION FOR ADG726 Test Circuit 11. Channel-to-Channel Crosstalk Test Circuit 12. Bandwidth OUTLINE DIMENSIONS 48-Lead Frame Chip Scale Package [LFCSP] (CP-48) Dimensions shown in millimeters 7.00 BSC SQ 0.30 0.23 0.18 0.60 MAX 0.60 MAX 37 5.25 4.70 2.25 BOTTOM VIEW 0.50 0.40 0.30 12 25 24 13 5.50 REF 0.70 MAX 0.65 NOM COPLANARITY 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 48-Lead Thin Plastic Quad Flatpack [TQFP] (SU-48) Dimensions shown in millimeters 1.20 MAX PRINTED IN U.S.A. 0.25 REF 1 6.75 BSC SQ TOP VIEW 12 MAX 48 36 PIN 1 INDICATOR 1.00 0.90 0.80 PIN 1 INDICATOR 9.00 BSC SQ 0.75 0.60 0.45 37 48 36 1 7.00 BSC SQ TOP VIEW (PINS DOWN) COPLANARITY 0.15 0.05 0 MIN 25 12 13 24 0.5 BSC 0.20 0.09 0.27 0.22 0.17 7 0 1.05 1.00 0.95 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MS-026BBC –12– REV. 0