High Power, 44 W Peak, Silicon SPDT,
Reflective Switch, 0.7 GHz to 3.8 GHz
ADRF5130
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
Reflective, 50 Ω design
Low insertion loss
0.6 dB typical to 2.0 GHz
0.7 dB typical to 3.5 GHz
High isolation
50 dB typical to 2.0 GHz
46 dB typical to 3.5 GHz
High power handling
RF input power, continuous wave (CW) at TCASE = 85°C
43 dBm maximum operating
46.5 dBm absolute maximum rating
High linearity
0.1 dB compression (P0.1dB): 46 dBm typical
Input third-order intercept (IP3)
68 dBm typical to 2 GHz
65 dBm typical to 3.5 GHz
ESD ratings
Human body model (HBM): 2 kV, Class 2
Charged device model (CDM): 1.25 kV
Single positive supply: VDD = 5 V
Positive control, TTL-compatible: VCTL = 0 V or VDD
24-lead, 4 mm × 4 mm LFCSP package (16 mm2)
VCTL
ADRF5130
RF1
RF2
RFC
14081-001
FEATURES
Figure 1.
APPLICATIONS
Cellular/4G infrastructure
Wireless infrastructure
Military and high reliability applications
Test equipment
Pin diode replacement
GENERAL DESCRIPTION
The ADRF5130 is a high power, reflective, 0.7 GHz to 3.8 GHz,
silicon, single-pole, double-throw (SPDT) switch in a leadless,
surface-mount package. The switch is ideal for high power and
cellular infrastructure applications, like long-term evolution (LTE)
base stations.
The ADRF5130 has high power handling of 43 dBm (maximum)
and 0.1 dB compression (P0.1dB) of 46 dBm, with a low
insertion loss of 0.6 dB at 2 GHz and 0.7 dB at 3.5 GHz. On-chip
circuitry operates at a single, positive supply voltage of 5 V and
typical supply current of 1.06 mA, making the ADRF5130 an
ideal alternative to pin diode-based switches.
The device comes in a RoHS compliant, compact, 24-lead, 4 mm ×
4 mm LFCSP package.
Rev. C
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ADRF5130
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................5
Applications ...................................................................................... 1
Typical Performance Characteristics .............................................6
Functional Block Diagram .............................................................. 1
Insertion Loss, Isolation, Return Loss, and IP3 ........................6
General Description ......................................................................... 1
Theory of Operation .........................................................................7
Revision History ............................................................................... 2
Applications Information ................................................................8
Specifications .................................................................................... 3
Evaluation Board ...........................................................................8
Absolute Maximum Ratings ........................................................... 4
Outline Dimensions ....................................................................... 10
ESD Caution.................................................................................. 4
Ordering Guide .......................................................................... 10
Pin Configuration and Function Descriptions ............................ 5
REVISION HISTORY
6/2020—Rev. B to Rev. C
Changed Operating Frequency from 0.7 GHz to 3.5 GHz to
0.7 GHz to 3.8 GHz ....................................................... Throughout
Changes to Data Sheet Title, Features Section, and General
Description Section .......................................................................... 1
Changes to Table 1 ........................................................................... 3
5/2018—Rev. A to Rev. B
Change to RFC to RF2 Column, Table 5 .......................................7
Updated Outline Dimensions ...................................................... 10
1/2017—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 10
7/2016—Revision 0: Initial Version
Rev. C | Page 2 of 10
Data Sheet
ADRF5130
SPECIFICATIONS
VDD = 5 V, VCTL = 0 V or VDD, TA = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter
FREQUENCY RANGE
INSERTION LOSS
Symbol
ISOLATION
RFC to RF1 or RF2 (Worst Case)
RF1 to RF2 (Worst Case)
RETURN LOSS
RFC
RFC to RF1 or RF2
SWITCHING SPEED
Time
Rise and Fall
On and Off
RADIO FREQUENCY (RF) SETTLING TIME
INPUT POWER
0.1 dB Compression
INPUT THIRD-ORDER INTERCEPT
tRISE, tFALL
tON, tOFF
P0.1dB
IP3
RECOMMENDED OPERATING
CONDITIONS
Voltage Range
Bias
Control
Maximum RF Input Power
TCASE = 105°C
TCASE = 85°C
VDD
VCTL
TCASE = 25°C
Case Temperature Range
DIGITAL INPUT CONTROL VOLTAGE
TCASE
Low Range
High Range
SUPPLY CURRENT
VIL
VIH
IDD
Test Conditions/Comments
Min
0.7
0.7 GHz to 2.0 GHz
2.0 GHz to 3.5 GHz
3.5 GHz to 3.8 GHz
0.6
0.7
0.75
Unit
GHz
dB
dB
dB
0.7 GHz to 2.0 GHz
2.0 GHz to 3.8 GHz
0.7 GHz to 2.0 GHz
2.0 GHz to 3.8 GHz
50
46
51
40
dB
dB
dB
dB
0.7 GHz to 2.0 GHz
2.0 GHz to 3.5GHz
3.5 GHz to 3.8 GHz
0.7 GHz to 2.0 GHz
2.0 GHz to 3.5 GHz
3.5 GHz to 3.8 GHz
23
17
15
21
17
16
dB
dB
dB
dB
dB
dB
90% to 10% of RF output
50% VCTL to 10% to 90% of RF output
50% VCTL to 0.1 dB margin of final RF output
155
750
1.8
ns
ns
µs
46
dBm
68
65
dBm
dBm
Two-tone input power = 25 dBm/tone
0.7 GHz to 2 GHz
2 GHz to 3.8 GHz
Typ
Max
3.8
4.5
0
5.4
VDD
V
V
−40
41
43
38
44
44.5
+105
dBm
dBm
dBm
dBm
dBm
°C
0
1.3
0.8
5.0
V
V
mA
Continuous wave
Continuous wave
8 dB peak to average ratio (PAR) LTE, average
8 dB PAR LTE, single event (
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