AOZ7523GAI-02

AOZ7523 Current Mode Flyback Converter with HV Start-Up and Advanced Features General Description Features AOZ7523 is a series of current mode controllers with a 650V integrated power MOSFET, and a X-capacitor discharge function (Bleeding Resistor Removal, BRR), Brown-In/Brown-Out (Lossless Brown-Out, LBO) plus a high voltage start-up circuitry. The series also provides frequency foldback and skip mode during light load conditions to achieve excellent light load efficiency and low power standby mode. As well as a digital Spread Spectrum Clock Generator (SSCG) to improve EMI emissions. In addition, AOZ7523 includes cycle-by-cycle current limit, Under Voltage Lockout (UVLO), VDD OVP, DMAG pin OVP, Over Load Protection (OLP), CS pin protection, Secondary-Side Diode Short protection (SSDS).  Integrated with 650V HV MOSFET Applications  Cycle-by-cycle current limit  SMPS  Minimum on time modulation to minimize acoustic  NB Adapter  Integrated bleeding resistor removal function  Integrated brown-in/brown-out function  Integrated HV start-up circuitry  Under-voltage lockout: 7V/15V  Low operation current  Lower operation current in skip mode ( 1V, Fs = 130kHz 65 kHz VCS > 1V, Fs = 65kHz 32.5 kHz SOFT-START TSS FSS-SKIP Soft-Start Time Soft-Start Skip Frequency Rev. 1.0 January 2017 www.aosmd.com Page 4 of 15 AOZ7523 Electrical Characteristics (Continued) TA = -25°C to 85°C, VDD = 15V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units 0.85 0.9 0.95 V 80 ms CURRENT SENSE VCL General Continuous Operation Limited Current Sense Level TOLP Over Load Protection De-Bounce Time 60 VCL2 SSDS Level 1.5 TCL2 De-Bounce Time for VCL2 TLEB TP Continuous 5 Clock Cycles, Fs = 65kHz V 75 100 μs Leading Edge Blanking Time 250 400 ns Propagation Delay Time 50 100 ns OVER TEMPERATURE PROTECTION OTP OTPREC Internal Over Temperature Protection TJ Rising 145 °C Thermal Shutdown Recovery Threshold TJ Falling 125 °C Note: 2. Guaranteed by design. Functional Block Diagram VDD R VSK VDD-OVP Spread Spectrum Clock Generator R CS Drain OVP Green Function FB HV UVLO Internal Bias LEB 7V/15V Slope Compensation OVP Soft Start VCL S CS pin & SSDS Protection ZCD Reset and Shutdown Control Logic Q R GATE Clamp Output Current Estimator BNI / BNO D-OVP DMAG VD-OVP GATE Driver X-Cap Discharge Thermal Shutdown Clamping VDIS Constant Power (OLP) Min. On-Time Modulator GND Rev. 1.0 January 2017 www.aosmd.com Source Page 5 of 15 AOZ7523 Typical Characteristics Figure 1. Supply Current From HV Pin vs. Temperature Figure 2. Turn-On Threshold Voltage vs. Temperature 1.6 16.0 1.5 15.5 1.4 VDD_ON (V) IHV (mA) 1.3 1.2 1.1 15.0 14.5 1.0 14.0 0.9 0.8 -40 -25 -10 5 20 35 50 65 80 95 13.5 -40 110 125 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) Figure 3. Operating Current vs. Temperature Figure 4. Under-Voltage Lockout Voltage vs. Temperature 7.4 3.00 2.95 7.3 2.90 7.2 VDD_UVLO (V) IDD_OP (mA) 2.85 2.80 2.75 2.70 7.1 7.0 6.9 2.65 6.8 2.60 6.7 2.55 2.50 -40 -25 -10 5 20 35 50 65 80 95 110 6.6 -40 125 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) Figure 5. VDD OVP Level vs. Temperature Figure 6. FB Pin Pull High Voltage vs. Temperature 29.0 4.600 28.8 4.575 28.6 VFB-OPEN (V) VDD_OVP (V) 28.4 28.2 28.0 27.8 4.550 4.525 4.500 27.6 27.4 4.475 27.2 27.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 4.450 -40 Temperature (°C) Rev. 1.0 January 2017 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) www.aosmd.com Page 6 of 15 AOZ7523 Typical Characteristics (Continued) Figure 8. Entry FR Threshold Voltage vs. Temperature 2.5 43 2.4 42 2.3 41 VFB-E (V) ZFB (Ω) Figure 7. FB Pin Impedance vs. Temperature 44 40 2.2 2.1 39 2.0 38 1.9 37 -40 -25 -10 5 20 35 50 65 80 95 1.8 -40 110 125 -25 -10 5 Temperature (°C) 20 35 50 65 80 95 110 125 Temperature (°C) Figure 9. Depart FR Threshold Voltage vs. Temperature Figure 10. Skip Mode Entry Level vs. Temperature 2.2 1.0 2.1 0.9 2.0 VSK-E (V) VFB-D (V) 0.8 1.9 1.8 0.7 0.6 1.7 0.5 1.6 1.5 -40 -25 -10 5 20 35 50 65 80 95 0.4 -40 110 125 -25 -10 5 Temperature (°C) 35 50 65 80 95 110 125 Temperature (°C) Figure 11. Skip Mode Depart Level vs. Temperature Figure 12. Maximum TMIN Clamp vs. Temperature 1.0 3.5 0.9 3.4 3.3 TMIN_MAX (μs) 0.8 VSK-D (V) 20 0.7 0.6 3.2 3.1 3.0 0.5 0.4 -40 2.9 -25 -10 5 20 35 50 65 80 95 110 125 2.8 -40 Temperature (°C) Rev. 1.0 January 2017 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) www.aosmd.com Page 7 of 15 AOZ7523 Typical Characteristics (Continued) Figure 14. General Continuous Operation Frequency vs. Temperature Figure 13. Minimum TMIN CLAMP vs. Temperature 0.85 66 0.83 65 0.80 0.78 TMIN_MIN (μs) 64 FOSC (kHz) 0.75 0.73 0.70 63 62 0.68 0.65 61 0.63 0.60 -40 -25 -10 5 20 35 50 65 80 95 110 60 -40 125 -25 -10 5 Temperature (°C) 20 35 50 65 80 95 110 125 Temperature (°C) Figure 15. Minimum Continuous Operation Frequenc vs. Temperature Figure 16. Maximum Duty Cycle vs. Temperature 22 80 79 21 78 77 DMAX (%) FMIN (kHz) 20 19 18 76 75 74 73 17 72 16 71 15 -40 -25 -10 5 20 35 50 65 80 95 70 -40 110 125 -25 -10 5 Temperature (°C) 20 35 50 65 80 95 110 125 Temperature (°C) Figure 18. DMAG Pin Over Voltage Level vs. Temperature Figure 17. Current Limit vs. Temperature 1.00 3.10 0.98 3.05 0.96 0.94 3.00 VD_OVP (V) VCL (V) 0.92 0.90 0.88 2.95 2.90 0.86 0.84 2.85 0.82 0.80 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.80 -40 Temperature (°C) Rev. 1.0 January 2017 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) www.aosmd.com Page 8 of 15 AOZ7523 Typical Characteristics (Continued) Figure 20. General Continuous Operation Frequency vs. VDD 0.53 67.0 0.52 66.5 0.51 66.0 0.50 65.5 FOSC (kHz) IDMAG (mA) Figure 19. DMAG Sourcing Current 0.5mA vs. Temperature 0.49 0.48 65.0 64.5 0.47 64.0 0.46 63.5 0.45 -40 63.0 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Rev. 1.0 January 2017 8 10 12 14 16 18 20 22 24 26 VDD (V) www.aosmd.com Page 9 of 15 AOZ7523 Typical Operation Description Start-Up During the start-up period, the HV device acts as a current source and charges the VDD capacitor until its voltage is higher than that of the turn-on threshold VDDON, at that point the AOZ7523 will start to operate but it will enter standby mode to wait brown-in signal. The VDD voltage of AOZ7523 will be kept between 12V~14V until brown-in is triggered. After brown-in, PWM signal will start to drive the MOSFET and the peak current of MOSFET will be increased linearly during the soft-start period. Normal Mode Operation In normal mode operation, if the output is in heavy load, the controller is switching with maximum frequency (130kHz or 65kHz) and operated with current-mode control. Frequency Foldback Mode Operation AOZ7523 provides green mode operation to reduce switching loss and improve system efficiency by frequency foldback function during light load condition. When the voltage of FB pin is decreased below VFB-E. The controller will enter green mode and the switching frequency starts foldback according to load condition. The minimum switching frequency will be clamped to FMIN when the voltage of FB pin is below VFB-D. Skipping Mode Operation Under very light load condition, the voltage of FB will be decreased to a very low level. When the voltage of FB is dropped below the threshold (VSK-E) that is the hysteresis voltage of internal PWM comparator, the PWM signal will be blanked and stop to drive MOSFET. After the output voltage dropped and FB voltage increased higher than VSK-D, the PWM signal will be resumed. VDD Hold-Up Mode Operation During load transient or ultra light load conditions, FB voltage will drop deeply and enter into skipping cycle mode to stop PWM signal. In some conditions, VDD voltage will drop below controller’s turn-off threshold (UVLO) and then the system will be restarted. If another load occurred, the system cannot respond immediately and the output voltage will drop deeply. This mode is very useful to prevent system restarting during ultra light load condition and has a quick response for load transients. It doesn’t require a two-stage VDD circuit to keep VDD voltage higher than UVLO. Rev. 1.0 January 2017 Minimum On Time Modulation In order to reduce switching loss and minimize acoustic noise, AOZ7523 provides Modulate On-Time to limit the minimum turn-on time (Ton,min). The modulate on-time is inversely proportional to input voltage. In the condition of low line input voltage, PWM on-time will be enlarged to reduce switching cycles and increase the efficiency of light load. In the condition of high line input voltage, PWM on time will be tighten to minimize acoustic noise and make the ripple of output voltage close in every line input. Protection Features Over Voltage Protection (OVP) It's critical that over voltage protection (OVP) prevents the output voltage from exceeding the ratings of converter’s components. The Over-Voltage Protection (OVP) is embedded by the information at the VDD pin. That information comes from the output voltage through the turn-ratio from auxiliary winding to secondary-side winding. When the voltage further rises and exceeds the comparator’s reference voltage of static OVP (27V typ), the OVP comparator will shut down the output PWM pulse. The OVP logic also includes 20μs de-glitch time for false triggering by noise. DMAG Over Voltage Protection (DOVP) AOZ7523 provides a more accurate OVP function from DMAG pin that is to protect system component when the output is over voltage. DMAG pin detect the voltage across the auxiliary winding during MOSFET turn-off period with another 1μs de-glitch time. The DMAG pin voltage is proportional to the output voltage. The DMAG OVP will be triggered when the DMAG voltage over 3V continuously with 5 PWM cycles. This DMAG OVP is more accurate and faster than the VDD OVP function. A bypass capacitance (15~100pF) in DMAG pin is needed to avoid false trigger DOVP and malfunction. DMAG pin Pull Low Protection AOZ7523 provides a useful protection function in DMAG pin, when DMAG pin is pulled low below 0.3V and continuous with two switching cycles. The pull low current must be larger than 2mA. AOZ7523 will trigger DMAG pin pull low protection to protect system for user defined protection applications. Cycle-by-Cycle Current Limit The cycle-by-cycle current-limit protection circuit detects the inductor current and protects power MOSFET by turning off the output driver each cycle when the CS voltage becomes larger than preset voltage level. The voltage across the current detection resistor RCS connected to the GND is fed to the CS pin for current limit detection. www.aosmd.com Page 10 of 15 AOZ7523 There are two levels for current limit. The slow one, reference voltage set point is VCL = 0.9V. AOZ7523 offers 60ms de-bounce timer for counting to enter Over Load Protection (OLP) mode and the system will be autorecovery. The fast one, reference voltage set point is VCL2 = 1.5V. This protection function will be triggered, if the fast one comparator is continuously triggered by five times. This condition will be happened during transformer short or Secondary Side Diode Short (SSDS), and the circuit will induce large current in the primary-side. Over Load Protection (OLP) AOZ7523 provides Over Load Protection function to prevent the device of power supply system from operating with high stress. The OLP level was set by current sense resistor (RCS). OLP will be triggered when load condition is larger than preset level and continuous with 60ms (4096 clock cycles). CS Pin Open Protection The CS pin features open-loop protection to pass the CS pin single fault testing. When CS pin was opened, CS pin voltage will be pulled high by internal circuit. The pull high voltage was higher than VCL2 = 1.5V, such that SSDS protection will be triggered to protect system. CS Pin Short Protection CS pin features short to GND protection to pass the CS pin single fault testing. When CS pin is shorted to GND, it means the CS pin voltage is zero. When CS pin voltage is lower than 80mV with modulate minimum on-time and continuous triggered with 5 cycles, the CS pin short protection will be triggered to protect the power supply system. The detection duration are different between high line input voltage and low line input voltage to protect the component in high line input and detect precisely in low line input voltage. Thermal Shutdown AOZ7523 provides internal thermal shutdown protection for controller thermal run away. If the temperature of controller is higher than internal set point, the controller will stop PWM until the temperature cools down, below hysteresis of thermal shutdown set point. PCB Layout Guide A good PCB layout can minimize EMI and reduce unknown noise, which is helpful during ESD or lighting surge tests. The followings are good PCB layout guideline for an AC/DC adaptor: 1. Bridge rectifier output should directly connect to CBULK first, and use a neck layout to ensure the current flows into CBULK to get better EMI and reduce line frequency ripple. 2. Loop (a), CBULK → Transformer → MOSFET → RCS → CBULK (2), this loop is a high frequency and high current loop. The trace return to CBULK should be kept as short as possible and directly connect to CBULK ground. 3. Loop (b), the primary-side RCD snubber acts as a high frequency noise tank, it should be kept far away from the controller. The loop should be as short as possible. 4. Loop (c), the secondary-side snubber is a high frequency switching noise, too. The loop should be kept as short as possible. 5. The VDD decoupling capacitor CVDD needs to be placed close to IC, VDD and GND pin as much as possible. 6. Loop (d), Switching current sense (CS pin) is very important for a stable operation. Normally, a RC filter is recommended to reduce the noise applied to the CS pin. 7. If there’s a heat sink for the MOSFET, it should be connected to ground. 8. All ground for controller (4, 5, 6, 7, 8, 9, 10) should connect together first and then use a trace connect to CBULK ground (2) by a neck layout. 9. Loop (e), auxiliary power loop still needs to be kept short. CVDD should be placed close to the controller. This one also needs to use a trace to directly connect to CBULK ground (2) by neck layout. 10. Primary-side ground of Y-Cap (11), it needs to use a trace to directly connect to CBULK ground (2) by neck layout. Application Information 2 Alpha and Omega Semiconductor provides an EXCEL based design tool, an application note and a demonstration board to help the design of AOZ7523 and reduce the R&D cycle time. All the tools can be download from: www.aosmd.com. 11 1 4, 5, 6, 7, 9 8 10 3 Figure 24. Ground Group of Layout Recommended Rev. 1.0 January 2017 www.aosmd.com Page 11 of 15 AOZ7523 (a) (c) Load (b) 2 1 14 HV Drain Source (d) CS FB 3 7 12 VDD 4 13 5 GND Dmag 6 (e) 8 9 10 11 15 Figure 25. Main Loops for PCB Layout Considerations Figure 26. Recommended PCB Layout Rev. 1.0 January 2017 www.aosmd.com Page 12 of 15 AOZ7523 Package Dimensions, SO-13L GAUGE PLANE 0.25mm Package Dimensions, SO-13L C L 13 E1 1 2 E 3 D A2 A 004” (0.10mm) SEATING PLANE A1 b e e1 Dimensions in millimeters RECOMMENDED LAND PATTERN 2.20 2.54 5.74 2.87 1.27 0.80 0.63 Dimensions in inches Symbols A Min. 1.35 Nom. 1.60 Max. 1.75 Symbols A Min. 0.053 Nom. 0.063 Max. 0.069 A1 A2 0.10 — — 1.45 0.25 — A1 A2 0.004 — — 0.057 0.010 — b c D E1 e E 0.33 0.19 9.80 3.80 0.51 0.25 10.00 4.00 0.013 0.007 0.386 0.150 6.20 b c D E1 e E L θ e1 0.40 — 1.27 — 8° 2.54 TYP L θ e1 0.016 — — — 3.90 1.27 TYP 5.80 6.00 0° — 0.020 — 0.010 — 0.394 0.154 0.157 0.050 TYP 0.228 0.236 0.244 0° — 0.050 — 8° 0.100 TYP UNIT: mm Notes: 1. All dimensions are in millimeters. Tape and Reel Dimensions, SO-13L 2. Dimensions are inclusive of plating. 3. Package body size exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils each. 4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. 5. Paddle exposed on bottom. Rev. 1.0 January 2017 www.aosmd.com Page 13 of 15 AOZ7523 Tape and Reel Dimensions, SO-13L P0 Carrier Tape D0 A P2 K0 T E1 E2 E CL B1 B0 B2 K1 P1 Section A - A A1 D1 A A0 Feeding Direction UNIT: mm Package A0 B0 K0 K1 D0 D1 E E1 E2 P0 P1 P2 T B1 B2 A1 SO-13 6.50 10.30 2.30 1.80 1.55 1.60 16.00 1.75 7.50 4.00 8.00 2.00 0.30 REF. REF. REF. (16mm) ±0.10 ±0.10 ±0.10 ±0.10 ±0.05 ±0.10 ±0.30 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.05 6.6 1.5 3.5 Reel W3 (Include flange distortion at outer edge) M S K H N (Hub Dia.) W1 (Measured at Hub) W2 (Measured at Hub) T UNIT: mm Tape Size 16mm M ø332 MAX. N ø100.00 ±2.00 T 2.00 ±0.05 W1 16.40 +0.50/-0.20 W2 22.40 MAX. W3 15.9~19.4 S 2.20 TYP. K 10.10 MIN. H ø13.00 ±2.00 Leader/Trailer and Orientation Unit Per Reel: 3000pc Trailer Tape 300mm min. Rev. 1.0 January 2017 Components Tape Orientation in Pocket www.aosmd.com Leader Tape 500mm min. Page 14 of 15 AOZ7523 Part Marking AOZ7523XAI-XX (SO-13) Z7523XAIX FAYWLT Part Number Code Assembly Lot Code Fab & Assembly Location Year & Week Code LEGAL DISCLAIMER Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or completeness of the information provided herein and takes no liabilities for the consequences of use of such information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes to such information at any time without further notice. This document does not constitute the grant of any intellectual property rights or representation of non-infringement of any third party’s intellectual property rights. LIFE SUPPORT POLICY ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 1.0 January 2017 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 15 of 15