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DS280BR810
SNLS514C – NOVEMBER 2015 – REVISED OCTOBER 2019
DS280BR810 Low Power 28 Gbps 8 Channel Linear Repeater
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
•
Octal-Channel Multi-Protocol Linear Equalizer
Supporting up to 28-Gbps Interfaces
Low Power Consumption: 93 mW and Channel
(Typical)
No Heat Sink Required
Linear Equalization for Seamless Support of
CR4/KR4 Link Training
Extends Channel Reach by 15 dB+ Beyond
Normal ASIC-to-ASIC Capability
Ultra-Low Latency: 100 ps (Typical)
Low Additive Random Jitter
Small 8-mm x 13-mm BGA Package with
Integrated RX and TX AC Coupling Capacitors for
Easy Flow-Through Routing
Unique Pinout Allows Routing High-Speed Signals
Underneath the Package
Pin-Compatible Retimer Available
Single 2.5-V ±5% Power Supply
–40°C to +85°C Operating Temperature Range
The DS280BR810's small package dimensions,
optimized high-speed signal escape, and the pincompatible retimer portfolio make the DS280BR810
ideal for high-density backplane applications.
Simplified
equalization
control,
low
power
consumption, and ultra-low additive jitter make it
suitable for front-port interfaces such as 100 GSR4/LR4/CR4. The small 8-mm x 13-mm footprint
easily fits behind numerous standard front-port
connectors like QSFP28, SFP28, CFP2/CFP4, and
CDFP without the need for a heat sink.
Integrated AC coupling capacitors (RX and TX)
eliminate the need for external capacitors on the
PCB. The DS280BR810 has a single power supply
and minimal need for external components. These
features reduce PCB routing complexity and bill of
materials (BOM) cost.
A pin-compatible retimer device is available for longer
reach applications.
The DS280BR810 can be configured either via the
SMBus or through an external EEPROM. Up to 16
devices can share a single EEPROM.
Device Information
2 Applications
•
•
•
Backplane and Mid-Plane Reach Extension
Front-Port Eye Opener for Optical and Passive
Copper (100G-SR4/LR4/CR4)
QSFP28, SFP28, CFP2, CFP4, CDFP
PART NUMBER
DS280BR810
The linear nature of the DS280BR810’s equalization
preserves the transmit signal characteristics, thereby
allowing the host and link partner ASICs to freely
negotiate transmit equalizer coefficients (100 GCR4/KR4). This transparency to the link training
protocol facilitates system-level interoperability with
minimal effect on the latency. Each channel operates
independently, which allows the DS280BR810 to
support individual lane Forward Error Correction
(FEC) pass-through.
BODY SIZE (NOM)
8.00 mm x 13.00
mm
nFBGA (135)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
3 Description
The DS280BR810 is an extremely low-power, highperformance eight-channel linear equalizer supporting
multi-rate, multi-protocol interfaces up to 28 Gbps. It
is used to extend the reach and improve the
robustness of high-speed serial links for front-port,
backplane, and chip-to-chip applications.
PACKAGE
(1)
..
.
RX0P
TX0P
RX0N
..
.
TX0N
..
.
..
.
RX7P
TX7P
RX7N
TX7N
..
.
VDD
SMBus
Slave mode
SDA(1)
SDC(1)
1 NŸ
EN_SMB
To system SMBus
ADDR0
Address straps (pullup, pull-down, or float)
ADDR1
SMBus Slave
mode
READ_EN_N
ALL_DONE_N
Float for SMBus Slave mode,
RU FRQQHFW WR QH[W GHYLFH¶V
READ_EN_N for SMBus
Master mode
2.5 V
VDD
1 F
(2x)
GND
0.1 F
(4x)
(1) SMBus signals need to be pulled up elsewhere in the system.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS280BR810
SNLS514C – NOVEMBER 2015 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
6
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Electrical Characteristics -- Serial Management Bus
Interface ................................................................... 12
6.7 Timing Requirements -- Serial Management Bus
Interface ................................................................... 12
6.8 Typical Characteristics ............................................ 13
7
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
14
17
7.5 Programming........................................................... 18
7.6 Register Maps ........................................................ 19
8
Application and Implementation ........................ 29
8.1 Application Information............................................ 29
8.2 Typical Application ................................................. 29
8.3 Initialization Set Up ................................................ 41
9 Power Supply Recommendations...................... 41
10 Layout................................................................... 41
10.1 Layout Guidelines ................................................. 41
10.2 Layout Example .................................................... 41
11 Device and Documentation Support ................. 43
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
43
43
43
43
43
43
12 Mechanical, Packaging, and Orderable
Information ........................................................... 44
12.1 Package Option Addendum .................................. 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2017) to Revision C
•
2
Page
Initial Public Release .............................................................................................................................................................. 1
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SNLS514C – NOVEMBER 2015 – REVISED OCTOBER 2019
5 Pin Configuration and Functions
ZBF Package
135-Pin nfBGA
Top View
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
J
GND
GND
TX1N
GND
TX2N
GND
TX3N
GND
TX4N
GND
TX5N
GND
TX6N
GND
GND
J
H
TX0N
GND
TX1P
GND
TX2P
GND
TX3P
GND
TX4P
GND
TX5P
GND
TX6P
GND
TX7N
H
G
TX0P
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TX7P
G
F
GND
GND
READ
_EN_
N
SDC
GND
VDD
GND
VDD
GND
VDD
GND
GND
INT_N
(NC)
GND
GND
F
Control/Status pin
E
CAL_
CLK_
OUT
TEST
1
ADDR
1
SDA
GND
VDD
VDD
VDD
VDD
VDD
VDD
GND
EN_S
MB
TEST
0
CAL_
CLK_
IN
E
No connect on
package
D
GND
GND
ADDR
0
GND
GND
VDD
GND
VDD
GND
VDD
GND
GND
ALL_
DONE
_N
GND
GND
D
Test pin
C
RX0P
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RX7P
C
B
RX0N
GND
RX1P
GND
RX2P
GND
RX3P
GND
RX4P
GND
RX5P
GND
RX6P
GND
RX7N
B
A
GND
GND
RX1N
GND
RX2N
GND
RX3N
GND
RX4N
GND
RX5N
GND
RX6N
GND
GND
A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
Ground pin
High-speed pin
VDD
Power pin
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
HIGH SPEED DIFFERENTIAL I/O
RX0N
B15
Input
RX0P
C15
Input
RX1N
A13
Input
RX1P
B13
Input
RX2N
A11
Input
RX2P
B11
Input
RX3N
A9
Input
RX3P
B9
Input
RX4N
A7
Input
RX4P
B7
Input
RX5N
A5
Input
RX5P
B5
Input
RX6N
A3
Input
RX6P
B3
Input
RX7N
B1
Input
RX7P
C1
Input
TX0N
H15
Output
TX0P
G15
Output
Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination
resistor connects RXP to RXN. These inputs are AC coupled with 220-nF capacitors
assembled on the package substrate.
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package
substrate.
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Pin Functions (continued)
PIN
I/O
NAME
NO.
TX1N
J13
Output
TX1P
H13
Output
TX2N
J11
Output
TX2P
H11
Output
TX3N
J9
Output
TX3P
H9
Output
TX4N
J7
Output
TX4P
H7
Output
TX5N
J5
Output
TX5P
H5
Output
TX6N
J3
Output
TX6P
H3
Output
TX7N
H1
Output
TX7P
G1
Output
DESCRIPTION
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package
substrate.
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package
substrate.
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package
substrate.
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package
substrate.
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package
substrate.
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package
substrate.
Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential
inputs. These outputs are AC coupled with 220-nF capacitors assembled on the package
substrate.
CALIBRATION CLOCK PINS (FOR SUPPORTING UPGRADE PATH TO PIN-COMPATIBLE RETIMER DEVICE)
CAL_CLK_IN
E1
Input
CAL_CLK_O
UT
E15
Output
25-MHz (±100 PPM) 2.5-V single-ended clock from external oscillator. No stringent phase
noise or jitter requirements on this clock. A 25-MHz input clock is only required if there is
a need to support a future upgrade to the pin-compatible Retimer device. If there is no
need to support a future upgrade to a pin-compatible Retimer device, then a 25-MHz clock is
not required. this pin can be left floating. This input pin has a weak active pull down and can
be left floating if the CAL_CLK feature is not required.
2.5-V buffered replica of calibration clock input (pin E1) for connecting multiple devices in a
daisy-chained fashion.
SYSTEM MANAGEMENT BUS (SMBus) PINS
ADDR0
D13
ADDR1
E13
ALL_DONE_
N
EN_SMB
4
D3
E3
Input, 4-Level 4-level strap pins used to set the SMBus address of the device. The pin state is read on
power-up. The multi-level nature of these pins allows for 16 unique device addresses. The
four strap options include:
0: 1 kΩ to GND
Input, 4-Level R: 10 kΩ to GND
F: Float
1: 1 kΩ to VDD
Output,
LVCMOS
Indicates the completion of a valid EEPROM register load operation when in SMBus master
mode (EN_SMB = Float):
High = External EEPROM load failed or incomplete.
Low = External EEPROM load successful and complete.
When in SMBus slave mode (EN_SMB = 1), this output will be high-Z until READ_EN_N is
driven low, at which point ALL_DONE_N will be driven low. This behavior allows the reset
signal connected to READ_EN_N of one device to propagate to the subsequent devices
when ALL_DONE_N is connected to READ_EN_N in an SMBus slave mode application.
4-level 2.5 V input used to select between SMBus master mode (float) and SMBus slave
mode (high). The four defined levels are:
0: 1 kΩ to GND - RESERVED
Input, 4-Level
R: 10 kΩ to GND - RESERVED
F: Float - SMBus master mode
1: 1 kΩ to VDD - SMBus slave mode
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
Pin has weak pull-up.
This pin is 3.3 V tolerant.
READ_EN_N
F13
Input,
LVCMOS
SMBus master mode (EN_SMB = Float): When asserted low, initiates the SMBus master
mode EEPROM read function. Once EEPROM read is complete (indicated by assertion of
ALL_DONE_N low), this pin can be held low for normal device operation.
SMBus slave mode (EN_SMB = 1): When asserted low, this causes the device to be held in
reset (SMBus state machine reset and register reset). This pin should be pulled high or left
floating for normal operation in SMBus slave mode.
SDA
E12
I/O, 3.3-V
LVCMOS,
Open Drain
SMBus data input or open drain output. External 2 -Ω to 5-kΩ pull-up resistor is required.
This pin is 3.3-V LVCMOS tolerant.
SDC
F12
I/O, 3.3-V
LVCMOS,
Open Drain
SMBus clock input or open drain clock output. External 2-kΩ to 5-kΩ pull-up resistor is
required. This pin is 3.3-V LVCMOS tolerant.
No connect on package. For applications using multiple repeaters and retimers, this pin
should be connected to other devices’ INT_N pins. This is only a recommendation for cases
where there is a need to support a potential future upgrade to the pin-compatible retimer
device, which uses this pin as an interrupt signal to a system controller.
MISCELLANEOUS PINS
INT_N
F3
No Connect
TEST0
E2
Input,
LVCMOS
TEST1
E14
Input,
LVCMOS
GND
A1, A2, A4,
A6, A8, A10,
A12, A14,
A15, B2, B4,
B6, B8, B10,
B12, B14,
C2, C3, C4,
C5, C6, C7,
C8, C9, C10,
C11, C12,
C13, C14,
D1, D2, D4,
D5, D7, D9,
D11, D12,
D14, D15,
E4, E11, F1,
F2, F4, F5,
F7, F9, F11,
F14, F15,
G2, G3, G4,
G5, G6, G7,
G8, G9, G10,
G11, G12,
G13, G14,
H2, H4, H6,
H8, H10,
H12, H14, J1,
J2, J4, J6,
J8, J10, J12,
J14, J15
Power
Ground reference. The GND pins on this device should be connected through a lowimpedance path to the board GND plane.
VDD
D6, D8, D10,
E5, E6, E7,
E8, E9, E10,
F6, F8, F10
Power
Power supply, VDD = 2.5 V ±5%. Use at least six de-coupling capacitors between the
Repeater’s VDD plane and GND as close to the Repeater as possible. For example, four
0.1-μF capacitors and two 1-μF capacitors directly beneath the device or as close to the VDD
pins as possible. The VDD pins on this device should be connected through a low-resistance
path to the board VDD plane. For more information, see Power Supply Recommendations.
Reserved test pin. During normal (non-test-mode) operation, this pin is configured as an
input and therefore is not affected by the presence of a signal. This pin may be left floating,
tied to GND, or connected to a 2.5-V (max) output.
POWER
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted).
(1)
MIN
MAX
UNIT
VDDABSMAX
Supply voltage (VDD)
–0.5
2.75
V
VIO2.5V,ABSMAX
2.5 V I/O voltage (LVCMOS and CMOS)
–0.5
2.75
V
VIO3.3V,ABSMAX
Open drain and 3.3 V-tolerance I/O voltage (SDA, SDC,
READ_EN_N)
–0.5
4
V
VIOHS,ABSMAX
High-speed I/O voltage (RXnP, RXnN, TXnP, TXnN)
–0.5
2.75
V
TJABSMAX
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
-40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
(1)
(2)
UNIT
±2000
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2 kV
may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
VDD
Supply voltage, VDD to GND
DC plus AC power should not
exceed these limits
MIN
NOM
MAX
UNIT
2.375
2.5
2.625
V
Supply noise, DC to 10 MHz,
sinusoidal
10
mVpp
TRampVDD
VDD supply ramp time
TJ
Operating junction temperature
-40
110
C
TA
Operating ambient temperature
-40
85
C
VDDSMBUS
SMBus SDA and SDC Open
Drain Termination Voltage
3.6
V
FSMBus
SMBus clock (SDC) frequency in
SMBus slave mode
400
kHz
(1)
From 0 V to 2.375 V
150
Supply voltage for open drain
pull-up resistor
µs
Sinusoidal noise is superimposed to supply voltage with negligeable impact to device function or critical performance shown in the
Electrical Table.
6.4 Thermal Information
THERMAL METRIC
RθJA
(1)
6
(1)
Junction-to-ambient thermal resistance
CONDITIONS / ASSUMPTIONS
VALUE
4-layer JEDEC board
44.8
10-layer 8-in x 6-in board
26.8
20-layer 8-in x 6-in board
25.1
30-layer 8-in x 6-in board
25.4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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Thermal Information (continued)
THERMAL METRIC
(1)
VALUE
UNIT
RθJC(top)
Junction-to-case (top) thermal resistance
CONDITIONS / ASSUMPTIONS
26.5
°C/W
RθJB
Junction-to-board thermal resistance
28.4
°C/W
Junction-to-top characterization parameter
ψJT
Junction-to-board characterization parameter
ψJB
4-layer JEDEC board
13.1
10-layer 8-in x 6-in board
13.1
20-layer 8-in x 6-in board
13.2
30-layer 8-in x 6-in board
13.2
4-layer JEDEC board
25.4
10-layer 8-in x 6-in board
22.2
20-layer 8-in x 6-in board
21.8
30-layer 8-in x 6-in board
21.7
°C/W
°C/W
6.5 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
Wchannel
Wchannel_FIR
Wstatic_total
Power consumption per active channel
Idle (static) mode total device power
consumption
Active mode total device supply
current consumption
Itotal
Itotal_FIR
Istatic_total
(1)
Power consumption per active channel
Active mode total device supply
current consumption
Idle (static) mode total device supply
current consumption
Channel enabled and in linear mode
with maximum driver VOD
(DRV_SEL_VOD = 3).
Static power consumption not
included.
82
97
(1)
mW
Channel enabled and in linear mode
with minimum driver VOD
(DRV_SEL_VOD = 0).
Static power consumption not
included.
75
89
(1)
mW
Channel enabled and in FIR limiting
mode with C0 = 31 and maximum
driver VOD (DRV_SEL_VOD = 3).
Static power consumption not
included.
105
123
(1)
mW
Channel enabled and in FIR limiting
mode with C0 = 31 and minimum
driver VOD (DRV_SEL_VOD = 0).
Static power consumption not
included.
97
115
(1)
mW
Channels disabled and powered down
(DRV_PD = 1, EQ_PD = 1).
110
132
(1)
mW
All channels enabled and in linear
mode with maximum driver VOD
(DRV_SEL_VOD = 3).
307
347
mA
All channels enabled and in linear
mode with minimum driver VOD
(DRV_SEL_VOD = 0).
283
322
mA
All channels enabled and in FIR
limiting mode with C0 = 31 and
maximum driver VOD
(DRV_SEL_VOD = 3).
380
426
mA
All channels enabled and in FIR
limiting mode with C0 = 31 and
minimum driver VOD
(DRV_SEL_VOD = 0).
355
401
mA
44
50
mA
All channels disabled and powered
down
(DRV_PD = 1, EQ_PD = 1).
Max values assume VDD = 2.5 V + 5%.
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.75
VDD
V
1.75
3.6
V
GND
0.7
V
LVCMOS DC SPECIFICATIONS (CAL_CLK_IN, CAL_CLK_OUT, READ_EN_N, ALL_DONE_N, TEST[1:0])
VIH
High level input voltage
VIL
Low level input voltage
VOH
High level output voltage
IOH = 4 mA
VOL
Low level output voltage
IOL = –4 mA
0.4
V
Vinput = VDD, TEST[1:0] pins
16
µA
66
µA
1
µA
IIH
READ_EN_N pin only
Input high leakage current
2
Vinput = VDD, CAL_CLK_IN pin
Vinput = VDD, READ_EN_N pin
(2)
Vinput = 0 V, TEST[1:0] pins
IIL
V
Input low leakage current
–38
µA
Vinput = 0 V, CAL_CLK_IN pin
(3)
–1
µA
Vinput = 0 V, READ_EN_N pin
(2)
–55
µA
4-LEVEL LOGIC ELECTRICAL SPECIFICATIONS (APPLIES TO 4-LEVEL INPUT CONTROL PINS ADDR0, ADDR1, and EN_SMB)
IIH
Input high leakage current
IIL
Input low leakage current
105
–253
µA
µA
0.95 ×
VDD
V
0.67 ×
VDD
V
10K to GND input voltage
0.33 ×
VDD
V
Low level (0) input voltage
0.1
V
Measured with maximum CTLE setting
and maximum BW setting (EQ_BST1
= 7, EQ_BST2 = 7, EQ_BW = 3).
Boost is defined as the gain at 14 GHz
relative to 20 MHz.
22.5
dB
Measured with maximum CTLE setting
and maximum BW setting (EQ_BST1
= 7, EQ_BST2 = 7, EQ_BW = 3).
Boost is defined as the gain at 12.9
GHz relative to 20 MHz.
23
dB
Measured with minimum CTLE setting
and minimum BW setting (EQ_BST1 =
0, EQ_BST2 = 0, EQ_BW = 0,
EQ_EN_BYPASS = 1). Boost is
defined as the gain at 14 Ghz relative
to 20 MHz.
0.5
dB
Measured with minimum CTLE setting
and minimum BW setting (EQ_BST1 =
0, EQ_BST2 = 0, EQ_BW = 0,
EQ_EN_BYPASS = 1). Boost is
defined as the gain at 12.9 Ghz
relative to 20 MHz.
1
dB
High level (1) input voltage
Float level input voltage
VTH
HIGH-SPEED DIFFERENTIAL INPUTS (RXnP, RXnN)
BST
BST
(2)
(3)
8
CTLE high-frequency boost
CTLE high-frequency boost
This pin has an internal weak pull-up.
This pin has an internal weak pull-down.
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Copyright © 2015–2019, Texas Instruments Incorporated
Product Folder Links: DS280BR810
DS280BR810
www.ti.com
SNLS514C – NOVEMBER 2015 – REVISED OCTOBER 2019
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
BSTdelta
BSTdelta
RLSDD11
RLSDC11
RLSCC11
VSDAT
VSDDT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Measured with maximum CTLE setting
(EQ_BST1 = 7, EQ_BST2 = 7). Gain
variation is defined as the total change
in gain at 14 GHz due to temperature
and voltage variation.
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