DS280MB810ZBLT

DS280MB810 DS280MB810 SNLS542C – OCTOBER 2016 – REVISED DECEMBER 2020 SNLS542C – OCTOBER 2016 – REVISED DECEMBER 2020 www.ti.com DS280MB810 Low Power 28 Gbps 8 Channel Linear Repeater with Cross-point 1 Features • • • • • • • • • • • • • Octal-Channel Multi-Protocol Linear Equalizer Supporting up to 28 Gbaud NRZ Interfaces Integrated 2x2 Cross-point with Pin or Register Control for Mux, Fanout, and Signal Crossing Applications Low Power Consumption: 93 mW / Channel (Typical) No Heat Sink Required Linear Equalization for Seamless Support of Link Training, Auto-Negotiation, and FEC PassThrough Extends Channel Reach by 17dB+ Beyond Normal ASIC-to-ASIC Capability at 14 GHz Ultra-Low Latency: 100 ps (Typical) Low Additive Random Jitter Small 8 mm x 13 mm BGA Package with Integrated RX AC Coupling Capacitors for Easy Flow-Through Routing Unique Pinout Allows Routing High-Speed Signals Underneath the Package Pin-Compatible Retimer with Cross-point Available Single 2.5-V ±5% Power Supply –40°C to +85°C Operating Temperature Range allowing the host and link partner ASICs to freely negotiate transmit equalizer coefficients (100G-CR4/ KR4). This transparency to the link training protocol facilitates system-level interoperability with minimal effect on the latency. The DS280MB810 supports twolevel pulse amplitude modulation (PAM), or NRZ, for symbol rates up to 28 Gbaud and peak signal amplitude within the linear operating range. Each channel operates independently, and every channel can be configured uniquely. In most application scenarios, the same configuration can be used regardless of data rate. The DS280MB810's small package dimensions, optimized high-speed signal escape, and the pincompatible Retimer portfolio make the DS280MB810 ideal for high-density backplane applications. Simplified equalization control, low power consumption, and ultra-low additive jitter make it suitable for front-port interfaces such as 100GSR4/LR4/CR4. The small 8-mm x 13-mm footprint easily fits behind numerous standard front-port connectors like QSFP, SFP, CFP, and CDFP without the need for a heat sink. Device Information (1) PART NUMBER 2 Applications DS280MB810 • (1) • • Backplane and Mid-Plane Signal Distribution Plus Equalization Mux and De-Mux for Failover Redundancy Front-Port Eye Opener Plus Signal Distribution for Switching Between Ports The DS280MB810 includes a full 2x2 cross-point switch between each pair of adjacent channels which enables 2-to-1 multiplexing and 1-to-2 de-multiplexing applications for failover redundancy, as well as signal cross-over to aid PCB routing. The cross-point can be controlled through pins or the SMBus register interface. BODY SIZE (NOM) 8.0 mm x 13.0 mm For all available packages, see the orderable addendum at the end of the data sheet. RX0P RX0N TX0P TX0N X RX1P 3 Description The DS280MB810 is an extremely low-power, highperformance eight-channel linear equalizer supporting multi-rate, multi-protocol interfaces up to 28 Gbaud NRZ. It is used to extend the reach and improve the robustness of high-speed serial links for backplane, front-port, and chip-to-chip applications. PACKAGE nFBGA(135) RX1N . . . . . . TX1P TX1N . . . RX6P . . . . . . TX6P TX6N RX6N X RX7P VDD SMBus Slave mode RX7N SDA(1) SDC(1) 1 NŸ READ_EN_N VDD Address straps (pull-up, pull-down, or float) ADDR1 ALL_DONE_N 2.5 V 1 F (2x) To system SMBus ADDR0 EN_SMB SMBus Slave mode TX7P TX7N GND Float for SMBus Slave mode, or connect to next GHYLFH¶V 5($'_EN_N for SMBus Master mode 0.1 F (4x) (1) SMBus signals need to be pulled up elsewhere in the system. The linear nature of the DS280MB810’s equalization preserves the transmit signal characteristics, thereby Simplified Schematic An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2020 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: DS280MB810 1 DS280MB810 www.ti.com SNLS542C – OCTOBER 2016 – REVISED DECEMBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Description (continued).................................................. 3 6 Pin Configuration and Functions...................................3 7 Specifications.................................................................. 7 7.1 Absolute Maximum Ratings........................................ 7 7.2 ESD Ratings............................................................... 7 7.3 Recommended Operating Conditions.........................7 7.4 Thermal Information....................................................8 7.5 Electrical Characteristics.............................................8 7.6 Timing Requirements – Serial Management Bus Interface...................................................................... 13 7.7 Typical Characteristics.............................................. 14 8 Detailed Description......................................................15 8.1 Overview................................................................... 15 8.2 Functional Block Diagram......................................... 15 8.3 Feature Description...................................................16 8.4 Device Functional Modes..........................................18 8.5 Programming............................................................ 20 8.6 Register Maps...........................................................21 9 Application and Implementation.................................. 32 9.1 Application Information............................................. 32 9.2 Typical Application.................................................... 32 9.3 Initialization Set Up................................................... 43 10 Power Supply Recommendations..............................43 11 Layout........................................................................... 45 11.1 Layout Guidelines................................................... 45 11.2 Layout Examples.....................................................45 12 Device and Documentation Support..........................48 12.1 Documentation Support.......................................... 48 12.2 Receiving Notification of Documentation Updates..48 12.3 Support Resources................................................. 48 12.4 Trademarks............................................................. 48 13 Mechanical, Packaging, and Orderable Information.................................................................... 49 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (October 2019) to Revision C (December 2020) Page • Changed data rate support to indicate that only NRZ is supported.................................................................... 1 • Removed support for PAM4 28 GBd interfaces..................................................................................................1 Changes from Revision A (September 2017) to Revision B (October 2019) Page • First Public Release............................................................................................................................................1 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS280MB810 DS280MB810 www.ti.com SNLS542C – OCTOBER 2016 – REVISED DECEMBER 2020 5 Description (continued) Integrated AC coupling capacitors (RX side) eliminate the need for external capacitors on the PCB. The DS280MB810 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and bill of materials (BOM) cost. A pin-compatible Retimer device with cross-point is available for longer reach applications. The DS280MB810 can be configured either through the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM. 6 Pin Configuration and Functions Legend 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 J GND GND TX1N GND TX2N GND TX3N GND TX4N GND TX5N GND TX6N GND GND J H TX0N GND TX1P GND TX2P GND TX3P GND TX4P GND TX5P GND TX6P GND TX7N H G TX0P GND GND GND GND GND GND GND GND GND GND GND GND GND TX7P G F GND GND READ_ EN_N SDC GND VDD GND VDD GND VDD GND GND INT_N (NC) GND GND F Control/Status pin E CAL_ CLK_ OUT M UXSEL1 _TEST1 ADDR1 SDA GND VDD VDD VDD VDD VDD VDD GND EN_SM B M UXSEL0 _TEST0 CAL_ CLK_ IN E No connect on package D GND GND ADDR0 GND GND VDD GND VDD GND VDD GND GND ALL_ DONE_ N GND GND D C RX0P GND GND GND GND GND GND GND GND GND GND GND GND GND RX7P C B RX0N GND RX1P GND RX2P GND RX3P GND RX4P GND RX5P GND RX6P GND RX7N B A GND GND RX1N GND RX2N GND RX3N GND RX4N GND RX5N GND RX6N GND GND A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND Ground pin High-speed pin VDD Power pin Figure 6-1. Top View Table 6-1. Pin Functions PIN NAME NO. I/O DESCRIPTION High Speed Differential I/O RX0P C15 Input RX0N B15 Input RX1P B13 Input RX1N A13 Input RX2P B11 Input RX2N A11 Input RX3P B9 Input RX3N A9 Input RX4P B7 Input RX4N A7 Input RX5P B5 Input RX5N A5 Input Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors assembled on the package substrate. Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors assembled on the package substrate. Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors assembled on the package substrate. Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors assembled on the package substrate. Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors assembled on the package substrate. Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors assembled on the package substrate. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS280MB810 3 DS280MB810 SNLS542C – OCTOBER 2016 – REVISED DECEMBER 2020 www.ti.com Table 6-1. Pin Functions (continued) PIN I/O NAME NO. RX6P B3 Input RX6N A3 Input RX7P C1 Input RX7N B1 Input TX0P G15 Output TX0N H15 Output TX1P H13 Output TX1N J13 Output TX2P H11 Output TX2N J11 Output TX3P H9 Output TX3N J9 Output TX4P H7 Output TX4N J7 Output TX5P H5 Output TX5N J5 Output TX6P H3 Output TX6N J3 Output TX7P G1 Output TX7N H1 Output DESCRIPTION Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors assembled on the package substrate. Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ω termination resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors assembled on the package substrate. Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Calibration Clock Pins (For Supporting Upgrade Path to Pin-Compatible Retimer Device) CAL_CLK_IN E1 Input CAL_CLK_ OUT E15 Output 25-MHz (±100 PPM) 2.5-V single-ended clock from external oscillator. No stringent phase noise or jitter requirements on this clock. A 25-MHz input clock is only required if there is a need to support a future upgrade to the pin-compatible Retimer device. If there is no need to support a future upgrade to a pin-compatible Retimer device, then a 25-MHz clock is not required. This input pin has a weak active pull down and can be left floating if the CAL_CLK feature is not required. 2.5-V buffered replica of calibration clock input (pin E1) for connecting multiple devices in a daisy-chained fashion. System Management Bus (SMBus) Pins 4 ADDR0 D13 ADDR1 E13 Input, 4-Level 4-level strap pins used to set the SMBus address of the device. The pin state is read on power-up. The multi-level nature of these pins allows for 16 unique device addresses, see Table 8-1. The four strap options include: 0: 1 kΩ to GND Input, 4-Level R: 10 kΩ to GND F: Float 1: 1 kΩ to VDD 4-level 2.5-V input used to select between SMBus master mode (float) and SMBus slave mode (high). The four defined levels are: 0: 1 kΩ to GND - RESERVED Input, 4-Level R: 10 kΩ to GND - RESERVED, TI test mode F: Float - SMBus master mode 1: 1 kΩ to VDD - SMBus slave mode EN_SMB E3 SDA E12 I/O, 3.3 V LVCMOS, Open Drain SMBus data input or open drain output. External 2-kΩ to 5-kΩ pull-up resistor is required. This pin is 3.3-V LVCMOS tolerant. SDC F12 I/O, 3.3 V LVCMOS, Open Drain SMBus clock input or open drain clock output. External 2-kΩ to 5-kΩ pull-up resistor is required. This pin is 3.3-V LVCMOS tolerant. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS280MB810 DS280MB810 www.ti.com SNLS542C – OCTOBER 2016 – REVISED DECEMBER 2020 Table 6-1. Pin Functions (continued) PIN NAME NO. READ_EN_N F13 ALL_DONE_ N D3 I/O DESCRIPTION Input, 3.3 V LVCMOS SMBus master mode (EN_SMB = Float): When asserted low, initiates the SMBus master mode EEPROM read function. Once EEPROM read is complete (indicated by assertion of ALL_DONE_N low), this pin can be held low for normal device operation. SMBus slave mode (EN_SMB = 1 kΩ to VDD): When asserted low, this causes the device to be held in reset (SMBus state machine reset and register reset). This pin should be pulled high or left floating for normal operation in SMBus slave mode. This pin has an internal weak pull-up and is 3.3-V LVCMOS tolerant. Output, LVCMOS Indicates the completion of a valid EEPROM register load operation when in SMBus master mode (EN_SMB = Float): High = External EEPROM load failed or incomplete. Low = External EEPROM load successful and complete. When in SMBus slave mode (EN_SMB = 1 kΩ to VDD), this output will be high-Z until READ_EN_N is driven low, at which point ALL_DONE_N will be driven low. This behavior allows the reset signal connected to READ_EN_N of one device to propagate to the subsequent devices when ALL_DONE_N is connected to READ_EN_N in an SMBus slave mode application. Miscellaneous Pins No connect on package. For applications using DS280MB810 and pin-compatible TI No connect in Retimers, this pin can be connected to other devices’ INT_N pins. This is a recommendation package for cases where there is a need to support a potential future upgrade to the pin-compatible Retimer device, which uses this pin as an interrupt signal to a system controller. INT_N F3 MUXSEL0_ TEST0 E2 Input, LVCMOS MUXSEL1_ TEST1 E14 Input, LVCMOS When operating the cross-point in pin-control mode (Shared Reg_0x05[1]=1), MUXSEL0 controls the cross-point for channels 0–1 and 4–5, and MUXSEL1 controls the cross-point for channels 2–3 and 6–7. If these pins are not used for cross-point control, they may be left floating or tied to GND. These pins also serve as TI test pins when in test mode (EN_SMB = 10 kΩ to GND). These pins have an internal weak pull-up. Power Power Power supply, VDD = 2.5 V +/- 5%. Use at least six de-coupling capacitors between the Repeater’s VDD plane and GND as close to the Repeater as possible. For example, four 0.1-μF capacitors and two 1-μF capacitors directly beneath the device or as close to the VDD pins as possible. The VDD pins on this device should be connected through a lowresistance path to the board VDD plane. For more information, see Section 10. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback VDD D6, D8, D10, E5, E6, E7, E8, E9, E10, F6, F8, F10 Product Folder Links: DS280MB810 5 DS280MB810 SNLS542C – OCTOBER 2016 – REVISED DECEMBER 2020 www.ti.com Table 6-1. Pin Functions (continued) PIN NAME GND 6 NO. A1, A2, A4, A6, A8, A10, A12, A14, A15, B2, B4, B6, B8, B10, B12, B14, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, D1, D2, D4, D5, D7, D9, D11, D12, D14, D15, E4, E11, F1, F2, F4, F5, F7, F9, F11, F14, F15, G2, G3, G4, G5, G6, G7, G8, G9, G10, G11, G12, G13, G14, H2, H4, H6, H8, H10, H12, H14, J1, J2, J4, J6, J8, J10, J12, J14, J15 I/O Power DESCRIPTION Ground reference. The GND pins on this device should be connected through a lowimpedance path to the board GND plane. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS280MB810 DS280MB810 www.ti.com SNLS542C – OCTOBER 2016 – REVISED DECEMBER 2020 7 Specifications 7.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted). (1) MIN MAX UNIT Supply voltage (VDD) -0.5 2.75 V VIO2.5V,ABSMAX 2.5 V I/O voltage (LVCMOS and CMOS) -0.5 2.75 V VIO3.3V,ABSMAX Open drain and 3.3 V-tolerance I/O voltage (SDA, SDC, READ_EN_N) -0.5 4.0 V VIOHS,ABSMAX High-speed I/O voltage (RXnP, RXnN, TXnP, TXnN) -0.5 2.75 V TJABSMAX Junction temperature 150 °C Tstg Storage temperature range 150 °C VDDABSMAX (1) -40 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) (1) (2) UNIT ±1500 V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2 kV may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted). VDD Supply voltage, VDD to GND Supply noise tolerance (1) NVDD MIN NOM MAX UNIT 2.375 2.5 2.625 V Supply noise, DC to 10 MHz, sinusoidal 10 mVpp DC plus AC power should not exceed these limits TRampVDD VDD supply ramp time TJ Operating junction temperature -40 110 C TA Operating ambient temperature -40 85 C VDDSMBUS SMBus SDA and SDC Open Drain Termination Voltage 3.6 V FSMBus SMBus clock (SDC) frequency in SMBus slave mode 400 kHz (1) From 0 V to 2.375 V 150 Supply voltage for open drain pull-up resistor µs Sinusoidal noise is superimposed to supply voltage with negligible impact to device function or critical performance shown in the Electrical Table. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS280MB810 7 DS280MB810 www.ti.com SNLS542C – OCTOBER 2016 – REVISED DECEMBER 2020 7.4 Thermal Information DS280MB810 THERMAL METRIC(1) CONDITIONS/ASSUMPTIONS(2) nFBGA UNIT 135 PINS RθJA Junction-to-ambient thermal resistance 4-Layer JEDEC Board 45.2 10-Layer 8-in x 6-in Board 26.3 20-Layer 8-in x 6-in Board 24.8 30-Layer 8-in x 6-in Board 22.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 4-Layer JEDEC Board 26.6 °C/W RθJB Junction-to-board thermal resistance 4-Layer JEDEC Board 25.8 °C/W ΨJT Junction-to-top characterization parameter ΨJB (1) (2) Junction-to-board characterization parameter 4-Layer JEDEC Board 13.3 10-Layer 8-in x 6-in Board 13.0 20-Layer 8-in x 6-in Board 13.0 30-Layer 8-in x 6-in Board 13.0 4-Layer JEDEC Board 22.8 10-Layer 8-in x 6-in Board 21.4 20-Layer 8-in x 6-in Board 21.1 30-Layer 8-in x 6-in Board 20.8 °C/W °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. No heat sink or airflow was assumed for these estimations. Depending on the application, a heat sink, faster airflow, or reduced ambient temperature (