QX9775

Intel® Core™2 Extreme Processor QX9775Δ Datasheet February 2008 Document Number:319128-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Core™2 Extreme processor QX9775 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details. Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/info/em64t for more information including details on which processors support Intel 64, or consult with your system vendor for more information. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. ± Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. ‡ Not all specified units of this processor support Enhanced Intel SpeedStep® Technology. See the Processor Spec Finder at http:/ /processorfinder.intel.com or contact your Intel representative for more information. Not all specified units of this processor support Thermal Monitor 2, Enhanced HALT State and Enhanced Intel SpeedStep® Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information. Warning: Altering clock frequency and/or voltage may (i) reduce system stability and useful life of the system and processor; (ii) cause the processor and other system components to fail; (iii) cause reductions in system performance; (iv) cause additional heat or other damage; and (v) affect system data integrity. Intel has not tested, and does not warranty, the operation of the processor beyond its specifications. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Core, speedStep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2008, Intel Corporation. 2 Datasheet Contents 1 Introduction................................................................................................................. 9 1.1 Terminology ..................................................................................................... 10 1.2 References ....................................................................................................... 12 Electrical Specifications ............................................................................................... 13 2.1 Front Side Bus and GTLREF ................................................................................ 13 2.2 Power and Ground Lands.................................................................................... 13 2.3 Decoupling Guidelines ........................................................................................ 14 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ....................................... 15 2.5 Voltage Identification (VID) ................................................................................ 17 2.6 Reserved, Unused, and Test Signals..................................................................... 19 2.7 Front Side Bus Signal Groups .............................................................................. 20 2.8 CMOS Asynchronous and Open Drain Asynchronous Signals .................................... 22 2.9 Test Access Port (TAP) Connection....................................................................... 22 2.10 Platform Environmental Control Interface (PECI) DC Specifications........................... 22 2.11 Mixing Processors.............................................................................................. 24 2.12 Absolute Maximum and Minimum Ratings ............................................................. 24 2.13 Processor DC Specifications ................................................................................ 25 2.14 AGTL+ FSB Specifications................................................................................... 32 Mechanical Specifications............................................................................................. 35 3.1 Package Mechanical Drawings ............................................................................. 35 3.2 Processor Component Keepout Zones................................................................... 39 3.3 Package Loading Specifications ........................................................................... 39 3.4 Package Handling Guidelines............................................................................... 40 3.5 Package Insertion Specifications.......................................................................... 40 3.6 Processor Mass Specifications ............................................................................. 40 3.7 Processor Materials............................................................................................ 40 3.8 Processor Markings............................................................................................ 41 3.9 Processor Land Coordinates ................................................................................ 42 Land Listing and Signal Description ............................................................................... 45 4.1 Land Listing...................................................................................................... 45 4.2 Signal Definitions .............................................................................................. 64 Thermal Specifications ................................................................................................ 75 5.1 Package Thermal Specifications ........................................................................... 75 5.2 Processor Thermal Features ................................................................................ 78 5.3 Platform Environment Control Interface (PECI) ...................................................... 81 Features.................................................................................................................... 85 6.1 Power-On Configuration Options.......................................................................... 85 6.2 Clock Control and Low Power States .................................................................... 85 6.3 Enhanced Intel SpeedStep® Technology .............................................................. 89 2 3 4 5 6 Datasheet 3 Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 3-2 3-3 3-4 3-5 3-6 3-7 5-1 5-2 5-3 5-4 5-5 6-1 Input Device Hysteresis.............................................................................................23 Processor Load Current versus Time............................................................................27 Processor VCC Static and Transient Tolerance Load Lines ..............................................29 VCC Overshoot Example Waveform .............................................................................31 Differential Clock Waveform .......................................................................................34 Differential Clock Crosspoint Specification ....................................................................34 Differential Rising and Falling Edge Rates.....................................................................34 Processor Package Assembly Sketch ...........................................................................35 Processor Package Drawing (Sheet 1 of 3) ...................................................................36 Processor Package Drawing (Sheet 2 of 3) ...................................................................37 Processor Package Drawing (Sheet 3 of 3) ...................................................................38 Processor Top-side Markings (Example).......................................................................41 Processor Land Coordinates, Top View.........................................................................42 Processor Land Coordinates, Bottom View....................................................................43 Processor Thermal Profile ..........................................................................................76 Case Temperature (TCASE) Measurement Location .......................................................78 Thermal Monitor 2 Frequency and Voltage Ordering ......................................................80 Processor PECI Topology ...........................................................................................82 Conceptual Fan Control Diagram of PECI-based Platforms ..............................................83 Stop Clock State Machine ..........................................................................................86 Tables 2-1 Core Frequency to FSB Multiplier Configuration.............................................................15 2-2 BSEL[2:0] Frequency Table........................................................................................16 2-3 Voltage Identification Definition ..................................................................................18 2-4 Loadline Selection Truth Table for LL_ID[1:0]...............................................................19 2-5 Market Segment Selection Truth Table for MS_ID[1:0] ..................................................19 2-6 FSB Signal Groups ....................................................................................................20 2-7 AGTL+ Signal Description Table..................................................................................21 2-8 Non AGTL+ Signal Description Table ...........................................................................21 2-9 Signal Reference Voltages .........................................................................................22 2-10PECI DC Electrical Limits ...........................................................................................23 2-11Processor Absolute Maximum Ratings..........................................................................25 2-12Voltage and Current Specifications..............................................................................26 2-13Processor VCC Static and Transient Tolerance ..............................................................28 2-14AGTL+ Signal Group DC Specifications ........................................................................29 2-15CMOS Signal Input/Output Group and TAP Signal Group DC Specifications......................................................................................................30 2-16Open Drain Output Signal Group DC Specifications........................................................30 2-17VCC Overshoot Specifications.....................................................................................30 2-18AGTL+ Bus Voltage Definitions ...................................................................................32 2-19FSB Differential BCLK Specifications ............................................................................33 3-1 Package Loading Specifications...................................................................................39 3-2 Package Handling Guidelines......................................................................................40 3-3 Processor Materials ...................................................................................................40 4-1 Land Listing by Land Name ........................................................................................46 4-2 Land Listing by Land Number .....................................................................................55 4-1 Signal Definitions .....................................................................................................64 5-1 Processor Thermal Specifications ................................................................................76 5-2 Processor Thermal Profile Table ..................................................................................77 5-3 GetTemp0() GetTemp1()Error Codes...........................................................................84 6-1 Power-On Configuration Option Lands .........................................................................85 6-2 Extended HALT Maximum Power.................................................................................87 4 Datasheet Revision History Revision -001 Initial release Description Date February 2008 Datasheet 5 6 Datasheet Intel® Core™2 Extreme Processor QX9775Δ Features • Available at 3.2 GHz • FSB frequency at 1600 MHz • Enhanced Intel Speedstep® Technology • Supports Intel® 64Φ architecture • Supports Intel® Virtualization Technology • Supports Execute Disable Bit capability • Binary compatible with applications running on previous members of the Intel microprocessor line • Intel® Wide Dynamic Execution • Intel® Advanced Smart Cache • Intel® Smart Memory Access • Intel® Intelligent Power Capability • Intel® Advanced Digital Media Boost • Optimized for 32-bit applications running on advanced 32-bit operating systems • Two 6 MB Level 2 caches • Intel® HD Boost utilizing new SSE4 instructions for improved multimedia performance, especially for video encoding and photo processing • System Management mode • 24-way cache associativity provides improved cache hit rate on load/store operations • 771-land Package The Intel Core™2 Extreme processor QX9775, designed for dual-socket configurations, delivers Intel's most advanced processor for professional multimedia content creation and for intense visual gaming. The processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. § Datasheet 7 8 Datasheet Introduction 1 Introduction The Intel® Core™2 Extreme processor QX9775 is a server/workstation processor using four 45-nm Hi-k next generation Intel® Core™ microarchitecture cores. The processor is manufactured on Intel’s 45 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. The Intel® Core™2 Extreme processor QX9775 maintains the tradition of compatibility with IA-32 software. Note: For this document, Intel® Core™2 Extreme processor QX9775 is referred to as “processor”. Key processor features include on-die, primary 32-kB instruction cache and 32-kB writeback data cache in each core and 12 MB (2 x 6 MB) Level 2 cache with Intel® Advanced Smart Cache Architecture. The processors’ Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in reduced effective bus latency and improved performance. The 1600 MHz Front Side Bus (FSB) is a quadpumped bus running from a 400 MHz system clock making 12.80 GBytes per second data transfer rates possible. Enhanced thermal and power management capabilities are implemented including Intel® Thermal Monitor (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel SpeedStep® Technology. These technologies are targeted for dual processor configurations in enterprise environments. TM1 and TM2 provide efficient and effective cooling in high temperature situations. Enhanced Intel SpeedStep Technology provides power management capabilities to servers and workstations. Processor features also include Intel® Wide Dynamic Execution, enhanced floating point and multi-media units, Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), and Streaming SIMD Extensions 4.1 (SSE4.1). Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor. The floating point and multi-media units include 128-bit wide registers and a separate register for data movement. SSE3 instructions provide highly efficient double-precision floating point, SIMD integer, and memory management operations. The processor supports Intel® 64 Architecture as an enhancement to Intel's IA-32 architecture. This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64-bit extension technology. Further details on Intel® 64 Architecture and its programming model can be found in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, at http://www.intel.com/ products/processor/manuals/. In addition, the processor supports the Execute Disable Bit functionality. When used in conjunction with a supporting operating system, Execute Disable allows memory to be marked as executable or non executable. This feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. Further details on Execute Disable can be found at http:// www.intel.com/cd/ids/developer/asmo-na/eng/149308.htm. The processor supports Intel® Virtualization Technology for hardware-assisted virtualization within the processor. Intel Virtualization Technology is a set of hardware enhancements that can improve virtualization solutions. Intel Virtualization Technology is used in conjunction with Virtual Machine Monitor software enabling multiple, independent software environments inside a single platform. Further details on Intel Virtualization Technology can be found at http://developer.intel.com/technology/ platform-technology/virtualization/index.htm. Datasheet 9 Introduction The processor is intended for high performance server and workstation systems. The processor supports a Dual Independent Bus (DIB) architecture with one processor on each bus, up to two processor sockets in a system. The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth. The processor is packaged in an FC-LGA Land Grid Array package with 771 lands for improved power delivery. It uses a surface mount LGA771 socket that supports Direct Socket Loading (DSL). The Intel® Core™2 Extreme processor QX9775-based platforms implement independent core voltage (VCC) power planes for each processor. FSB termination voltage (VTT) is shared and must connect to all FSB agents. The processor core voltage uses power delivery guidelines specified by VRM/EVRD 11.0 and its associated load line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details). VRM/EVRD 11.0 will support the power requirements of all frequencies of the processor. The processor supports a1600 MHz Front Side Bus operations. The FSB uses a splittransaction, deferred reply protocol and Source-Synchronous Transfer (SST) of address and data to improve performance. The processor transfers data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a ‘doubleclocked’ or a 2X address bus. In addition, the Request Phase completes in one clock cycle. The FSB is also used to deliver interrupts. Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages. Section 2.1 contains the electrical specifications of the FSB. 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level). Commonly used terms are explained here for clarification: • Intel® Core™2 Extreme processor QX9775 – Intel® 64-bit microprocessor intended for dual processor desktops. The processor is based on Intel’s 45 nanometer process, and packaged in the FC-LGA package with four processor cores. • FC-LGA (Flip Chip Land Grid Array) Package – The processor package is a Land Grid Array, consisting of a processor core mounted on a pinless substrate with 771 lands, and includes an integrated heat spreader (IHS). • LGA771 socket – The processor interfaces to the baseboard through this surface mount, 771 Land socket. See the LGA771 Socket Design Guidelines for details regarding this socket. • Processor core – Processor core with integrated L1 cache. L2 cache and system bus interface are shared between the two cores on the die. All AC timing and signal integrity specifications are at the pads of the system bus interface. • Front Side Bus (FSB) – The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions, as well as interrupt messages, pass between the processor and chipset over the FSB. • Dual Independent Bus (DIB) – A front side bus architecture with one processor on each of several processor buses, rather than a processor bus shared between 10 Datasheet Introduction • • • • • • • • • • • • • • • two processor agents. The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth. Functional Operation – Refers to the normal operating conditions in which all processor specifications, including DC, AC, FSB, signal quality, mechanical and thermal are satisfied. Storage Conditions – Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (that is, unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. Priority Agent – The priority agent is the host bridge to the processor and is typically known as the chipset. Symmetric Agent – A symmetric agent is a processor which shares the same I/O subsystem and memory array, and runs the same operating system as another processor in a system. Systems using symmetric agents are known as Symmetric Multiprocessing (SMP) systems. Integrated Heat Spreader (IHS) – A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface. Thermal Design Power (TDP) – Processor thermal solutions should be designed to meet this target. It is the highest expected sustainable power while running known power intensive applications. TDP is not the maximum power that the processor can dissipate. Intel®64 Architecture – An enhancement to Intel's IA-32 architecture that allows the processor to execute operating systems and applications written to take advantage of the 64-bit extension technology. Enhanced Intel SpeedStep® Technology – Technology that provides power management capabilities to servers and workstations. Platform Environment Control Interface (PECI) – A proprietary one-wire bus interface that provides a communication channel between Intel processor and external thermal monitoring devices, for use in fan speed control. PECI communicates readings from the processor’s digital thermometer. PECI replaces the thermal diode available in previous processors. Intel® Virtualization Technology – Processor virtualization, which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. VRM (Voltage Regulator Module) – DC-DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and current to the processor based on the logic state of the processor VID bits. EVRD (Enterprise Voltage Regulator Down) – DC-DC converter integrated onto the system board that provides the correct voltage and current to the processor based on the logic state of the processor VID bits. VCC – The processor core power supply. VSS – The processor ground. VTT – FSB termination voltage. Datasheet 11 Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Document Intel® Core™2 Extreme Processor QX9775 Specification Update Intel® Core™2 Extreme Processor QX9775 Thermal and Mechanical Design Guidelines Addendum (TMDG) Location http://www.intel.com/ design/processor/ specupdt/319129.htm http://www.intel.com/ design/processor/ designex/319130.htm http://www.intel.com/ design/xeon/guides/ 313871.htm http://www.intel.com/ design/processor/ applnots/313214.htm http://www.intel.com/ design/processor/ applnots/241618.htm LGA771 Socket Mechanical Design Guide Voltage Regulator Module (VRM) and Enterprise Voltage RegulatorDown (EVRD) 11.0 Design Guidelines AP-485, Intel® Processor Identification and the CPUID Instruction Intel® 64 and IA-32 Intel Architecture Software Developer's Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide Intel® 64 and IA-32 Intel® Architecture Optimization Reference Manual Intel® 64 and IA-32 Intel® Software Developer's Manual Documentation Changes http://www.intel.com/ products/processor/ manuals/ http://www.intel.com/ products/processor/ manuals/ http://www.intel.com/ products/processor/ manuals/ § § 12 Datasheet Electrical Specifications 2 2.1 Electrical Specifications Front Side Bus and GTLREF Most processor FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high logic level and termination. AGTL+ output buffers differ from GTL+ buffers with the addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during the first clock of a low-to-high voltage transition. Platforms implement a termination voltage level for AGTL+ signals defined as VTT. Because platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address buses have made signal integrity considerations and platform design methods even more critical than with previous processor families. The AGTL+ inputs require reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END) which are used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF_DATA_MID and GTLREF_DATA_END is used for the 4X front side bus signaling group and GTLREF_ADD_MID and GTLREF_ADD_END is used for the 2X and common clock front side bus signaling groups. GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END must be generated on the baseboard (See Table 2-18 for GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END specifications). Termination resistors (RTT) for AGTL+ signals are provided on the processor silicon and are terminated to VTT. The on-die termination resistors are always enabled on the processor to control reflections on the transmission line. Intel chipsets also provide on-die termination, thus eliminating the need to terminate the bus on the baseboard for most AGTL+ signals. Some FSB signals do not include on-die termination (RTT) and must be terminated on the baseboard. See Table 2-8 for details regarding these signals. The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the FSB, including trace lengths, is highly recommended when designing a system. Contact your Intel Field Representative to obtain the processor signal integrity models, which includes buffer and package models. 2.2 Power and Ground Lands For clean on-chip processor core power distribution, the processor has 223 VCC (power) and 267 VSS (ground) inputs. All VCC lands must be connected to the processor power plane, while all VSS lands must be connected to the system ground plane. The processor VCC lands must be supplied with the voltage determined by the processor Voltage IDentification (VID) signals. See Table 2-3 for VID definitions. Twenty two lands are specified as VTT, which provide termination for the FSB and provides power to the I/O buffers. The platform must implement a separate supply for these lands which meets the VTT specifications outlined in Table 2-12. Datasheet 13 Electrical Specifications 2.3 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors, supply voltage during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2-12. Failure to do so can result in timing violations or reduced lifetime of the component. 2.3.1 VCC Decoupling Vcc regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR), and the baseboard designer must assure a low interconnect resistance from the regulator (EVRD or VRM pins) to the LGA771 socket. Bulk decoupling must be provided on the baseboard to handle large voltage swings. The power delivery solution must insure the voltage and current specifications are met (as defined in Table 2-12). 2.3.2 VTT Decoupling Bulk decoupling must be provided on the baseboard. Decoupling solutions must be sized to meet the expected load. To insure optimal performance, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution consists of a combination of low ESR bulk capacitors and high frequency ceramic capacitors. 2.3.3 Front Side Bus AGTL+ Decoupling The processor integrates signal termination on the die, as well as a portion of the required high frequency decoupling capacitance on the processor package. However, additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the FSB. Bulk decoupling must also be provided by the baseboard for proper AGTL+ bus operation. 14 Datasheet Electrical Specifications 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous processor generations, the processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is set during manufacturing. The default setting is for the maximum speed of the processor. It is possible to override this setting using software (see the Intel® 64 and IA-32 Architectures Software Developer’s Manual). This permits operation at lower frequencies than the processor’s tested frequency. The processor core frequency is configured during reset by using values stored internally during manufacturing. The stored value sets the highest bus fraction at which the particular processor can operate. If lower speeds are desired, the appropriate ratio can be configured via the CLOCK_FLEX_MAX MSR. For details of operation at core frequencies lower than the maximum rated processor speed, refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual. Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread spectrum clocking. Processor DC specifications for the BCLK[1:0] inputs are provided in Table 2-19. These specifications must be met while also meeting signal integrity requirements as outlined in Table 2-19. The processor uses differential clocks. Table 2-1 contains processor core frequency to FSB multipliers and their corresponding core frequencies. Table 2-1. Core Frequency to FSB Multiplier Configuration Core Frequency to FSB Multiplier 1/6 1/7 1/7.5 1/8 1/8.5 1/9 1/9.5 1/10 1/10.5 1/11 1/11.5 1/12 1/12.5 1/13 Core Frequency with 400.000 MHz Bus Clock 2.40 GHz 2.80 GHz 3 GHz 3.20 GHz 3.40 GHz 3.60 GHz 3.80 GHz 4 GHz 4.20 GHz 4.40 GHz 4.60 GHz 4.80 GHz 5 GHz 5.20 GHz Notes 1, 2, 3 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 NOTES: 1. Listed frequencies are not necessarily committed production frequencies. 2. For valid processor core frequencies, see the Intel® Core™2 Extreme processor QX9775 Specification Update 3. The lowest bus ratio supported by the processor is 1/6. Datasheet 15 Electrical Specifications 2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0]) Upon power up, the FSB frequency is set to the maximum supported by the individual processor. BSEL[2:0] are CMOS outputs which must be pulled up to VTT, and are used to select the FSB frequency. Refer to Table 2-14 for DC specifications. Table 2-2 defines the possible combinations of the signals and the frequency associated with each combination. The frequency is determined by the processor(s), chipset, and clock synthesizer. All FSB agents must operate at the same core and FSB frequency. Table 2-2. BSEL[2:0] Frequency Table BSEL2 0 0 0 0 1 1 1 1 BSEL1 0 0 1 1 0 0 1 1 BSEL0 0 1 0 1 0 1 0 1 Bus Clock Frequency Reserved Reserved Reserved Reserved Reserved Reserved 400 MHz Reserved 2.4.2 PLL Power Supply An on-die PLL filter solution is implemented on the processor. The VCCPLL input is used for this configuration in Intel® Core™2 Extreme processor QX9775 -based platforms. Refer to Table 2-12 for DC specifications. 16 Datasheet Electrical Specifications 2.5 Voltage Identification (VID) The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor Vcc pins. VID signals are open drain outputs, which must be pulled up to VTT. Refer to Table 2-15 for the DC specifications for these signals. A voltage range is provided in Table 2-12 and changes with frequency. The specifications have been set such that one voltage regulator can operate with all supported frequencies. Individual processor VID values may be calibrated during manufacturing such that two devices at the same core frequency may have different default VID settings. This is reflected by the VID range values provided in Table 2-3. The processor uses six voltage identification signals, VID[6:1], to support automatic selection of power supply voltages. Table 2-3 specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself. See the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details. Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines defines VID[7:0], VID7 and VID0 are not used on the processor; VID7 is always hard wired low at the voltage regulator. The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (VCC). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Table 2-12 includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 2-13 and Table 2-2. The VRM or EVRD used must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 2-12 and Table 2-13. Refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details. Power source characteristics must be assured to be stable whenever the supply to the voltage regulator is stable. Datasheet 17 Electrical Specifications Table 2-3. 7A 78 76 74 72 70 6E 6C 6A 68 66 64 62 60 5E 5C 5A 58 56 54 52 50 4E 4C 4A 48 46 44 42 40 3E NOTES: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Voltage Identification Definition HEX VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 3C 3A 38 36 34 32 30 2E 2C 2A 28 26 24 22 20 1E 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000 OFF1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 1.2125 1.2250 HEX VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 1. 2. 3. When the “111111” VID pattern is observed, the voltage regulator output should be disabled. The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see Section 5.2.4), Extended HALT state transitions (see Section 6.2.2), or Enhanced Intel SpeedStep® Technology transitions (see Section 6.3). The Extended HALT state must be enabled for the processor to remain within its specifications. Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is deasserted or a specific VID off code is received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 ms and latch off until power is cycled. Refer to Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines. 18 Datasheet Electrical Specifications Table 2-4. Loadline Selection Truth Table for LL_ID[1:0] LL_ID1 0 0 1 1 LL_ID0 0 1 0 1 Reserved Intel® Core™2 Extreme processor QX9775 Reserved Reserved Description NOTE: The LL_ID[1:0] signals are used to select the correct loadline slope for the processor. Table 2-5. Market Segment Selection Truth Table for MS_ID[1:0] MS_ID1 0 0 1 1 MS_ID0 0 1 0 1 Reserved Reserved Reserved Intel® Core™2 Extreme processor QX9775 Description NOTE: The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying. 2.6 Reserved, Unused, and Test Signals All Reserved signals must remain unconnected. Connection of these signals to VCC, VTT, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all Reserved signals. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected; however, this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (RTT). For details see Table 2-18. TAP, CMOS Asynchronous inputs, and CMOS Asynchronous outputs do not include ondie termination. Inputs and utilized outputs must be terminated on the baseboard. Unused outputs may be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. The TESTHI signals must be tied to the processor VTT using a matched resistor, where a matched resistor has a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω is required. The TESTHI signals must use individual pull-up resistors as detailed below. A matched resistor must be used for each signal: • TESTHI10 – cannot be grouped with other TESTHI signals • TESTHI11 – cannot be grouped with other TESTHI signals • TESTHI12 - cannot be grouped with other TESTHI signals Datasheet 19 Electrical Specifications 2.7 Front Side Bus Signal Groups The FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF_DATA and GTLREF_ADD as reference levels. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. AGTL+ asynchronous outputs can become active anytime and include an active PMOS pull-up transistor to assist during the first clock of a low-to-high voltage transition. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 2-6 identifies which signals are common clock, source synchronous and asynchronous. Table 2-6. FSB Signal Groups (Sheet 1 of 2) Signal Group AGTL+ Common Clock Input AGTL+ Common Clock Output AGTL+ Common Clock I/O Type Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] Signals1 BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#; BPM4#, BPM[2:1]#, BPMb[2:1]# ADS#, AP[1:0]#, BINIT#2, BNR#2, BPM5#, BPM3#, BPM0#, BPMb3#, BPMb0#, BR[1:0]#, DBSY#, DP[3:0]#, DRDY#, HIT#2, HITM#2, LOCK#, MCERR#2 Signals REQ[4:0]#, A[16:3]#, A[37:36]# AGTL+ Source Synchronous I/O Synchronous to assoc. strobe A[35:17]# D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# AGTL+ Strobes I/O Open Drain Output CMOS Asynchronous Input CMOS Asynchronous Output FSB Clock Synchronous to BCLK[1:0] Asynchronous Asynchronous Asynchronous Clock Associated Strobe ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3# ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# FERR#/PBE#, IERR#, PROCHOT#, THERMTRIP#, TDO A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, STPCLK# BSEL[2:0], VID[6:1] BCLK[1:0] 20 Datasheet Electrical Specifications Table 2-6. FSB Signal Groups (Sheet 2 of 2) Signal Group TAP Input TAP Output Type Synchronous to TCK Synchronous to TCK Signals1 TCK, TDI, TMS, TRST# TDO COMP[3:0], GTLREF_ADD_MID, GTLREF_ADD_END, GTLREF_DATA_MID, GTLREF_DATA_END, LL_ID[1:0], MS_ID[1:0], PECI, RESERVED, SKTOCC#, TESTIN1, TESTIN2, TESTHI[12:10], VCC, VCC_DIE_SENSE, VCC_DIE_SENSE2, VCCPLL, VID_SELECT, VSS_DIE_SENSE, VSS_DIE_SENSE2, VSS, VTT, VTT_OUT, VTT_SEL Power/Other Power/Other NOTES: 1. Refer to Section 4.2 for signal descriptions. 2. These signals may be driven simultaneously by multiple agents (Wired-OR). Table 2-7 outlines the signals which include on-die termination (RTT). Table 2-8 outlines non AGTL+ signals including open drain signals. Table 2-9 provides signal reference voltages. Table 2-7. AGTL+ Signal Description Table AGTL+ signals with RTT A[37:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY# AGTL+ signals with no RTT BPM[5:0]#, BPMb[3:0]#, RESET#, BR[1:0]# Table 2-8. Non AGTL+ Signal Description Table Signals with RTT Signals with no RTT A20M#, BCLK[1:0], BSEL[2:0], COMP[3:0], FERR#/ PBE#, GTLREF_ADD_MID, GTLREF_ADD_END, GTLREF_DATA_MID, GTLREF_DATA_END, IERR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, LL_ID[1:0], MS_ID[1:0], PECI, PWRGOOD, SKTOCC#, SMI#, STPCLK#, TCK, TDI, TDO, TESTHI[12:8], THERMTRIP#, TMS, TRDY#, TRST#, VCC_DIE_SENSE, VCC_DIE_SENSE2, VID[6:1], VID_SELECT, VSS_DIE_SENSE, VSS_DIE_SENSE2, VTT_SEL FORCEPR#1, PROCHOT#2 NOTES: 1. These signals have RTT in the package with a 80 Ω pullup to VTT. 2. These signals have RTT in the package with a 50 Ω pullup to VTT. Datasheet 21 Electrical Specifications Table 2-9. Signal Reference Voltages GTLREF A[37:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BPM[5:0]#, BPMb[3:0]#,BPRI#, BR[1:0]#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#, HITM#, LOCK#, MCERR#, RESET#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY# CMOS A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#, PWRGOOD, SMI#, STPCLK#, TCK, TDI, TMS, TRST# 2.8 CMOS Asynchronous and Open Drain Asynchronous Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#, and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state. See Section 2.13 for the DC specifications. See Chapter 5 for additional timing requirements for entering and leaving the low power states. 2.9 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the processor(s) be first in the TAP chain followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage. Similar considerations must be made for TCK, TDO, TMS, and TRST#. Two copies of each signal may be required with each driving a different voltage level. 2.10 Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains Digital Thermal Sensor (DTS) sprinkled both inside and outside the cores in a die. These sensors are implemented as analog-to-digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature. PECI provides an interface to relay the highest DTS temperature within a die to external devices for thermal/fan speed control. More detailed information may be found in the Platform Environment Control Interface (PECI) Specification. 2.10.1 DC Characteristics The PECI interface operates at a nominal voltage set by VTT. The set of DC electrical specifications shown in Table 2-10 is used with devices normally operating from a VTT interface supply. VTT nominal levels will vary between processor families. All PECI devices will operate at the VTT level determined by the processor installed in the system. For specific nominal VTT levels, refer to Table 2-3. 22 Datasheet Electrical Specifications Table 2-10. PECI DC Electrical Limits Symbol Vin Vhysteresis Vn Vp Isource Isink Definition and Conditions Input Voltage Range Hysteresis Negative-edge threshold voltage Positive-edge threshold voltage High level output source (VOH = 0.75 * VTT) Low level output sink (VOL = 0.25 * VTT) High impedance state leakage to VTT (Vleak = VOL) High impedance leakage to GND (Vleak = VOH) Bus capacitance per node Signal noise immunity above 300 MHz N/A N/A 0.1 * VTT 10 10 N/A µA pF Vp-p 2 3 Min -0.150 0.1 * VTT 0.275 * VTT 0.550 * VTT -6.0 0.5 Max VTT N/A 0.500 * VTT 0.725 * VTT N/A 1.0 Units V V V V mA mA Notes1 Ileak+ N/A 50 µA 2 IleakCbus Vnoise NOTE: 1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. 2. The leakage specification applies to powered devices on the PECI bus. 3. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional nodes. 2.10.2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-1 as a guide for input buffer design. Figure 2-1. Input Device Hysteresis VTT Maximum VP Minimum VP Minimum Hysteresis Maximum VN Minimum VN PECI Ground PECI Low Range Valid Input Signal Range PECI High Range Datasheet 23 Electrical Specifications 2.11 Mixing Processors Intel supports and validates dual processor configurations only in which both processors operate with the same FSB frequency, core frequency, power segments, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel. Combining processors from different power segments is also not supported. Note: Processors within a system must operate at the same frequency per bits [12:8] of the CLOCK_FLEX_MAX MSR; however this does not apply to frequency transitions initiated due to thermal events, Extended HALT, Enhanced Intel SpeedStep Technology transitions, or assertion of the FORCEPR# signal (See Chapter 5). Not all operating systems can support dual processors with mixed frequencies. Mixing processors of different steppings but the same model (as per CPUID instruction) is supported. Details regarding the CPUID instruction are provided in the AP-485 Intel® Processor Identification and the CPUID Instruction application note. 2.12 Absolute Maximum and Minimum Ratings Table 2-11 specifies absolute maximum and minimum ratings only, which lie outside the functional limits of the processor. Only within specified operation limits, can functionality and long-term reliability be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded. Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields. 24 Datasheet Electrical Specifications Table 2-11. Processor Absolute Maximum Ratings Symbol VCC VTT TCASE TSTORAGE Parameter Core voltage with respect to VSS FSB termination voltage with respect to VSS Processor case temperature Storage temperature Min -0.30 -0.30 See Chapter 5 -40 Max 1.35 1.45 See Chapter 5 85 Unit V V °C °C 3, 4, 5 Notes1, 2 NOTES: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, please refer to the processor case temperature specifications. 4. This rating applies to the processor and does not include any tray or packaging. 5. Failure to adhere to this specification can affect the long-term reliability of the processor. 2.13 Processor DC Specifications The processor DC specifications in this section are defined at the processor die (pads) unless noted otherwise. See Chapter 4 for the processor land listings and signal definitions. Voltage and current specifications are detailed in Table 2-12. For platform planning refer to Table 2-13, which provides VCC static and transient tolerances. This same information is presented graphically in Figure 2-3. The FSB clock signal group is detailed in Table 2-19. BSEL[2:0] and VID[6:1] signals are specified in Table 2-14. The DC specifications for the AGTL+ signals are listed in Table 2-15. Legacy signals and Test Access Port (TAP) signals follow DC specifications similar to GTL+. The DC specifications for the PWRGOOD input and TAP signal group are listed in Table 2-15. Table 2-12 through Table 2-17 list the DC specifications for the processor and are valid only while meeting specifications for case temperature (TCASE as specified in Chapter 5, “Thermal Specifications”), clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter. Datasheet 25 Electrical Specifications Table 2-12. Voltage and Current Specifications Symbol VID VCC Vcc_boot VVID_STEP VVID_SHIFT VTT VCCPLL ICC Processor Number: QX9775 Parameter VID range VCC for processor core 3.2 GHz Min 0.850 Typ — Max 1.3500 Unit V V V mV mV V V A 150 — — 150 8 — ICC for VTT supply after VCC stable Processor Number: ICC_TDC ICC_VTT_OUT ICC_GTLREF ICC_VCCPLL ITCC QX9775 Thermal Design Current (TDC): 3.2 GHz — — — — 130 580 mA 15 — 7 A 13,17,18 A 14 A 9 7,12 11 4,5,8,17, 18 2, 3, 4, 8, 18 2 Notes 1, 10 See Table 2-13 and Figure 2-3 — — — 1.045 1.455 — 1.10 — — 1.10 1.500 — — ± 12.5 450 1.155 1.605 Default VCC Voltage for initial power up VID step size during a transition Total allowable DC load line shift from VID steps FSB termination voltage (DC + AC specification) PLL supply voltage (DC + AC specification) Processor Number: QX9775 Processor Number: ICC processor core with multiple VID” 3.2 GHz ICC_RESET core with multiple VID: 3.2 GHz ICC_RESET QX9775 ITT 16,17 ICC for VTT supply before VCC stable DC current that may be drawn from VTT_OUT per land ICC for GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END ICC for PLL supply ICC during active thermal control circuit (TCC) — — — — — — 200 260 150 µA mA A 6 11 17 NOTES: 1. Unless otherwise noted, all specifications in this table are based on final silicon characterization data. 2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.5 for more information. 3. The voltage specification requirements are measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 4. The processor must not be subjected to any static VCC level that exceeds the VCC_MAX associated with any particular current. Failure to adhere to this specification can shorten processor lifetime. 5. ICC_MAX specification is based on maximum VCC loadline. Refer to Figure 2-3 for details. The processor is capable of drawing ICC_MAX for up to 10 ms. Refer to Figure 2-1 for further details on the average processor current draw over various time durations. 6. This specification represents the total current for. 7. VTT must be provided via a separate voltage source and must not be connected to VCC. This specification is measured at the land. 26 Datasheet Electrical Specifications 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. . Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE) shown in Figure 5-1. This specification refers to the total reduction of the load line due to VID transitions below the specified VID. Individual processor VID values may be calibrated during manufacturing such that two devices at the same frequency may have different VID settings. This specification applies to the VCCPLL land. Baseboard bandwidth is limited to 20 MHz. ICC_TDC is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion. The processor is capable of drawing ICC_TDC indefinitely. Refer to Figure 2-1 for further details on the average processor current draw over various time durations. This parameter is based on design characterization and is not tested. This is the maximum total current drawn from the VTT plane by only one processor with RTT enabled. This specification does not include the current coming from on-board termination (RTT), through the signal line. Refer to the Voltage Regulator Design Guidelines to determine the total ITT drawn by the system. This parameter is based on design characterization and is not tested. ICC_VTT_OUT is specified at 1.1 V. ICC_RESET is specified while PWRGOOD and RESET# are asserted. The processor is intended for dual processor workstations only. Figure 2-2. Processor Load Current versus Time 16 0 155 Sustained Current (A) 150 14 5 14 0 13 5 13 0 12 5 12 0 0 .0 1 0 .1 1 10 10 0 10 0 0 Tim e Duration (s ) NOTES: 1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization. Datasheet 27 Electrical Specifications Table 2-13. Processor VCC Static and Transient Tolerance ICC (A) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 VCC_Max (V) VID - 0.000 VID - 0.006 VID - 0.013 VID - 0.019 VID - 0.025 VID - 0.031 VID - 0.038 VID - 0.044 VID - 0.050 VID - 0.056 VID - 0.063 VID - 0.069 VID - 0.075 VID - 0.081 VID - 0.087 VID - 0.094 VID - 0.100 VID - 0.106 VID - 0.113 VID - 0.119 VID - 0.125 VID - 0.131 VID - 0.138 VID - 0.144 VID - 0.150 VID - 0.156 VID - 0.163 VID - 0.169 VID - 0.175 VID - 0.181 VID - 0.188 VCC_Typ (V) VID - 0.010 VID - 0.016 VID - 0.023 VID - 0.029 VID - 0.035 VID - 0.041 VID - 0.048 VID - 0.054 VID - 0.060 VID - 0.066 VID - 0.073 VID - 0.079 VID - 0.085 VID - 0.091 VID - 0.097 VID - 0.104 VID - 0.110 VID - 0.116 VID - 0.123 VID - 0.129 VID - 0.135 VID - 0.141 VID - 0.148 VID - 0.154 VID - 0.160 VID - 0.166 VID - 0.173 VID - 0.179 VID - 0.185 VID - 0.191 VID - 0.198 VCC_Min (V) VID - 0.020 VID - 0.026 VID - 0.033 VID - 0.039 VID - 0.045 VID - 0.051 VID - 0.058 VID - 0.064 VID - 0.070 VID - 0.076 VID - 0.083 VID - 0.089 VID - 0.095 VID - 0.101 VID - 0.108 VID - 0.114 VID - 0.120 VID - 0.126 VID - 0.133 VID - 0.139 VID - 0.145 VID - 0.151 VID - 0.158 VID - 0.164 VID - 0.170 VID - 0.176 VID - 0.183 VID - 0.189 VID - 0.195 VID - 0.201 VID - 0.208 Notes 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 NOTES: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. See Section 2.13.1 for VCC overshoot specifications. 2. This table is intended to aid in reading discrete points on Figure 2-3. 3. The loadlines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR implementation. 28 Datasheet Electrical Specifications Figure 2-3. Processor VCC Static and Transient Tolerance Load Lines Icc [A] 0 VID - 0.000 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 VID - 0.050 VCC Maximum VID - 0.100 Vcc [V] VID - 0.150 VCC Typical VCC Minimum VID - 0.200 VID - 0.250 Table 2-14. AGTL+ Signal Group DC Specifications Symbol VIL VIH VOH RON ILI Parameter Input Low Voltage Input High Voltage Output High Voltage Buffer On Resistance Input Leakage Current Min -0.10 GTLREF+0.10 VTT-0.10 8.25 N/A Typ 0 VTT N/A 10.25 N/A Max GTLREF–0.10 VTT+0.10 VTT 12.25 ± 100 Units V V V Ω μA Notes1 2,4,6 3,6 4,6 5 7 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal quality specifications. 5. This is the pull down driver resistance. Measured at 0.31*VTT. RON (min) = 0.158*RTT. RON (typ) = 0.167*RTT. RON (max) = 0.175*RTT. 6. GTLREF should be generated from VTT with a 1% tolerance resistor divider. The VTT referred to in these specifications is the instantaneous VTT. 7. Specified when on-die RTT and RON are turned off. VIN between 0 and VTT. Datasheet 29 Electrical Specifications Table 2-15. CMOS Signal Input/Output Group and TAP Signal Group DC Specifications Symbol VIL VIH VOL VOH IOL IOH ILI Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current Output High Current Input Leakage Current Min -0.10 0.7 * VTT -0.10 0.9 * VTT 1.70 1.70 N/A Typ 0.00 VTT 0 VTT N/A N/A N/A Max 0.3 * VTT VTT + 0.1 0.1 * VTT VTT + 0.1 4.70 4.70 ± 100 Units V V V V mA mA μA Notes1 2,6 2 2 2 3 4 5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The VTT referred to in these specifications refers to instantaneous VTT. 3. Measured at 0.1*VTT. 4. Measured at 0.9*VTT. 5. For Vin between 0 V and VTT. Measured when the driver is tristated. Table 2-16. Open Drain Output Signal Group DC Specifications Symbol VOL VOH IOL ILO Parameter Output Low Voltage Output High Voltage Output Low Current Leakage Current Min 0 0.95 * VTT 16 N/A Typ N/A VTT N/A N/A Max 0.20 * VTT 1.05 * VTT 50 ± 200 Units V V mA μA 3 2 4 Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Measured at 0.2*VTT. 3. VOH is determined by value of the external pullup resistor to VTT. 4. For VIN between 0 V and VOH. 2.13.1 VCC Overshoot Specification The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot above VID). These specifications apply to the processor die voltage as measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Table 2-17. VCC Overshoot Specifications Symbol VOS_MAX TOS_MAX Parameter Magnitude of VCC overshoot above VID Time duration of VCC overshoot above VID Min — — Max 50 25 Units mV µs Figure 2-4 2-4 Notes 30 Datasheet Electrical Specifications Figure 2-4. VCC Overshoot Example Waveform Example Overshoot Waveform VID + 0.050 VOS Voltage [V] VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is the measured overshoot voltage. 2. TOS is the measured time duration above VID. 2.13.2 Die Voltage Validation Core voltage (VCC) overshoot events at the processor must meet the specifications in Table 2-17 when measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. Datasheet 31 Electrical Specifications 2.14 AGTL+ FSB Specifications Routing topologies are dependent on the processors supported and the chipset used in the design. In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 2-8 for details on which signals do not include on-die termination. Refer to Table 2-18 for RTT values. Valid high and low levels are determined by the input buffers via comparing with a reference voltage called GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END. GTLREF_DATA_MID and GTLREF_DATA_END is the reference voltage for the FSB 4X data signals, GTLREF_ADD_MID, and GTLREF_ADD_END is the reference voltage for the FSB 2X address signals and common clock signals. Table 2-18 lists the GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END specifications. The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard using high precision voltage divider circuits. Table 2-18. AGTL+ Bus Voltage Definitions Symbol GTLREF_DATA_MID, GTLREF_DATA_END GTLREF_ADD_MID, GTLREF_ADD_END RTT COMP Parameter Data Bus Reference Voltage Address Bus Reference Voltage Termination Resistance (pull up) COMP Resistance Min 0.98 * 0.667 * VTT 0.98 * 0.667 * VTT 45 49.4 Typ 0.667 * VTT 0.667 * VTT 50 49.9 Max 1.02*0.667 * VTT 1.02*0.667 * VTT 55 50.4 Units V V Ω Ω Notes1 2, 3 2, 3 4 5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values across the range of VTT. 3. GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END is generated from VTT on the baseboard by a voltage divider of 1% resistors. The minimum and maximum specifications account for this resistor tolerance. The VTT referred to in these specifications is the instantaneous VTT. 4. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.31*VTT. RTT is connected to VTT on die. 5. COMP resistance must be provided on the system board with 1% resistors. 32 Datasheet Electrical Specifications Table 2-19. FSB Differential BCLK Specifications Symbol VL VH VCROSS(abs) VCROSS(rel) Δ VCROSS VOS VUS VRBM VTR ILI ERRefclk-diffRrise ERRefclk-diff-Fall Parameter Input Low Voltage Input High Voltage Absolute Crossing Point Relative Crossing Point Range of Crossing Points Overshoot Undershoot Ringback Margin Threshold Region Input Leakage Current Differential Rising and falling edge rates Min -0.150 0.660 0.250 0.250 + 0.5 * (VHavg – 0.700) N/A N/A -0.300 0.200 VCROSS - 0.100 N/A Typ 0.0 0.710 0.350 N/A N/A N/A N/A N/A N/A N/A Max 0.150 0.850 0.550 0.550 + 0.5 * (VHavg – 0.700) 0.140 1.150 N/A N/A VCROSS + 0.100 ± 100 Unit V V V V V V V V V μA V/ns 2-7 Figure 2-5 2-5 2-5, 2-6 2-5, 2-6 2-5, 2-6 2-5 2-5 2-5 2-5 4 5 6 7 10 2,9 3,8,9,11 Notes1 0.6 4 12 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to the falling edge of BCLK1. 3. VHavg is the statistical average of the VH measured by the oscilloscope. 4. Overshoot is defined as the absolute value of the maximum voltage. 5. Undershoot is defined as the absolute value of the minimum voltage. 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 9. VHavg can be measured directly using “Vtop” on Agilent and “High” on Tektronix oscilloscopes. 10. For VIN between 0 V and VH. 11. ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 3. 12. Measured from -200 mV to +200 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 2-7. Datasheet 33 Electrical Specifications Figure 2-5. Differential Clock Waveform Overshoot BCLK1 VH Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot Tp Tp = T1: BCLK[1:0] period Figure 2-6. Differential Clock Crosspoint Specification 650 600 Crossing Point (mV) 550 500 450 400 350 300 250 200 550 mV 550 + 0.5 (VHavg - 700) 250 + 0.5 (VHavg - 700) 250 mV 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 2-7. Differential Rising and Falling Edge Rates §§ 34 Datasheet Mechanical Specifications 3 Mechanical Specifications The processor is packaged in a Flip Chip Land Grid Array (FC-LGA) package that interfaces to the baseboard via a LGA771 socket. The package consists of a processor core mounted on a pinless substrate with 771 lands. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink. Figure 3-1 shows a sketch of the processor package components and how they are assembled together. Refer to the LGA771 Socket Design Guidelines for complete details on the LGA771 socket. The package components shown in Figure 3-1 include the following: • Integrated Heat Spreader (IHS) • Thermal Interface Material (TIM) • Processor Core (die) • Package Substrate • Landside capacitors • Package Lands Figure 3-1. Processor Package Assembly Sketch TIM IHS Substrate Package Lands Core (die) Capacitors LGA771 Socket System Board NOTE: This drawing is not to scale and is for reference only. 3.1 Package Mechanical Drawings The package mechanical drawings are shown in Figure 3-2 through Figure 3-4. The drawings include dimensions necessary to design a thermal solution for the processor including: • Package reference and tolerance dimensions (total height, length, width, and so forth) • IHS parallelism and tilt • Land dimensions • Top-side and back-side component keepout dimensions • Reference datums Note: All drawing dimensions are in mm [in.]. Datasheet 35 Mechanical Specifications Figure 3-2. Processor Package Drawing (Sheet 1 of 3) NOTE: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines (See Section 1.2). 36 Datasheet Mechanical Specifications Figure 3-3. Processor Package Drawing (Sheet 2 of 3) Datasheet 37 Mechanical Specifications Figure 3-4. Processor Package Drawing (Sheet 3 of 3) 38 Datasheet Mechanical Specifications 3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. Decoupling capacitors are typically mounted to either the topside or landside of the package substrate. See Figure 3-4 for keepout zones. 3.3 Package Loading Specifications Table 3-1 provides dynamic and static load specifications for the processor package. These mechanical load limits should not be exceeded during heatsink assembly, mechanical stress testing or standard drop and shipping conditions. The heatsink attach solutions must not include continuous stress onto the processor with the exception of a uniform load to maintain the heatsink-to-processor thermal interface. Also, any mechanical system or component testing should not exceed these limits. The processor package substrate should not be used as a mechanical reference or loadbearing surface for thermal or mechanical solutions. Table 3-1. Package Loading Specifications Parameter Board Thickness 1.57 mm 0.062” Min 80 18 111 25 133 30 Max 311 70 311 70 311 70 311 N (max static compressive load) + 222 N dynamic loading 70 lbf (max static compressive load) + 50 lbf dynamic loading 750 Unit N lbf N lbf N lbf N 1,3,4,5,6 lbf 1,2,3,8 Notes Static Compressive Load 2.16 mm 0.085” 2.54 mm 0.100” Dynamic Compressive Load NA NA Transient Bend Limits 1.57 mm 0.062” NA me 1,3,7 NOTES: 1. These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface. 2. This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface. 3. These specifications are based on limited testing for design characterization. Loading limits are for the LGA771 socket. 4. Dynamic compressive load applies to all board thickness. 5. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement. 6. Test condition used a heatsink mass of 1 lbm with 50 g acceleration measured at heatsink mass. The dynamic portion of this specification in the product application can have flexibility in specific values, but the ultimate product of mass times acceleration should not exceed this dynamic load. 7. Transient bend is defined as the transient board deflection during manufacturing such as board assembly and system integration. It is a relatively slow bending event compared to shock and vibration tests. 8. Refer to the for information on heatsink clip load metrology. Datasheet 39 Mechanical Specifications 3.4 Package Handling Guidelines Table 3-2 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Table 3-2. Package Handling Guidelines Parameter Shear Tensile Torque Maximum Recommended 311 70 111 25 3.95 35 Units N lbf N lbf N-m LBF-in Notes 1,4,5 2,4,5 3,4,5 NOTES: 1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface. 2. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface. 3. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface. 4. These guidelines are based on limited testing for design characterization and incidental applications (one time only). 5. Handling guidelines are for the package only and do not include the limits of the processor socket. 3.5 Package Insertion Specifications The processor can be inserted and removed 15 times from an LGA771 socket, which meets the criteria outlined in the LGA771 Socket Design Guidelines. 3.6 Processor Mass Specifications The typical mass of the processor is 21.5 grams [0.76D oz.]. This includes all components which make up the entire processor product. 3.7 Processor Materials The processor is assembled from several components. The basic material properties are described in Table 3-3. Table 3-3. Processor Materials Component Integrated Heat Spreader (IHS) Substrate Substrate Lands Material Nickel over copper Fiber-reinforced resin Gold over nickel 40 Datasheet Mechanical Specifications 3.8 Processor Markings Figure 3-5 shows the topside markings on the processor. This diagram aids in the identification of the processor. Figure 3-5. Processor Top-side Markings (Example) INTEL(M) © ’06 QX9775 INTEL® CORE™ 2 EXTREME SXXX XXXXX 3.20GHZ/12M/1600 FPO ATPO S/N Datasheet 41 Mechanical Specifications 3.9 Processor Land Coordinates Figure 3-6 and Figure 3-7 show the top and bottom view of the processor land coordinates, respectively. The coordinates are referred to throughout the document to identify processor lands. Figure 3-6. Processor Land Coordinates, Top View VCC / VSS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 65 43 21 AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A Socket 771 Quadrants Top View Address / Common Clock / Async 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 65 43 21 VTT / Clocks Data 42 Datasheet Mechanical Specifications Figure 3-7. Processor Land Coordinates, Bottom View VCC / VSS 1 23 4 56 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A Address / Common Clock / Async Socket 771 Quadrants Bottom View 1 23 4 56 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Data § VTT / Clocks Datasheet 43 Mechanical Specifications 44 Datasheet Land Listing and Signal Description 4 4.1 Land Listing and Signal Description Land Listing Table 4-1 is a listing of all processor lands ordered alphabetically by Land name. Table 4-2 is a listing of all processor lands ordered by land number. Datasheet 45 Land Listing and Signal Description Table 4-1. Land Name A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A20M# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# A36# A37# ADS# ADSTB0# ADSTB1# AP0# AP1# BCLK0 BCLK1 BINIT# BNR# BPM0# Land Listing by Land Name (Sheet 1 of 17) Land No. M5 P6 L5 L4 M4 R4 T5 U6 T4 U5 U4 V5 V4 W5 AB6 W6 Y6 Y4 K3 AA4 AD6 AA5 AB5 AC5 AB4 AF5 AF4 AG6 AG4 AG5 AH4 AH5 AJ5 AJ6 N4 P5 D2 R6 AD5 U2 U3 F28 G28 AD3 C2 AJ2 Signal Buffer Type Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync CMOS ASync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Common Clk Source Sync Source Sync Common Clk Common Clk Clk Clk Common Clk Common Clk Common Clk Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Table 4-1. Land Name BPM1# BPM2# BPM3# BPM4# BPM5# BPMb0# BPMb1# BPMb2# BPMb3# BPRI# BR0# BR1# BSEL0 BSEL1 BSEL2 COMP0 COMP1 COMP2 COMP3 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# Land Listing by Land Name (Sheet 2 of 17) Land No. AJ1 AD2 AG2 AF2 AG3 G1 C9 G4 G3 G8 F3 H5 G29 H30 G30 A13 T1 G2 R1 B4 C5 A4 C6 A5 B6 B7 A7 A10 A11 B10 C11 D8 B12 C12 D11 G9 F8 F9 E9 D7 E10 D10 F11 F12 D13 E13 Signal Buffer Type Common Clk Common Clk Common Clk Common Clk Common Clk Common Clk Common Clk Common Clk Common Clk Common Clk Common Clk Common Clk CMOS ASync CMOS ASync CMOS Async Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Direction Output Output Input/Output Output Input/Output Input/Output Output Output Input/Output Input Input/Output Input Output Output Output Input Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output 46 Datasheet Land Listing and Signal Description Table 4-1. Land Name D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBI0# DBI1# DBI2# DBI3# DBR# DBSY# DEFER# DP0# DP1# Land Listing by Land Name (Sheet 3 of 17) Land No. G13 F14 G14 F15 G15 G16 E15 E16 G18 G17 F17 F18 E18 E19 F20 E21 F21 G21 E22 D22 G22 D20 D17 A14 C15 C14 B15 C18 B16 A17 B18 C21 B21 B19 A19 A22 B22 A8 G11 D19 C20 AC2 B2 G7 J16 H15 Signal Buffer Type Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Power/Other Common Clk Common Clk Common Clk Common Clk Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input/Output Input Input/Output Input/Output Table 4-1. Land Name DP2# DP3# DRDY# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# FORCEPR# Land Listing by Land Name (Sheet 4 of 17) Land No. H16 J17 C1 C8 G12 G20 A16 B9 E12 G19 C17 AK6 Signal Buffer Type Common Clk Common Clk Common Clk Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Open Drain CMOS ASync Power/Other Power/Other Power/Other Power/Other Common Clk Common Clk Open Drain CMOS ASync CMOS ASync CMOS ASync CMOS ASync Power/Other Power/Other Common Clk Common Clk Power/Other Power/Other Power/Other Open Drain CMOS ASync Source Sync Source Sync Source Sync Source Sync Source Sync Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input Input Input Input Input Input/Output Input/Output Output Input Input Input Input Output Output Input/Output Input/Output Output Output Input/Output Output Input Input/Output Input/Output Input/Output Input/Output Input/Output FERR#/PBE# R3 GTLREF_ADD G10 _END GTLREF_ADD F2 _MID GTLREF_DAT A_END GTLREF_DAT A_MID HIT# HITM# IERR# IGNNE# INIT# LINT0 LINT1 LL_ID0 LL_ID1 LOCK# MCERR# MS_ID0 MS_ID1 PECI PROCHOT# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESERVED RESERVED RESERVED RESERVED RESERVED H1 H2 D4 E4 AB2 N2 P3 K1 L1 V2 AA2 C3 AB3 W1 V1 G5 AL2 N1 K4 J5 M6 K6 J6 AM6 A20 A23 A24 AC4 Datasheet 47 Land Listing and Signal Description Table 4-1. Land Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESET# RS0# RS1# Land Listing by Land Name (Sheet 5 of 17) Land No. AE4 AE6 AH2 AH7 AJ3 AJ7 AK3 AM2 AN5 AN6 B13 B23 C23 D1 D14 D16 E1 E23 E24 E5 E6 E7 E29 F23 F29 F6 G6 J2 J3 N5 T2 Y1 Y3 AL1 AK1 G27 G26 G24 F24 F26 F25 G25 W3 G23 B3 F5 Common Clk Common Clk Common Clk Input Input Input Signal Buffer Type Direction Table 4-1. Land Name RS2# RSP# SKTOCC# SMI# STPCLK# TCK TDI TDO TESTHI10 TESTHI11 TESTHI12 TESTIN1 TESTIN2 TMS TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land Listing by Land Name (Sheet 6 of 17) Land No. A3 H4 AE8 P2 M3 AE1 AD1 AF1 P1 L2 AE3 W2 U1 AC1 E3 AG1 AA8 AB8 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC8 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD8 AE11 AE12 AE14 AE15 AE18 AE19 AE21 AE22 AE23 Signal Buffer Type Common Clk Common Clk Power/Other CMOS ASync CMOS ASync TAP TAP TAP Power/Other Power/Other Power/Other Power/Other Power/Other Open Drain TAP Common Clk TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Input Input Output Input Input Input Input Output Input Input Input Input Input Output Input Input Input THERMTRIP# M2 48 Datasheet Land Listing and Signal Description Table 4-1. Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land Listing by Land Name (Sheet 7 of 17) Land No. AE9 AF11 AF12 AF14 AF15 AF18 AF19 AF21 AF22 AF8 AF9 AG11 AG12 AG14 AG15 AG18 AG19 AG21 AG22 AG25 AG26 AG27 AG28 AG29 AG30 AG8 AG9 AH11 AH12 AH14 AH15 AH18 AH19 AH21 AH22 AH25 AH26 AH27 AH28 AH29 AH30 AH8 AH9 AJ11 AJ12 AJ14 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 4-1. Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land Listing by Land Name (Sheet 8 of 17) Land No. AJ15 AJ18 AJ19 AJ21 AJ22 AJ25 AJ26 AJ8 AJ9 AK11 AK12 AK14 AK15 AK18 AK19 AK21 AK22 AK25 AK26 AK8 AK9 AL11 AL12 AL14 AL15 AL18 AL19 AL21 AL22 AL25 AL26 AL29 AL30 AL9 AM11 AM12 AM14 AM15 AM18 AM19 AM21 AM22 AM25 AM26 AM29 AM30 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Datasheet 49 Land Listing and Signal Description Table 4-1. Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land Listing by Land Name (Sheet 9 of 17) Land No. AM8 AM9 AN11 AN12 AN14 AN15 AN18 AN19 AN21 AN22 AN25 AN26 AN8 AN9 J10 J11 J12 J13 J14 J15 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J8 J9 K23 K24 K25 K26 K27 K28 K29 K30 K8 L8 M23 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 4-1. Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land Listing by Land Name (Sheet 10 of 17) Land No. M24 M25 M26 M27 M28 M29 M30 M8 N23 N24 N25 N26 N27 N28 N29 N30 N8 P8 R8 T23 T24 T25 T26 T27 T28 T29 T30 T8 U23 U24 U25 U26 U27 U28 U29 U30 U8 V8 W23 W24 W25 W26 W27 W28 W29 W30 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction 50 Datasheet Land Listing and Signal Description Table 4-1. Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_DIE_SE NSE VCC_DIE_SE NSE2 VCCPLL VID_SELECT VID1 VID2 VID3 VID4 VID5 VID6 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Listing by Land Name (Sheet 11 of 17) Land No. W8 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y8 AN3 AL8 D23 AN7 AL5 AM3 AL6 AK4 AL4 AM5 A12 A15 A18 A2 A21 A6 A9 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA3 AA30 AA6 AA7 AB1 AB23 AB24 AB25 AB26 AB27 AB28 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Async CMOS Async CMOS Async CMOS Async CMOS Async CMOS Async Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Input Output Output Output Output Output Output Output Direction Table 4-1. Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Listing by Land Name (Sheet 12 of 17) Land No. AB29 AB30 AB7 AC3 AC6 AC7 AD4 AD7 AE10 AE13 AE16 AE17 AE2 AE20 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE5 AE7 AF7 AF10 AF13 AF16 AF17 AF20 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF3 AF30 AF6 AG10 AG13 AG16 AG17 AG20 AG23 AG24 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Datasheet 51 Land Listing and Signal Description Table 4-1. Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Listing by Land Name (Sheet 13 of 17) Land No. AG7 AH1 AH10 AH13 AH16 AH17 AH20 AH23 AH24 AH3 AH6 AJ10 AJ13 AJ16 AJ17 AJ20 AJ23 AJ24 AJ27 AJ28 AJ29 AJ30 AJ4 AK10 AK13 AK16 AK17 AK2 AK20 AK23 AK24 AK27 AK28 AK29 AK30 AK5 AK7 AL10 AL13 AL16 AL17 AL20 AL23 AL24 AL27 AL28 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 4-1. Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Listing by Land Name (Sheet 14 of 17) Land No. AL3 AM1 AM10 AM13 AM16 AM17 AM20 AM23 AM24 AM27 AM28 AM4 AM7 AN1 AN10 AN13 AN16 AN17 AN2 AN20 AN23 AN24 B1 B11 B14 B17 B20 B24 B5 B8 C10 C13 C16 C19 C22 C24 C4 C7 D12 D15 D18 D21 D24 D3 D5 D6 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction 52 Datasheet Land Listing and Signal Description Table 4-1. Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Listing by Land Name (Sheet 15 of 17) Land No. D9 E11 E14 E17 E2 E20 E25 E26 E27 E28 E8 F1 F10 F13 F16 F19 F22 F4 F7 H10 H11 H12 H13 H14 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H3 H6 H7 H8 H9 J4 J7 K2 K5 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 4-1. Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land Listing by Land Name (Sheet 16 of 17) Land No. K7 L23 L24 L25 L26 L27 L28 L29 L3 L30 L6 L7 M1 M7 N3 N6 N7 P23 P24 P25 P26 P27 P28 P29 P30 P4 P7 R2 R23 R24 R25 R26 R27 R28 R29 R30 R5 R7 T3 T6 T7 U7 V23 V24 V25 V26 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Datasheet 53 Land Listing and Signal Description Table 4-1. Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_DIE_SE NSE VSS_DIE_SE NSE2 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT_OUT VTT_OUT VTT_SEL Land Listing by Land Name (Sheet 17 of 17) Land No. V27 V28 V29 V3 V30 V6 V7 W4 W7 Y2 Y5 Y7 AN4 AL7 A25 A26 B25 B26 B27 B28 B29 B30 C25 C26 C27 C28 C29 C30 D25 D26 D27 D28 D29 D30 E30 F30 AA1 J1 F27 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output Direction 54 Datasheet Land Listing and Signal Description Table 4-2. Pin No. A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 Land Listing by Land Number (Sheet 1 of 17) Signal Buffer Type Power/Other Common Clk Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Source Sync Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Direction Table 4-2. Pin No. B22 B23 B24 B25 B26 B27 B28 B29 B30 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 Land Listing by Land Number (Sheet 2 of 17) Signal Buffer Type Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clk Common Clk Common Clk Power/Other Source Sync Source Sync Power/Other Source Sync Common Clk Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clk Power/Other Common Clk Power/Other Power/Other Source Sync Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Direction Input/Output Pin Name VSS RS2# D02# D04# VSS D07# DBI0# VSS D08# D09# VSS COMP0 D50# VSS DSTBN3# D56# VSS D61# RESERVED VSS D62# RESERVED RESERVED VTT VTT VSS DBSY# RS0# D00# VSS D05# D06# VSS DSTBP0# D10# VSS D13# RESERVED VSS D53# D55# VSS D57# D60# VSS D59# Pin Name D63# RESERVED VSS VTT VTT VTT VTT VTT VTT DRDY# BNR# LOCK# VSS D01# D03# VSS DSTBN0# BPMb1 VSS D11# D14# VSS D52# D51# VSS DSTBP3# D54# VSS DBI3# D58# VSS RESERVED VSS VTT VTT VTT VTT VTT VTT RESERVED ADS# VSS HIT# VSS VSS D20# Power/Other Power/Other Power/Other Common Clk Common Clk Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 D1 D2 D3 D4 D5 D6 D7 Datasheet 55 Land Listing and Signal Description Table 4-2. Pin No. D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 Land Listing by Land Number (Sheet 3 of 17) Signal Buffer Type Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clk Common Clk Input Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Direction Input/Output Table 4-2. Pin No. E24 E25 E26 E27 E28 E29 E30 F1 F2 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 Land Listing by Land Number (Sheet 4 of 17) Signal Buffer Type Direction Pin Name D12# VSS D22# D15# VSS D25# RESERVED VSS RESERVED D49# VSS DBI2# D48# VSS D46# VCCPLL VSS VTT VTT VTT VTT VTT VTT RESERVED VSS TRDY# HITM# RESERVED RESERVED RESERVED VSS D19# D21# VSS DSTBP1# D26# VSS D33# D34# VSS D39# D40# VSS D42# D45# RESERVED Pin Name RESERVED VSS VSS VSS VSS RESERVED VTT VSS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input GTLREF_ADD_ Power/Other MID VSS RS1# RESERVED VSS D17# D18# VSS D23# D24# VSS D28# D30# VSS D37# D38# VSS D41# D43# VSS RESERVED RESERVED RESERVED RESERVED VTT_SEL BCLK0 RESERVED BR0# VTT BPMb0# COMP2 BPMb3# BPMb2# PECI RESERVED DEFER# BPRI# Common Clk Common Clk Common Clk Power/Other Common Clk Power/Other Common Clk Common Clk Power/Other Power/Other Clk Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Power/Other Common Clk Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output F25 F26 F27 F28 F29 F3 F30 G1 G2 G3 G4 G5 G6 G7 G8 Output Input Input/Output Input/Output Input Input/Output Output Input/Output Input Input 56 Datasheet Land Listing and Signal Description Table 4-2. Pin No. G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 Land Listing by Land Number (Sheet 5 of 17) Signal Buffer Type Source Sync Direction Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Table 4-2. Pin No. H23 H24 H25 H26 H27 H28 H29 H30 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 Land Listing by Land Number (Sheet 6 of 17) Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Async Power/Other Output Output Direction Pin Name D16# Pin Name VSS VSS VSS VSS VSS VSS VSS BSEL1 VTT_OUT RESERVED RESERVED VSS REQ1# REQ4# VSS VCC VCC VCC VCC VCC VCC VCC VCC DP0# DP3# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC LINT0 VSS A20M# REQ0# VSS REQ3# VSS VCC GTLREF_ADD_ Power/Other END DBI1# DSTBN1# D27# D29# D31# D32# D36# D35# DSTBP2# DSTBN2# D44# D47# RESET# RESERVED RESERVED RESERVED RESERVED BCLK1 BSEL0 BSEL2 GTLREF_DATA _END GTLREF_DATA _MID VSS RSP# BR1# VSS VSS VSS VSS VSS VSS VSS VSS VSS DP1# DP2# VSS VSS VSS VSS VSS VSS Clk CMOS Async CMOS Async Power/Other Power/Other Power/Other Common Clk Common Clk Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clk Common Clk Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Common Clk Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clk Common Clk Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Async Power/Other CMOS Async Source Sync Power/Other Source Sync Power/Other Power/Other Input/Output Input Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Output Output Input Input Input Input Input/Output Input/Output K1 K2 K3 K4 K5 K6 K7 K8 Datasheet 57 Land Listing and Signal Description Table 4-2. Pin No. K23 K24 K25 K26 K27 K28 K29 K30 L1 L2 L3 L4 L5 L6 L7 L8 L23 L24 L25 L26 L27 L28 L29 L30 M1 M2 M3 M4 M5 M6 M7 M8 M23 M24 M25 M26 M27 M28 M29 M30 N1 N2 N3 N4 N5 N6 Land Listing by Land Number (Sheet 7 of 17) Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Async Power/Other Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Open Drain CMOS Async Source Sync Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Async Power/Other Source Sync Power/Other Input/Output Input Input Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Direction Table 4-2. Pin No. N7 N8 N23 N24 N25 N26 N27 N28 N29 N30 P1 P2 P3 P4 P5 P6 P7 P8 P23 P24 P25 P26 P27 P28 P29 P30 R1 R2 R3 R4 R5 R6 R7 R8 R23 R24 R25 R26 R27 R28 R29 R30 T1 T2 T3 T4 Land Listing by Land Number (Sheet 8 of 17) Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Async CMOS Async Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Open Drain Source Sync Power/Other Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Input/Output Input Input/Output Output Input/Output Input Input/Output Input/Output Input Input Input Direction Pin Name VCC VCC VCC VCC VCC VCC VCC VCC LINT1 TESTHI11 VSS A06# A05# VSS VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS THERMTRIP# STPCLK# A07# A03# REQ2# VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC PWRGOOD IGNNE# VSS A36# RESERVED VSS Pin Name VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC TESTHI10 SMI# INIT# VSS A37# A04# VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS COMP3 VSS FERR#/PBE# A08# VSS ADSTB0# VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS COMP1 RESERVED VSS A11# 58 Datasheet Land Listing and Signal Description Table 4-2. Pin No. T5 T6 T7 T8 T23 T24 T25 T26 T27 T28 T29 T30 U1 U2 U3 U4 U5 U6 U7 U8 U23 U24 U25 U26 U27 U28 U29 U30 V1 V2 V3 V4 V5 V6 V7 V8 V23 V24 V25 V26 V27 V28 V29 V30 W1 W2 Land Listing by Land Number (Sheet 9 of 17) Signal Buffer Type Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clk Common Clk Source Sync Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Input Input/Output Input/Output Output Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Direction Input/Output Table 4-2. Pin No. W3 W4 W5 W6 W7 W8 W23 W24 W25 W26 W27 W28 W29 W30 Y1 Y2 Y3 Y23 Y4 Y5 Y6 Y7 Y8 Y24 Y25 Y26 Y27 Y28 Y29 Y30 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 Land Listing by Land Number (Sheet 10 of Signal Buffer Type Direction Pin Name A09# VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC TESTIN2 AP0# AP1# A13# A12# A10# VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC MS_ID1 LL_ID0 VSS A15# A14# VSS VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS MS_ID0 TESTIN1 Pin Name RESERVED VSS A16# A18# VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC RESERVED VSS RESERVED VCC A20# VSS A19# VSS VCC VCC VCC VCC VCC VCC VCC VCC VTT_OUT LL_ID1 VSS A21# A23# VSS VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Power/Other Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input/Output Input/Output Output Output Input/Output Input/Output Input/Output Input/Output Datasheet 59 Land Listing and Signal Description Table 4-2. Pin No. AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD23 AD24 AD25 AD26 AD27 AD28 Land Listing by Land Number (Sheet 11 of Signal Buffer Type Power/Other Open Drain Common Clk Source Sync Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Power/Other Power/Other Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Common Clk Common Clk Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input/Output Input/Output Input Output Input/Output Input/Output Input Output Output Input/Output Input/Output Input/Output Input/Output Direction Table 4-2. Pin No. AD29 AD30 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 Land Listing by Land Number (Sheet 12 of Signal Buffer Type Power/Other Power/Other TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Common Clk Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input/Output Input/Output Output Output Output Input Input Direction Pin Name VSS IERR# MCERR# A26# A24# A17# VSS VCC VSS VSS VSS VSS VSS VSS VSS VSS TMS DBR# VSS RESERVED A25# VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC TDI BPM2# BINIT# VSS ADSTB1# A22# VSS VCC VCC VCC VCC VCC VCC VCC Pin Name VCC VCC TCK VSS TESTHI12 RESERVED VSS RESERVED VSS SKTOCC# VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS TDO BPM4# VSS A28# A27# VSS VSS VCC VCC VSS VCC VCC VSS VCC 60 Datasheet Land Listing and Signal Description Table 4-2. Pin No. AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 Land Listing by Land Number (Sheet 13 of Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Common Clk Common Clk Source Sync Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input/Output Input/Output Input/Output Input/Output Input/Output Direction Table 4-2. Pin No. AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 Land Listing by Land Number (Sheet 14 of Signal Buffer Type Power/Other Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clk Common Clk Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input/Output Input/Output Output Input/Output Input/Output Input/Output Direction Pin Name VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS TRST# BPM3# BPM5# A30# A31# A29# VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VCC VCC VCC VCC Pin Name VSS RESERVED VSS A32# A33# VSS RESERVED VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VCC VCC VCC VCC BPM1# BPM0# RESERVED VSS A34# A35# RESERVED VCC VCC VSS VCC VCC VSS VCC VCC VSS Datasheet 61 Land Listing and Signal Description Table 4-2. Pin No. AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AL1 AL2 Land Listing by Land Number (Sheet 15 of Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Async Power/Other CMOS Async Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Open Drain Output Input Output Direction Table 4-2. Pin No. AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 Land Listing by Land Number (Sheet 16 of Signal Buffer Type Power/Other CMOS Async CMOS Async CMOS Async Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Async Power/Other CMOS Async Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output Direction Pin Name VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VSS VSS RESERVED VSS RESERVED VID4 VSS FORCEPR# VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VSS VSS RESERVED PROCHOT# Pin Name VSS VID5 VID1 VID3 VSS_DIE_ SENSE2 VCC_DIE_ SENSE2 VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS RESERVED VID2 VSS VID6 RESERVED VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS 62 Datasheet Land Listing and Signal Description Table 4-2. Pin No. AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 Land Listing by Land Number (Sheet 17 of Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Direction Pin Name VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC_DIE_ SENSE VSS_DIE_ SENSE RESERVED RESERVED VID_SELECT VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC VCC Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Datasheet 63 Land Listing and Signal Description 4.2 Table 4-1. Signal Definitions Signal Definitions (Sheet 1 of 11) Name Type Description A[37:3]# (Address) define a 238-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins of all agents on the FSB. A[37:3]# are protected by parity signals AP[1:0]#. A[37:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the processors sample a subset of the A[37:3]# lands to determine their power-on configuration. See Section 6.1. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1 MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[37:3]# lands. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. This signal must be connected to the appropriate pins on all processor FSB agents. Address strobes are used to latch A[37:3]# and REQ[4:0]# on their rising and falling edge. Strobes are associated with signals as shown below. ADSTB[1:0]# I/O Signals REQ[4:0]#, A[16:3]#, A[37:36]# A[35:17]# Associated Strobes ADSTB0# ADSTB1# 3 Notes A[37:3]# I/O 3 A20M# I 2 ADS# I/O 3 64 Datasheet Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 2 of 11) Name Type Description AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[37:3]#, and the transaction type on the REQ[4:0]# signals. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]# must be connected to the appropriate pins of all processor FSB agents. The following table defines the coverage model of these signals. Request Signals A[37:24]# A[23:3]# REQ[4:0]# Subphase 1 AP0# AP1# AP1# Subphase 2 AP1# AP0# AP0# Notes AP[1:0]# I/O 3 BCLK[1:0] I The differential bus clock pair BCLK[1:0] (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS. BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration (see Section 6.1) and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state machines. The bus agents do not reset their I/O Queue (IOQ) and transaction tracking state machines upon observation of BINIT# assertion. Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for the FSB and attempt completion of their bus queue and IOQ entries. If BINIT# observation is disabled during power-on configuration, a priority agent may handle an assertion of BINIT# as appropriate to the error handling architecture of the system. BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. 3 BINIT# I/O 3 BNR# I/O Since multiple agents might need to request a bus stall at the same time, BNR# is a wired-OR signal which must connect the appropriate pins of all processor FSB agents. In order to avoid wired-OR glitches associated with simultaneous edge transitions driven by multiple drivers, BNR# is activated on specific clock edges and sampled on specific clock edges. 3 Datasheet 65 Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 3 of 11) Name Type Description BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins of all FSB agents. BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processors. BPM[5:4]# must be bussed to all bus agents. BPMb3# BPMb[2:1]# BPMb0# I/O O I/O BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPMb[3:0]# should connect the appropriate pins of all FSB agents. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB. It must connect the appropriate pins of all processor FSB agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. The BR[1:0]# signals are sampled on the active-toinactive transition of RESET#. The signal which the agent samples asserted determines its agent ID. BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. These signals do not have on-die termination and must be terminated. The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency. Table 2-2 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processors, chipset, and clock synthesizer. All FSB agents must operate at the same frequency. COMP[3:0] must be terminated to VSS on the baseboard using precision resistors. These inputs configure the AGTL+ drivers of the processor. 2 Notes BPM5# BPM4# BPM3# BPM[2:1]# BPM0# I/O O I/O O I/O BPRI# I 3 BR[1:0]# I/O 3 BSEL[2:0] O COMP[3:0] I 66 Datasheet Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 4 of 11) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to strobes and DBI#. D[63:0]# I/O 3 DBI# 0 1 2 3 Notes Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]# DSTBN#/ DSTBP# 0 1 2 3 Furthermore, the DBI# signals determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high. DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within, within a 16-bit group, would have been asserted electronically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group. DBI[3:0]# I/O DBI[3:0] Assignment to Data Bus Bus Signal DBI0# DBI1# DBI2# DBI3# Data Bus Signals D[15:0]# D[31:16]# D[47:32]# D[63:48]# 3 DBR# O DBR# is used only in systems where no debug port connector is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port connector is implemented in the system, DBR# is a no-connect on the processor package. DBR# is not a processor signal. Datasheet 67 Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 5 of 11) Name Type Description DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all processor FSB agents. DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or I/O agent. This signal must connect the appropriate pins of all processor FSB agents. DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They are driven by the agent responsible for driving D[63:0]#, and must connect the appropriate pins of all processor FSB agents. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all processor FSB agents. Data strobe used to latch in D[63:0]#. Signals DSTBN[3:0]# I/O D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# Associated Strobes DSTBN0# DSTBN1# DSTBN2# DSTBN3# 3 Notes DBSY# I/O 3 DEFER# I 3 DP[3:0]# I/O 3 DRDY# I/O 3 Data strobe used to latch in D[63:0]#. Signals DSTBP[3:0]# I/O D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# Associated Strobes DSTBP0# DSTBP1# DSTBP2# DSTBP3# 3 68 Datasheet Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 6 of 11) Name Type Description FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel® 387 coprocessor, and is included for compatibility with systems using MS-DOS*type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. For additional information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to Vol. 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual and the Intel Processor Identification and the CPUID Instruction application note. The FORCEPR# (force power reduction) input can be used by the platform to cause the processor to activate the Thermal Control Circuit (TCC). GTLREF_ADD determines the signal reference level for AGTL+ address and common clock input lands. GTLREF_ADD is used by the AGTL+ receivers to determine if a signal is a logical 0 or a logical 1. Refer to Table 2-18 for additional details. GTLREF_DATA determines the signal reference level for AGTL+ data input lands. GTLREF_DATA is used by the AGTL+ receivers to determine if a signal is a logical 0 or a logical 1. Refer to Table 2-18 for additional details. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#. This signal does not have on-die termination. Notes FERR#/PBE# O 2 FORCEPR# I GTLREF_ADD_MID GTLREF_ADD_END I GTLREF_DATA_MID GTLREF_DATA_END I HIT# HITM# I/O I/O 3 IERR# O 2 Datasheet 69 Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 7 of 11) Name Type Description IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floatingpoint instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O write bus transaction. INIT# (Initialization), when asserted, resets integer registers inside all processors without affecting their internal caches or floating-point registers. Each processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins of all processor FSB agents. LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all FSB agents. When the APIC functionality is disabled, the LINT0/INTR signal becomes INTR, a maskable interrupt request signal, and LINT1/ NMI becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium® processor. Both signals are asynchronous. These signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LL_ID[1:0] O The LL_ID[1:0] signals are used to select the correct loadline slope for the processor. These signals are not connected to the processor die. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. LOCK# I/O When the priority agent asserts BPRI# to arbitrate for ownership of the processor FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock. 3 Notes IGNNE# I 2 INIT# I 2 LINT[1:0] I 2 70 Datasheet Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 8 of 11) Name Type Description MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor FSB agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: MCERR# I/O • • • • Enabled or disabled. Asserted, if configured, for internal errors along with IERR#. Asserted, if configured, by the request initiator of a bus transaction after it observes an error. Asserted by any bus agent when it observes an error in a bus transaction. Notes For more details regarding machine check architecture, refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3. These signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying. These signals are not connected to the processor die. Both the bits 0 and 1 are logic 1 and are no connects on the package. PROCHOT# (Processor Hot) will go active when the processor’s temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the Thermal Control Circuit (TCC) has been activated, if enabled. The TCC will remain active until shortly after the processor deasserts PROCHOT#. See Section 5.2.3 for more details. PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications. “Clean” implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. REQ[4:0]# (Request Command) must connect the appropriate pins of all processor FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking of these signals. MS_ID[1:0] O PROCHOT# O PWRGOOD I 2 REQ[4:0]# I/O 3 Datasheet 71 Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 9 of 11) Name Type Description Asserting the RESET# signal resets all processors to known states and invalidates their internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least 1 ms after VCC and BCLK have reached their proper specifications. On observing active RESET#, all FSB agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted. A number of bus signals are sampled at the active-toinactive transition of RESET# for power-on configuration. These configuration options are described in the Section 6.1. This signal does not have on-die termination and must be terminated on the system board. RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor FSB agents. RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all processor FSB agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent ensuring correct parity. SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate that the processor is present. There is no connection to the processor silicon for this signal. SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tri-state its outputs. See Section 6.1. STPCLK# (Stop Clock), when asserted, causes processors to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. Notes RESET# I 3 RS[2:0]# I 3 RSP# I 3 SKTOCC# O SMI# I 2 STPCLK# I 2 72 Datasheet Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 10 of 11) Name TCK Type I Description TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TESTHI[12:10] must be connected to a VTT power source through a resistor for proper processor operation. Refer to Section 2.6 for TESTHI grouping restrictions. TESTIN1 must be connected to a VTT power source through a resistor as well as to the TESTIN2 land of the same socket for proper processor operation. TESTIN2 must be connected to a VTT power source through a resistor as well as to the TESTIN1 land of the same socket for proper processor operation. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor its core voltage (VCC) must be removed following the assertion of THERMTRIP#. Intel also recommends the removal of VTT when THERMTRIP# is asserted. Driving of the THERMTRIP# signals is enabled within 10 μs of the assertion of PWRGOOD and is disabled on deassertion of PWRGOOD. Once activated, THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 μs of the assertion of PWRGOOD. TMS I TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all FSB agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. The processor implements an on-die PLL filter solution. The VCCPLL input is used as a PLL supply voltage. Notes TDI I TDO O TESTHI[12:10] I TESTIN1 TESTIN2 I I THERMTRIP# O 1 TRDY# I TRST# VCCPLL I I Datasheet 73 Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 11 of 11) Name Type Description VCC_DIE_SENSE and VCC_DIE_SENSE2 provides an isolated, low impedance connection to the processor core power and ground. This signal should be connected to the voltage regulator feedback signal, which insures the output voltage (that is, processor voltage) remains within specification. VID[6:1] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC). These are CMOS signals that are driven by the processor and must be pulled up through a resistor. Conversely, the voltage regulator output must be disabled prior to the voltage supply for these pins becomes invalid. The VID pins are needed to support processor voltage specification variations. See Table 2-4 for definitions of these pins. The VR must supply the voltage that is requested by these pins, or disable itself. VID_SELECT is an output from the processor which selects the appropriate VID table for the Voltage Regulator. This signal is not connected to the processor die. This signal is a no-connect on the processor package. VSS_DIE_SENSE and VSS_DIE_SENSE2 provides an isolated, low impedance connection to the processor core power and ground. This signal should be connected to the voltage regulator feedback signal, which insures the output voltage (that is, processor voltage) remains within specification. The FSB termination voltage input pins. Refer to Table 2-12 for further details. The VTT_OUT signals are included in order to provide a local VTT for some signals that require termination to VTT on the motherboard. The VTT_SEL signal is used to select the correct VTT voltage level for the processor. VTT_SEL is connected to VSS on the processor package. Notes VCC_DIE_SENSE VCC_DIE_SENSE2 O VID[6:1] O VID_SELECT O VSS_DIE_SENSE VSS_DIE_SENSE2 O VTT P VTT_OUT O VTT_SEL O NOTES: 1. For this processor land, the maximum number of symmetric agents is one. Maximum number of priority agents is zero. 2. For this processor land, the maximum number of symmetric agents is two. Maximum number of priority agents is zero. 3. For this processor land, the maximum number of symmetric agents is two. Maximum number of priority agents is one. § 74 Datasheet Thermal Specifications 5 5.1 Thermal Specifications Package Thermal Specifications The processor requires a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting. This section provides data necessary for developing a complete thermal solution. For more information on designing a component level thermal solution, refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). 5.1.1 Thermal Specifications To allow the optimal operation and long-term reliability of Intel processor-based systems, the processor must remain within the minimum and maximum case temperature (TCASE) specifications as defined by the applicable thermal profile Table 5-1 and Figure 5-1. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). The processor implements a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and to assure processor reliability. Selection of the appropriate fan speed is based on the relative temperature data reported by the processor’s Platform Environment Control Interface (PECI) bus as described in Section 5.3. If the value reported via PECI is less than TCONTROL, then the case temperature is permitted to exceed the Thermal Profile. If the value reported via PECI is greater than or equal to TCONTROL, then the processor case temperature must remain at or below the temperature as specified by the thermal. The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 5.2, Processor Thermal Features). Systems that implement fan speed control must be designed to use this data. Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications. The processor supports a single Thermal Profile (see Figure 5-1, Table 5-1). With this Thermal Profile, it is expected that the Thermal Control Circuit (TCC) would only be activated for very brief periods of time when running the most power-intensive applications. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for details on system thermal solution design, thermal profiles and environmental considerations. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 5-1 for the processor, instead of the maximum processor power consumption. The Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period. For more Datasheet 75 Thermal Specifications details on this feature, refer to Section 5.2. Thermal Monitor 1 and Thermal Monitor 2 feature must be enabled for the processor to remain within its specifications. Table 5-1. Processor Thermal Specifications Core Frequency Maximum Power (W) 155 Thermal Design Power (W) 150 Minimum TCASE (°C) 5 Maximum TCASE (°C) See Figure 5-1; Table 5-2 Notes QX9775 1,2,3,4,5 NOTES: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Refer to the loadline specifications in Section 2.13. 2. Thermal Design Power (TDP) should be used for the processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on silicon characterization. 4. Power specifications are defined at all VIDs found in Table 2-3. The processor may be shipped under multiple VIDs for each frequency. 5. The processor s intended for dual processor workstations only. Figure 5-1. Processor Thermal Profile Thermal Profile (2U) 75 70 65 60 Tcase [C] 55 50 45 40 35 0 10 20 30 40 50 60 70 80 Power [W] 90 100 110 120 130 140 150 Thermal Profile Y = 0.187*x + 35 NOTES: 1. Refer to Table 5-2 for discrete points that constitute the thermal profile. 2. Implementation of the processor Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for system and environmental implementation details. 76 Datasheet Thermal Specifications Table 5-2. Processor Thermal Profile Table Power (W) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 TCASE_MAX (°C) 35.0 35.9 36.9 37.8 38.7 39.7 40.6 41.5 42.5 43.0 44.4 45.3 46.2 47.2 48.1 49.0 Power (W) 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 TCASE_MAX (°C) 50.0 50.9 51.8 52.8 53.7 54.6 55.6 56.5 57.4 58.4 59.3 60.2 61.2 62.1 63.0 5.1.2 Thermal Metrology The minimum and maximum case temperatures (TCASE) are specified in Table 5-2 is measured at the geometric top center of the processor integrated heat spreader (IHS). Figure 5-2 illustrates the location where TCASE temperature measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). Datasheet 77 Thermal Specifications Figure 5-2. Case Temperature (TCASE) Measurement Location NOTE: Figure is not to scale and is for reference only. 5.2 5.2.1 Processor Thermal Features Intel® Thermal Monitor Features The processor provides two thermal monitor features — Thermal Monitor (TM1) and Enhanced Thermal Monitor (TM2). The Thermal Monitor and Enhanced Thermal Monitor must both be enabled in BIOS for the processor to be operating within specifications. When both are enabled, TM2 will be activated first and TM1 will be added if TM2 is not effective. 5.2.1.1 Thermal Monitor (TM1) The Thermal Monitor (TM1) feature helps control the processor temperature by activating the Thermal Control Circuit (TCC) when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption as needed by modulating (starting and stopping) the internal processor core clocks. The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. 78 Datasheet Thermal Specifications When the TM1 is enabled, and a high temperature situation exists (that is, TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30 – 50%). Cycle times are processor speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. With thermal solutions designed to the processor Thermal Profile, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). The duty cycle for the TCC, when activated by the TM1, is factory configured and cannot be modified. The TM1 does not require any additional hardware, software drivers, or interrupt handling routines. 5.2.1.2 Enhanced Thermal Monitor (TM2) The processor adds supports for an Enhanced Thermal Monitor capability known as Thermal Monitor 2 (TM2). This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor. TM2 requires support for dynamic VID transitions in the platform. When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the Thermal Control Circuit (TCC) will be activated for both processor cores. The TCC causes the processor to adjust its operating frequency (via the bus multiplier) and input voltage (via the VID signals). This combination of reduced frequency and VID results in a reduction to the processor power consumption. A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a specific operating frequency and voltage, which is identical for both processor cores. The first operating point represents the normal operating condition for the processor. Under this condition, the core-frequency-to-system-bus multiplier used by the processor is that contained in the CLOCK_FLEX_MAX MSR and the VID that is specified in Table 2-3. The second operating point consists of both a lower operating frequency and voltage. The lowest operating frequency is determined by the lowest supported bus ratio (1/6 for the processor. When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs rapidly, on the order of 5 µs. During the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency. Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support dynamic VID steps in order to support Thermal Monitor 2. During the voltage change, it will be necessary to transition through multiple VID codes to reach the target operating voltage. Each step will be one VID table entry (see Table 2-3). The processor continues to execute instructions during the voltage transition. Operation at the lower voltage reduces the power consumption of the processor. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and Datasheet 79 Thermal Specifications voltage transition back to the normal system operating point. Transition of the VID code will occur first, in order to insure proper operation once the processor reaches its normal operating frequency. Refer to Figure 5-3 for an illustration of this ordering. Figure 5-3. Thermal Monitor 2 Frequency and Voltage Ordering TTM2 Temperature fMAX fTM2 VNOM VTM2 Frequency Vcc Time T(hysterisis) The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor 1 or Thermal Monitor 2 is enabled. 5.2.2 On-Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “OnDemand” mode and is distinct from the Thermal Monitor 1 and Thermal Monitor 2 features. On-Demand mode is intended as a means to reduce system level power consumption. Systems using the processor must not rely on software usage of this mechanism to limit the processor temperature. If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a ‘1’, the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used in conjunction with the Thermal Monitor; however, if the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the OnDemand mode. 5.2.3 PROCHOT# Signal An external signal, PROCHOT# (processor hot) is asserted when the processor die temperature of any processor cores reaches its factory configured trip point. If Thermal Monitor is enabled (note that Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual for specific register and programming details. 80 Datasheet Thermal Specifications PROCHOT# is designed to assert at or a few degrees higher than maximum TCASE when dissipating TDP power, and cannot be interpreted as an indication of processor case temperature. This temperature delta accounts for processor package, lifetime and manufacturing variations and attempts to ensure the Thermal Control Circuit is not activated below maximum TCASE when dissipating TDP power. There is no defined or fixed correlation between the PROCHOT# trip temperature, or the case temperature. Thermal solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of TCASE, or PROCHOT#. 5.2.4 FORCEPR# Signal The FORCEPR# (force power reduction) input can be used by the platform to cause the processor to activate the TCC. If the Thermal Monitor is enabled, the TCC will be activated upon the assertion of the FORCEPR# signal. Assertion of the FORCEPR# signal will activate TCC for all processor cores. The TCC will remain active until the system deasserts FORCEPR#. FORCEPR# is an asynchronous input. FORCEPR# can be used to thermally protect other system components. To use the VR as an example, when FORCEPR# is asserted, the TCC circuit in the processor will activate, reducing the current consumption of the processor and the corresponding temperature of the VR. It should be noted that assertion of FORCEPR# does not automatically assert PROCHOT#. As mentioned previously, the PROCHOT# signal is asserted when a high temperature situation is detected. A minimum pulse width of 500 µs is recommended when FORCEPR# is asserted by the system. Sustained activation of the FORCEPR# signal may cause noticeable platform performance degradation. 5.2.5 THERMTRIP# Signal Regardless of whether or not Thermal Monitor 1 or Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Section 4.2). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Section 4.2. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. Intel also recommends the removal of VTT. 5.3 5.3.1 Platform Environment Control Interface (PECI) Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. Figure 5-4 shows an example of the PECI topology in a system with the Intel® Core™2 Extreme processor QX9775. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices. Also, data transfer speeds across the PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps). The PECI interface on the processor is disabled by default and must be enabled through BIOS. Datasheet 81 Thermal Specifications Figure 5-4. Processor PECI Topology P ro c e s s o r (S o c k e t 0 ) 0 x 3 0 0 x 3 0 D o m a in 0 G5 D o m a in 1 PEC I H ost C o n tro lle r 0 x 3 1 G5 0 x 3 1 P ro c e s s o r (S o c k e t 1 ) D o m a in 0 D o m a in 1 82 Datasheet Thermal Specifications 5.3.1.1 TCONTROL and TCC Activation on PECI-based Systems Fan speed control solutions based on PECI utilize a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset temperature format as PECI though it contains no sign bit. Thermal management devices should infer the TCONTROL value as negative. Thermal management algorithms should use the relative temperature value delivered over PECI in conjunction with the TCONTROL MSR value to control or optimize fan speeds. Figure 5-5 shows a conceptual fan control diagram using PECI temperatures. The relative temperature value reported over PECI represents the data below the onset of thermal control circuit (TCC) activation as needed by PROCHOT# assertions. As the temperature approaches TCC activation, the PECI value approaches zero. TCC activates at a PECI count of zero. Figure 5-5. Conceptual Fan Control Diagram of PECI-based Platforms TOT O C NR L S ttin eg Mx a P C =0 EI F nS e d a pe (P) RM P C =- 0 EI 1 M in T CA tiv tio C can T m e au e e pr t r P C =- 0 EI 2 T m ea r e p r tu e ( o in n e tod p t a tu l im le e ta n n t te d d e ic c a p m n tio ) 5.3.1.2 Processor Thermal Data Sample Rate and Filtering The Digital Thermal Sensor (DTS) provides an improved capability to monitor device hot spots, which inherently leads to more varying temperature readings over short time intervals. The DTS sample interval range can be modified, and a data filtering algorithm can be activated to help moderate this. The DTS sample interval range is 82 us (default) to 20 ms (max). This value can be set in BIOS. To reduce the sample rate requirements on PECI and improve thermal data stability vs. time the processor DTS also implements an averaging algorithm that filters the incoming data. This is an alpha-beta filter with coefficients of 0.5, and is expressed mathematically as: Current_filtered_temp = (Previous_filtered_temp / 2) + (new_sensor_temp / 2). This filtering algorithm is fixed and cannot be changed. It is on by default and can be turned off in BIOS. Host controllers should use the min/max sample times to determine the appropriate sample rate based on the controller's fan control algorithm and targeted response rate. The key items to take into account when settling on a fan control algorithm are the DTS sample rate, whether the temperature filter is enabled, how often the PECI host will poll the processor for temperature data, and the rate at which fan speed is changed. Depending on the designer’s specific requirements the DTS sample rate and alpha-beta filter may have no effect on the fan control algorithm. Datasheet 83 Thermal Specifications 5.3.2 5.3.2.1 PECI Specifications PECI Device Address The PECI device address for socket 0 is 30h and socket 1 is 31h. Note that each address also supports two domains (Domain0 and Domain1). For more information on PECI domains, please refer to the Platform Environment Control Interface (PECI) Specification. 5.3.2.2 PECI Command Support PECI command support is covered in detail in Platform Environment Control Interface Specification. Refer to this document for details on supported PECI command function and codes. 5.3.2.3 PECI Fault Handling Requirements PECI is largely a fault tolerant interface, including noise immunity and error checking improvements over other comparable industry standard interfaces. The PECI client is as reliable as the device that it is embedded in, and thus given operating conditions that fall under the specification, the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures. There are, however, certain scenarios where PECI is known to be unresponsive. Prior to a power on RESET# and during RESET# assertion, PECI is not assured to provide reliable thermal data. System designs should implement a default power-on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI. To protect platforms from potential operational or safety issues due to an abnormal condition on PECI, the Host controller should take action to protect the system from possible damage. It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive gettemp()s or for a one second time interval. The host controller may also implement an alert to software in the event of a critical or continuous fault condition. 5.3.2.4 PECI GetTemp0()and GetTemp1() Error Code Support The error codes supported for the processor GetTemp0() and GetTemp1() commands are listed in Table 5-3. Table 5-3. GetTemp0() GetTemp1()Error Codes Error Code 8000h 8002h General sensor error Sensor is operational, but has detected a temperature below its operational range (underflow). Description § 84 Datasheet Features 6 6.1 Features Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples its hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifics on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All external resets reconfigure the processor, for configuration purposes, the processor does not distinguish between a “warm” reset (PWRGOOD signal remains asserted) and a “power-on” reset. Table 6-1. Power-On Configuration Option Lands Configuration Option Output tri state Execute BIST (Built-In Self Test) Disable MCERR# observation Disable BINIT# observation Symmetric agent arbitration ID NOTES: 1. 2. Asserting this signal during RESET# will select the corresponding option. Address lands not identified in this table as configuration options should not be asserted during RESET#. Land Name SMI# A3# A9# A10# BR[1:0]# Notes 1,2 1,2 1,2 1,2 1,2 Disabling of any of the cores within the processor must be handled by configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the package. 6.2 Clock Control and Low Power States The processor supports the Extended HALT state (also referred to as C1E) in addition to the HALT state and Stop-Grant state to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 6-1 for a visual representation of the processor low power states. The Extended HALT state is a lower power state than the HALT state or Stop Grant state. The Extended HALT state must be enabled via the BIOS for the processor to remain within its specifications. For processors that are already running at the lowest bus to core frequency ratio for its nominal operating point, the processor will transition to the HALT state instead of the Extended HALT state. The Stop Grant state requires chipset and BIOS support on multiprocessor systems. In a multiprocessor system, all the STPCLK# signals are bussed together, thus all processors are affected in unison. When the STPCLK# signal is asserted, the processor enters the Stop Grant state, issuing a Stop Grant Special Bus Cycle (SBC) for each processor die. The chipset needs to account for a variable number of processors asserting the Stop Grant SBC on the bus before allowing the processor to be transitioned into one of the lower processor power states. Datasheet 85 Features Figure 6-1. Stop Clock State Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated Normal State Normal execution INIT#, BINIT#, INTR, NMI, SMI#, RESET#, FSB interrupts Extended HALT or HALT State BCLK running Snoops and interrupts allowed S As TPC se L rte K# d S De TPC - a LK ss # er te d STPCLK# Asserted STPCLK# De-asserted Snoop Event Occurs Snoop Event Serviced Extended HALT Snoop or HALT Snoop State BCLK running Service snoops to caches Stop Grant State BCLK running Snoops and interrupts allowed Snoop Event Occurs Snoop Event Serviced Stop Grant Snoop State BCLK running Service snoops to caches 6.2.1 Normal State This is the normal operating state for the processor. 6.2.2 HALT or Extended HALT State The Extended HALT state (C1E) is enabled via the BIOS. The Extended HALT state must be enabled for the processor to remain within its specifications. The Extended HALT state requires support for dynamic VID transitions in the platform. 6.2.2.1 HALT State HALT is a low power state entered when the processor have executed the HALT or MWAIT instruction. When one of the processor cores execute the HALT or MWAIT instruction, that processor core is halted; however, the other processor continues normal operation. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the front side bus. RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT state. See the Intel® 64 and IA-32 Architecture Software Developer's Manual. 86 Datasheet Features The system can generate a STPCLK# while the processor is in the HALT state. When the system deasserts STPCLK#, the processor will return execution to the HALT state. While in HALT state, the processor will process front side bus snoops and interrupts. 6.2.2.2 Extended HALT State Extended HALT state is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT state has been enabled via the BIOS. When one of the processor cores executes the HALT instruction, that processor core is halted; however, the other processor core continues normal operation. The Extended HALT state is a lower power state than the HALT state or Stop Grant state. The Extended HALT state must be enabled for the processor to remain within its specifications. The processor will automatically transition to a lower core frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor will first switch to the lower bus to core frequency ratio and then transition to the lower voltage (VID). While in the Extended HALT state, the processor will process bus snoops. Table 6-2. Extended HALT Maximum Power Symbol PEXTENDED_HALT Parameter Extended HALT State Power Min — Typ — Max 16 Unit W Notes 1,2 NOTE: 1. The specification is at Tcase = 40 °C and nominal Vcc. The VID setting represents the maximum expected VID when running in HALT state. 2. Processors running in the lowest bus ratio supported as shown in Table 2-1, will enter the HALT State when the processor has executed the HALT or MWAIT instruction since the processor is already operating in the lowest core frequency and voltage operating point. The processor exits the Extended HALT state when a break event occurs. When the processor exits the Extended HALT state, it will first transition the VID to the original value and then change the bus to core frequency ratio back to the original value. 6.2.3 Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered no later than 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle. By default, the processor will issue two Stop Grant Acknowledge special bus cycles, one for each die. Once the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop Grant state. All processor cores will enter the Stop-Grant state once the STPCLK# pin is asserted. Additionally, all processor cores must be in the Stop Grant state before the de-assertion of STPCLK#. Since the AGTL+ signal pins receive power from the front side bus, these pins should not be driven (allowing the level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the front side bus should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be serviced by software upon exit from the Stop Grant state. Datasheet 87 Features RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. A transition to the Grant Snoop state will occur when the processor detects a snoop on the front side bus (see Section 6.2.4.1). While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal state. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus. The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that it should return the processor to the Normal state. 6.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State The Extended HALT Snoop state is used in conjunction with the Extended HALT state. If the Extended HALT state is not enabled in the BIOS, the default Snoop state entered will be the HALT Snoop state. Refer to the sections below for details on HALT Snoop state, Stop Grant Snoop state, and Extended HALT Snoop state. 6.2.4.1 HALT Snoop State, Stop Grant Snoop State The processor will respond to snoop or interrupt transactions on the front side bus while in Stop-Grant state or in HALT state. During a snoop or interrupt transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the front side bus has been serviced (whether by the processor or another agent on the front side bus) or the interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor will return to the Stop-Grant state or HALT state, as appropriate. 6.2.4.2 Extended HALT Snoop State The Extended HALT Snoop state is the default Snoop state when the Extended HALT state is enabled via the BIOS. The processor will remain in the lower bus to core frequency ratio and VID operating point of the Extended HALT state. While in the Extended HALT Snoop state, snoops and interrupt transactions are handled the same way as in the HALT Snoop state. After the snoop is serviced or the interrupt is latched, the processor will return to the Extended HALT state. 88 Datasheet Features 6.3 Enhanced Intel SpeedStep® Technology The processor supports Enhanced Intel SpeedStep® Technology. This technology enables the processor to switch between multiple frequency and voltage points, which results in platform power savings. Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform. Switching between voltage/ frequency states is software controlled. For more configuration details also refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual. Enhanced Intel SpeedStep Technology creates processor performance states (P-states) or voltage/frequency operating points which are lower power capability states within the Normal state (see Figure 6-1 for the Stop Clock State Machine for supported Pstates). Enhanced Intel SpeedStep Technology enables real-time dynamic switching between frequency and voltage points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage. This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. The processor has hardware logic that coordinates the requested voltage (VID) between the processor cores. The highest voltage that is requested for either of the processor cores is selected for that processor package. Note that the front side bus is not altered; only the internal core frequency is changed. In order to run at reduced power consumption, the voltage is altered in step with the bus ratio. The following are key features of Enhanced Intel SpeedStep Technology: • Multiple voltage/frequency operating points provide optimal performance at reduced power consumption. • Voltage/frequency selection is software controlled by writing to the processor MSR’s (Model Specific Registers); thus, eliminating chipset dependency. — If the target frequency is higher than the current frequency, VCC is incremented in steps (+12.5 mV) by placing a new value on the VID signals and the processor shifts to the new frequency. Note that the top frequency for the processor can not be exceeded. — If the target frequency is lower than the current frequency, the processor shifts to the new frequency and VCC is then decremented in steps (-12.5 mV) by changing the target VID through the VID signals. § Datasheet 89 Features 90 Datasheet