CAT310

CAT310 10 Channel Automotive LED Display Driver Description The CAT310 is a 10−channel LED driver for automotive and other lighting applications. All LED output channels are driven from a low on−resistance open−drain High Voltage CMOS Nch−FETs and are fully compliant with “Load Dump” transients of up to 40 volts. The LED bias current of each channel can be set independently using an external series ballast resistor, making the device ideal for multi−color instrumentation displays. A high−speed serial interface (suitable with both 3.3 volt and 5 volt systems) feeding a 10 bit shift register is used to program the desired state (on/off) of each channel. The device offers a blanking control pin (BLANK) which can be used to disable all channels on demand. A serial output data pin (SOUT) is provided to daisy−chain devices in large cluster LED applications. During initial power up all channels are reset and cleared via an under−voltage lock out (UVLO) detector and for added protection all channels are disabled in the event of a battery over−voltage condition (19 volts or more). Features http://onsemi.com SOIC−20 W SUFFIX CASE 751BJ PIN CONNECTIONS SCLK XLAT SIN SOUT GND OUT4 OUT3 OUT2 OUT1 OUT0 1 NC BLANK VCC VBATT PGND OUT5 OUT6 OUT7 OUT8 OUT9 • • • • • • • • • • Automotive “Load Dump” Protection (40 V) 10 Independent LED Channels Up to 50 mA Output per Channel Overvoltage Detection at 19 V Serial Interface for Channel Programming Daisy Chain Output for Multi−driver Cascading LED Blanking Control Operating Temperature from −40°C to +125°C 20−pin SOIC Package This Device is Pb−Free, Halogen Free/BFR Free and RoHS Compliant Automotive Lighting White and Other Color High Brightness LEDs Multi−color High−brightness LED Cluster Displays General LED Lighting MARKING DIAGRAM CAT310W CAT310W = Specific Device Code Applications • • • • ORDERING INFORMATION Device CAT310W Package SOIC−20 (Pb−Free) Shipping 1,000/Tape & Reel © Semiconductor Components Industries, LLC, 2009 November, 2009 − Rev. 2 1 Publication Order Number: CAT310/D CAT310 VBATTERY 14 V (typical) RS1 RS2 OUT1 RS10 330 W OUT9 30 mA VBATT OUT0 VCC 5V 1 mF VCC BLANK CAT310 XLAT SIN SCLK GND PGND SOUT Figure 1. Typical Application Circuit Table 1. ABSOLUTE MAXIMUM RATINGS Parameter VCC voltage Input voltage range (SIN, SCLK, BLANK, XLAT) SOUT voltage range Peak OUT0 to OUT9 voltage VBATT input voltage DC output current on OUT0 to OUT9 Storage Temperature Range Operating Junction Temperature Range Lead Soldering Temperature (10 sec.) ESD Rating: Low Voltage Pins Human Body Model Machine Model ESD Rating: VBATT, OUT[0:9] pins Human Body Model Machine Model Rating 7 −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V 40 40 70 −55 to +160 −40 to +150 300 3000 300 V 1000 100 Unit V V V V V mA °C °C °C V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 2. RECOMMENDED OPERATING CONDITIONS Parameter VCC Voltage applied to OUT0 to OUT9 Output current on OUT0 to OUT9 Ambient Temperature Range Range 3.0 to 5.5 9 to 17 0 to 50 −40 to +125 Unit V V mA _C http://onsemi.com 2 CAT310 Electrical Operating Characteristics Table 3. DC CHARACTERISTICS (VCC = 5.0 V, −40°C ≤ TA ≤ 125°C, over recommended operating conditions unless specified otherwise.) Symbol ISTBY VOVP VUVLO RSW IO(n)LKG IXLAT IBLANK VIH VIL IIL VOH VOL Name Standby Quiescent Current VBATT Over Voltage Protection Trigger threshold VCC Under Voltage Lockout Trigger threshold Switch on resistance for OUT0 to OUT9 OUT0 to OUT9 Output Switch Leakage XLAT Internal Pull−down current BLANK Internal Pull−up current Logic high input voltage Logic low input voltage Logic Input leakage current (SCLK, SIN) SOUT logic high output voltage SOUT logic low output voltage VI = VCC or GND IOH = −1 mA IOL = 1 mA IO(n) = 30 mA V(OUT(n)) = 15 V XLAT = VCC XLAT = 0.3 V BLANK = 0 V BLANK = VCC − 0.3 V 4 1 4 1 0.3 VCC −5 VCC −0.3 V 0.3 0 5 mA V 2 Conditions Static input signal. All outputs turned off. 17 Min Typ 1 19 1.7 5 0.1 10 3 10 3 Max 10 21 2.5 12 10 30 6 30 6 0.7 VCC Units mA V V W mA mA mA V Table 4. SWITCHING CHARACTERISTICS (VCC = 5.0 V, −40°C ≤ TA ≤ 125°C, over recommended operating conditions unless specified otherwise.) Symbol SCLK fSCLK twh/wl SIN tsu th XLAT tw th tr tf tpd tpd tpd XLAT Pulse width Hold time SCLK to XLAT SOUT rise time (10% to 90%) SOUT fall time (90% to 10%) Propagation delay time Propagation delay time Propagation delay time CL = 15 pF CL = 15 pF Blank ↑ to OUT(n) Blank ↓ to OUT(n) SCLK to SOUT SIN to SCLK 20 20 20 15 25 25 25 ns ns ns ns ns ns ns Setup time SIN to SCLK Hold time SIN to SCLK 10 10 ns ns SCLK Clock Frequency SCLK Pulse width High or Low 30 10 MHz ns Name Conditions Min Typ Max Units 1. All logic inputs contain Schmitt trigger inputs. http://onsemi.com 3 CAT310 2.5 V UVLO + VCC – RESET SCLK SIN 10 BIT SHIFT REGISTER SOUT XLAT 10 BIT DATA LATCHES OUT0 BLANK VBATT + – 19 V GND PGND OR DISABLE 10 BIT DRIVER DRV9 SW−0 SW−9 OUT9 DRV0 Figure 2. Block Diagram http://onsemi.com 4 CAT310 PIN DESCRIPTIONS VCC is the supply input for the internal logic and is compatible with both 3.3 V and 5 V systems. The logic is held in a reset state until VCC exceeds 2.5 V. It is recommended that a small bypass ceramic capacitor (1 mF) be placed between VCC and GND pins on the device. SIN is the CMOS logic pin for delivering the serial input data stream into the internal 10−bit shift register. The most recent or last data value in the serial stream is used to configure the state of output channel “zero” (OUT0). During the initial power up sequence all contents of the shift register are reset and cleared to zero. SCLK is the CMOS logic pin used to clock the internal shift register. On each rising edge of clock, the serial data will advance through one stage of the shift register. XLAT is the CMOS logic input used to transfer data from the 10−bit shift register into the output channel latches. An internal pull−down current of 10 microampere is present on this pin. When XLAT is low, the state of each output channel remains unchanged. When XLAT is driven high, the contents of the shift register appear at their respective output channels. An external pull−up resistance of 10 kW or less is adequate for logic high. PGND, GND pins should be connected to the ground on the PCB. BLANK is the CMOS logic input (active high) used to temporarily disable all outputs. An internal pull−up current of 10 microampere is present on this pin. The BLANK pin must be driven to a logic low in order for channel outputs to resume normal operation. An external pull−down resistance of 10 kW or less is adequate for logic low. SOUT is the CMOS logic output used for daisy chain applications. The serial output data stream is fed from the last stage of the internal 10−bit shift register. On each rising edge of the clock, the SOUT value will be updated. The data value present on this pin is identical to the data value being used for configuring the state of output channel nine (OUT9). At initial power up, the SOUT data stream will contain all zeroes until the shift register has been fully loaded. VBATT input monitors the battery voltage. If an over−voltage, above 19 V typical, is detected, all outputs are disabled. Upon conclusion of the over−voltage condition, all outputs resume normal operation. The current drawn by the VBATT pin is less than 1 microampere during normal operation. OUT0−OUT9 are the ten LED outputs connected internally to the switch N−channel FETs. They sink currents up to 50 mA per channel and can withstand transients up to 40 V compatible with automotive “load dump”. The output on−resistance is 5 W, and the off−resistance is 5 MW. Table 5. PIN TABLE Pin Number 1 2 3 4 5 6−10 11−15 16 17 18 19 20 Pin Name SCLK XLAT SIN SOUT GND OUT4 − OUT0 OUT9 − OUT5 PGND VBATT VCC BLANK N.C. Description/Function Clock input for the data shift register. Control input for the data latch. Serial data input. Serial data output. Ground. Open drain outputs. Open drain outputs. Ground for LED driver outputs. Battery sense input. Power supply voltage for the logic Blank input. When BLANK is high, all the output drivers are turned off. No connect. http://onsemi.com 5 CAT310 TYPICAL CHARACTERISTICS (VCC = 5 V, VBATT = 14 V, TAMB = 25°C, unless otherwise specified.) VBATT 5V/div 18V BLANK 5V/div LED current 50mA/div LED current 50mA/ div OUT pin voltage 10V/div 1 msec / div 50 msec / div Figure 3. VBATT Overvoltage Detection Amplitude between 16 V and 26 V 14 12 XLAT CURRENT (mA) 10 8 6 4 2 0 0 1 2 3 4 5 125°C −40°C 25°C 85°C BLANK CURRENT (mA) 14 12 Figure 4. BLANK and Output Waveform −40°C 25°C 10 85°C 125°C 8 6 4 VCC = 5 V 2 0 0 1 2 3 4 5 XLAT VOLTAGE (V) BLANK VOLTAGE (V) Figure 5. XLAT Pull−down Current vs. Input Voltage 12 SWITCH ON RESISTANCE (W) 40V VBATT 10V/div 10 8 Figure 6. BLANK Pull−up Current vs. Input Voltage 125°C 6 4 2 0 85°C 25°C −40°C LED current 20mA/ div 2 3 4 VCC VOLTAGE (V) 5 6 5 msec / div Figure 7. VBATT Load Dump Figure 8. Switch On−resistance vs. VCC http://onsemi.com 6 CAT310 TYPICAL CHARACTERISTICS (VCC = 5 V, VBATT = 14 V, TAMB = 25°C, unless otherwise specified.) 14 QUIESCENT CURRENT (mA) OUTPUT PIN LEAKAGE (mA) 12 10 8 6 4 2 0 10 11 12 13 14 15 125°C 85°C 25°C −40°C 16 20 15 10 5 0 −50 −25 0 25 50 75 100 125 OUTPUT PIN BIAS VOLTAGE (V) TEMPERATURE (°C) Figure 9. Output Channel Leakage vs. Bias Voltage 24 OVERVOLTAGE DETECTION (V) UNDERVOLTAGE LOCKOUT (V) 22 20 18 16 14 −50 3.0 2.5 2.0 1.5 1.0 0.5 Figure 10. Quiescent Current vs. Temperature −25 0 25 50 75 100 125 0 −50 −25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. VBATT Overvoltage Detection vs. Temperature Functional Description Figure 12. VCC Undervoltage Lockout vs. Temperature The CAT310 implements a 10−bit serial−in shift register for storing the setting of the ten outputs. Serial input data SIN are clocked into the shift register on the rising edge of the clock. At the 10th clock pulse, the first data bit entered is outputted from the shift register to SOUT. The following clock pulses will output the following data bits onto SOUT. The output data pattern replicates the input data stream with a delay of ten clock pulses. The 10−bit data pattern present in the shift register is stored in the 10−bit data latch when the latch signal XLAT Serial to Parallel Shift Register CLK → SIN → Data Latch XLAT → Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 is logic high. When XLAT transitions to logic low, data are latched and stay unchanged for as long as XLAT remains low. The last serial input data corresponds to OUT0. The serial input data that was received 10 clock pulse ago is stored in OUT9. When the BLANK input is logic high, all the output switches are in the off state. If the BLANK input is low, the 10−bit data latches control the 10 output switches. A data bit value of zero keeps the switch off. A data bit value of one keeps the switch on. Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 → SOUT ↓ LED OUT0 ↓ LED OUT1 ↓ LED OUT2 ↓ LED OUT3 ↓ LED OUT4 ↓ LED OUT5 ↓ LED OUT6 ↓ LED OUT7 ↓ LED OUT8 ↓ LED OUT9 http://onsemi.com 7 CAT310 1/fsclk SCLK tsu th twl twh SIN tpd SOUT th tsu XLAT BLANK tpd tpd OUTn Output Switch OFF Output Switch ON Figure 13. Timing Diagram Application Information For applications with a large number of LEDs, several CAT310 drivers can be daisy chained. The serial data output pin (SOUT) of the first driver is connected to the second driver data input pin (SIN). This sequence is repeated until the last driver is linked. All drivers are controlled by the VBATTERY = 14 V (typical) + V BATT same clock signal. Figure 14 shows an example with three CAT310 devices driving a total of 30 LEDs in parallel. The controller transmits the serial data sequentially through the CAT310 devices. For N drivers connected in cascade, after 10 x N clock pulses, the data are latched with one single XLAT transition. − OUT0 VBAT VCC SIN SOUT CAT310 SCLK BLANK XLAT GND PGND OUT1 OUT9 VCC OUT0 VBAT VCC SIN SOUT CAT310 SCLK BLANK XLAT GND PGND OUT1 OUT9 VCC OUT0 OUT9 OUT1 VBAT VCC SIN SOUT CAT310 SCLK BLANK XLAT GND PGND VCC + 5V − 4.7 mF CONTROLLER Figure 14. Daisy Chain Application Diagram http://onsemi.com 8 CAT310 PACKAGE DIMENSIONS SOIC−20, 300 mils CASE 751BJ−01 ISSUE O SYMBOL A A1 A2 b c E1 E D E E1 e h L b PIN#1 IDENTIFICATION TOP VIEW e 0.25 0.40 0.81 MIN 2.36 0.10 2.05 0.31 0.20 12.60 10.01 7.40 NOM 2.49 MAX 2.64 0.30 2.55 0.41 0.27 12.80 10.30 7.50 1.27 BSC 0.51 0.33 13.00 10.64 7.60 0.75 1.27 θ θ1 0º 5º 8º 15º D h h q1 A A2 q A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. L END VIEW q1 c http://onsemi.com 9 CAT310 Example of Ordering Information (Note 2) Prefix CAT Device # 310 Suffix W − T1 Company ID (Optional) Product Number 310 Package W: SOIC Tape & Reel (Note 5) T: Tape & Reel 1: 1,000 / Reel 2. 3. 4. 5. The device used in the above example is a CAT310W−T1 (SOIC, Tape & Reel, 1,000 / Reel). All packages are RoHS−compliant (Lead−free, Halogen−free). The standard lead finish is Matte−Tin. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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