CAT310W-T1

CAT310 LED Driver, 10-Channel Description The CAT310 is a 10−channel LED driver for automotive and other lighting applications. All LED output channels are driven from a low on−resistance open−drain High Voltage CMOS Nch−FETs and are fully compliant with “Load Dump” transients of up to 40 volts. The LED bias current of each channel can be set independently using an external series ballast resistor, making the device ideal for multi−color instrumentation displays. A high−speed serial interface (suitable with both 3.3 volt and 5 volt systems) feeding a 10 bit shift register is used to program the desired state (on/off) of each channel. The device offers a blanking control pin (BLANK) which can be used to disable all channels on demand. A serial output data pin (SOUT) is provided to daisy−chain devices in large cluster LED applications. During initial power up all channels are reset and cleared via an under−voltage lock out (UVLO) detector and for added protection all channels are disabled in the event of a battery over−voltage condition (19 volts or more). Features • • • • • • • • • • Automotive “Load Dump” Protection (40 V) 10 Independent LED Channels Up to 50 mA Output per Channel Overvoltage Detection at 19 V Serial Interface for Channel Programming Daisy Chain Output for Multi−driver Cascading LED Blanking Control Operating Temperature from −40°C to +125°C 20−pin SOIC Package This Device is Pb−Free, Halogen Free/BFR Free and RoHS Compliant http://onsemi.com SOIC−20 W SUFFIX CASE 751BJ PIN CONNECTIONS SCLK XLAT SIN SOUT GND OUT4 OUT3 OUT2 OUT1 OUT0 NC BLANK VCC VBATT PGND OUT5 OUT6 OUT7 OUT8 OUT9 1 MARKING DIAGRAM CAT310W CAT310W = Specific Device Code Applications • • • • Automotive Lighting White and Other Color High Brightness LEDs Multi−color High−brightness LED Cluster Displays General LED Lighting © Semiconductor Components Industries, LLC, 2009 November, 2009 − Rev. 2 ORDERING INFORMATION 1 Device Package Shipping CAT310W SOIC−20 (Pb−Free) 1,000/Tape & Reel Publication Order Number: CAT310/D CAT310 VBATTERY 14 V (typical) RS1 RS2 30 mA OUT1 OUT9 BLANK CAT310 XLAT SIN SCLK GND PGND SOUT VBATT OUT0 VCC RS10 330 W VCC 5V 1 mF Figure 1. Typical Application Circuit Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit 7 V Input voltage range (SIN, SCLK, BLANK, XLAT) −0.3 V to VCC + 0.3 V V SOUT voltage range −0.3 V to VCC + 0.3 V V Peak OUT0 to OUT9 voltage 40 V VBATT input voltage 40 V DC output current on OUT0 to OUT9 70 mA Storage Temperature Range −55 to +160 °C Operating Junction Temperature Range VCC voltage −40 to +150 °C Lead Soldering Temperature (10 sec.) 300 °C ESD Rating: Low Voltage Pins Human Body Model Machine Model 3000 300 ESD Rating: VBATT, OUT[0:9] pins Human Body Model Machine Model 1000 100 V V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 2. RECOMMENDED OPERATING CONDITIONS Parameter VCC Range Unit 3.0 to 5.5 V Voltage applied to OUT0 to OUT9 9 to 17 V Output current on OUT0 to OUT9 0 to 50 mA −40 to +125 _C Ambient Temperature Range http://onsemi.com 2 CAT310 Electrical Operating Characteristics Table 3. DC CHARACTERISTICS (VCC = 5.0 V, −40°C ≤ TA ≤ 125°C, over recommended operating conditions unless specified otherwise.) Name Symbol ISTBY Standby Quiescent Current VOVP VBATT Over Voltage Protection Trigger threshold VUVLO VCC Under Voltage Lockout Trigger threshold Conditions Min Static input signal. All outputs turned off. 17 Max Units 1 10 mA 19 21 V 1.7 2.5 V 5 12 W 0.1 10 mA RSW Switch on resistance for OUT0 to OUT9 IO(n) = 30 mA IO(n)LKG OUT0 to OUT9 Output Switch Leakage V(OUT(n)) = 15 V IXLAT XLAT Internal Pull−down current XLAT = VCC XLAT = 0.3 V 4 1 10 3 30 6 mA IBLANK BLANK Internal Pull−up current BLANK = 0 V BLANK = VCC − 0.3 V 4 1 10 3 30 6 mA 0.7 VCC V 5 mA VIH VIL Logic high input voltage Logic low input voltage IIL Logic Input leakage current (SCLK, SIN) VI = VCC or GND SOUT logic high output voltage SOUT logic low output voltage IOH = −1 mA IOL = 1 mA VOH VOL 2 Typ 0.3 VCC −5 0 VCC −0.3 V V 0.3 Table 4. SWITCHING CHARACTERISTICS (VCC = 5.0 V, −40°C ≤ TA ≤ 125°C, over recommended operating conditions unless specified otherwise.) Name Symbol Conditions Min Typ Max Units 10 MHz SCLK fSCLK SCLK Clock Frequency twh/wl SCLK Pulse width High or Low 30 ns SIN tsu Setup time SIN to SCLK 10 ns th Hold time SIN to SCLK 10 ns 20 ns 20 ns XLAT tw XLAT Pulse width SIN to SCLK th Hold time SCLK to XLAT tr SOUT rise time (10% to 90%) CL = 15 pF 20 ns tf SOUT fall time (90% to 10%) CL = 15 pF 15 ns tpd Propagation delay time Blank ↑ to OUT(n) 25 ns tpd Propagation delay time Blank ↓ to OUT(n) 25 ns tpd Propagation delay time SCLK to SOUT 25 ns 1. All logic inputs contain Schmitt trigger inputs. http://onsemi.com 3 CAT310 2.5 V UVLO + – VCC RESET SCLK SIN 10 BIT SHIFT REGISTER XLAT 10 BIT DATA LATCHES SOUT OUT0 BLANK OR + VBATT DISABLE 10 BIT DRIVER DRV0 – DRV9 OUT9 SW−0 SW−9 19 V GND PGND Figure 2. Block Diagram http://onsemi.com 4 CAT310 PIN DESCRIPTIONS VCC is the supply input for the internal logic and is compatible with both 3.3 V and 5 V systems. The logic is held in a reset state until VCC exceeds 2.5 V. It is recommended that a small bypass ceramic capacitor (1 mF) be placed between VCC and GND pins on the device. SIN is the CMOS logic pin for delivering the serial input data stream into the internal 10−bit shift register. The most recent or last data value in the serial stream is used to configure the state of output channel “zero” (OUT0). During the initial power up sequence all contents of the shift register are reset and cleared to zero. SCLK is the CMOS logic pin used to clock the internal shift register. On each rising edge of clock, the serial data will advance through one stage of the shift register. XLAT is the CMOS logic input used to transfer data from the 10−bit shift register into the output channel latches. An internal pull−down current of 10 microampere is present on this pin. When XLAT is low, the state of each output channel remains unchanged. When XLAT is driven high, the contents of the shift register appear at their respective output channels. An external pull−up resistance of 10 kW or less is adequate for logic high. PGND, GND pins should be connected to the ground on the PCB. BLANK is the CMOS logic input (active high) used to temporarily disable all outputs. An internal pull−up current of 10 microampere is present on this pin. The BLANK pin must be driven to a logic low in order for channel outputs to resume normal operation. An external pull−down resistance of 10 kW or less is adequate for logic low. SOUT is the CMOS logic output used for daisy chain applications. The serial output data stream is fed from the last stage of the internal 10−bit shift register. On each rising edge of the clock, the SOUT value will be updated. The data value present on this pin is identical to the data value being used for configuring the state of output channel nine (OUT9). At initial power up, the SOUT data stream will contain all zeroes until the shift register has been fully loaded. VBATT input monitors the battery voltage. If an over−voltage, above 19 V typical, is detected, all outputs are disabled. Upon conclusion of the over−voltage condition, all outputs resume normal operation. The current drawn by the VBATT pin is less than 1 microampere during normal operation. OUT0−OUT9 are the ten LED outputs connected internally to the switch N−channel FETs. They sink currents up to 50 mA per channel and can withstand transients up to 40 V compatible with automotive “load dump”. The output on−resistance is 5 W, and the off−resistance is 5 MW. Table 5. PIN TABLE Pin Number Pin Name 1 SCLK Clock input for the data shift register. 2 XLAT Control input for the data latch. 3 SIN 4 SOUT Serial data output. 5 GND Ground. 6−10 OUT4 − OUT0 Open drain outputs. 11−15 OUT9 − OUT5 Open drain outputs. 16 PGND Ground for LED driver outputs. 17 VBATT Battery sense input. 18 VCC 19 BLANK 20 N.C. Description/Function Serial data input. Power supply voltage for the logic Blank input. When BLANK is high, all the output drivers are turned off. No connect. http://onsemi.com 5 CAT310 TYPICAL CHARACTERISTICS (VCC = 5 V, VBATT = 14 V, TAMB = 25°C, unless otherwise specified.) BLANK 5V/div VBATT 5V/div LED current 50mA/div 18V LED current 50mA/ div OUT pin voltage 10V/div 1 msec / div 50 msec / div Figure 3. VBATT Overvoltage Detection Amplitude between 16 V and 26 V Figure 4. BLANK and Output Waveform 14 14 −40°C 25°C 10 85°C 8 125°C 6 4 25°C 10 85°C 125°C 8 6 4 VCC = 5 V 2 2 0 −40°C 12 BLANK CURRENT (mA) XLAT CURRENT (mA) 12 0 1 2 3 4 0 5 0 1 2 3 4 5 XLAT VOLTAGE (V) BLANK VOLTAGE (V) Figure 5. XLAT Pull−down Current vs. Input Voltage Figure 6. BLANK Pull−up Current vs. Input Voltage 12 SWITCH ON RESISTANCE (W) 40V VBATT 10V/div LED current 20mA/ div 10 8 125°C 85°C 6 25°C 4 −40°C 2 0 2 3 4 5 5 msec / div VCC VOLTAGE (V) Figure 7. VBATT Load Dump Figure 8. Switch On−resistance vs. VCC http://onsemi.com 6 6 CAT310 TYPICAL CHARACTERISTICS (VCC = 5 V, VBATT = 14 V, TAMB = 25°C, unless otherwise specified.) 20 12 QUIESCENT CURRENT (mA) OUTPUT PIN LEAKAGE (mA) 14 10 8 6 125°C 4 85°C 25°C 2 0 10 5 −40°C 10 11 12 13 14 15 0 −50 16 −25 0 25 50 75 100 125 OUTPUT PIN BIAS VOLTAGE (V) TEMPERATURE (°C) Figure 9. Output Channel Leakage vs. Bias Voltage Figure 10. Quiescent Current vs. Temperature 3.0 UNDERVOLTAGE LOCKOUT (V) 24 OVERVOLTAGE DETECTION (V) 15 22 20 18 16 14 −50 −25 0 25 50 75 100 2.5 2.0 1.5 1.0 0.5 0 −50 125 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. VBATT Overvoltage Detection vs. Temperature Figure 12. VCC Undervoltage Lockout vs. Temperature 125 Functional Description is logic high. When XLAT transitions to logic low, data are latched and stay unchanged for as long as XLAT remains low. The last serial input data corresponds to OUT0. The serial input data that was received 10 clock pulse ago is stored in OUT9. When the BLANK input is logic high, all the output switches are in the off state. If the BLANK input is low, the 10−bit data latches control the 10 output switches. A data bit value of zero keeps the switch off. A data bit value of one keeps the switch on. The CAT310 implements a 10−bit serial−in shift register for storing the setting of the ten outputs. Serial input data SIN are clocked into the shift register on the rising edge of the clock. At the 10th clock pulse, the first data bit entered is outputted from the shift register to SOUT. The following clock pulses will output the following data bits onto SOUT. The output data pattern replicates the input data stream with a delay of ten clock pulses. The 10−bit data pattern present in the shift register is stored in the 10−bit data latch when the latch signal XLAT Serial to Parallel Shift Register CLK → SIN → Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Data Latch ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ XLAT → LED OUT0 LED OUT1 LED OUT2 LED OUT3 LED OUT4 LED OUT5 LED OUT6 LED OUT7 LED OUT8 http://onsemi.com 7 Bit 9 ↓ LED OUT9 → SOUT CAT310 1/fsclk SCLK tsu th twl twh SIN tpd SOUT th tsu XLAT BLANK tpd tpd OUTn Output Switch OFF Output Switch ON Figure 13. Timing Diagram Application Information same clock signal. Figure 14 shows an example with three CAT310 devices driving a total of 30 LEDs in parallel. The controller transmits the serial data sequentially through the CAT310 devices. For N drivers connected in cascade, after 10 x N clock pulses, the data are latched with one single XLAT transition. For applications with a large number of LEDs, several CAT310 drivers can be daisy chained. The serial data output pin (SOUT) of the first driver is connected to the second driver data input pin (SIN). This sequence is repeated until the last driver is linked. All drivers are controlled by the VBATTERY = 14 V (typical) + V BATT − OUT0 OUT1 VCC + 5V − 4.7 mF OUT9 VBAT VCC SIN SOUT CAT310 SCLK BLANK XLAT GND PGND CONTROLLER VCC OUT0 VCC OUT1 OUT9 VBAT VCC SIN SOUT CAT310 SCLK BLANK XLAT GND PGND Figure 14. Daisy Chain Application Diagram http://onsemi.com 8 OUT0 OUT9 OUT1 VBAT VCC SIN SOUT CAT310 SCLK BLANK XLAT GND PGND CAT310 Example of Ordering Information (Note 2) 2. 3. 4. 5. Prefix Device # Suffix CAT 310 W − T1 Company ID (Optional) Product Number 310 Package W: SOIC Tape & Reel (Note 5) T: Tape & Reel 1: 1,000 / Reel The device used in the above example is a CAT310W−T1 (SOIC, Tape & Reel, 1,000 / Reel). All packages are RoHS−compliant (Lead−free, Halogen−free). The standard lead finish is Matte−Tin. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−20, 300 mils CASE 751BJ−01 ISSUE O E1 DATE 19 DEC 2008 SYMBOL MIN NOM MAX A 2.36 2.49 2.64 A1 0.10 0.30 A2 2.05 2.55 b 0.31 0.51 c 0.20 0.27 0.33 D 12.60 12.80 13.00 E 10.01 10.30 10.64 E1 7.40 7.50 7.60 E 1.27 BSC e b 0.41 e PIN#1 IDENTIFICATION 0.75 h 0.25 L 0.40 θ 0º 8º θ1 5º 15º 0.81 1.27 TOP VIEW D h A2 A A1 SIDE VIEW h q1 q q1 L c END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. DOCUMENT NUMBER: DESCRIPTION: 98AON34287E SOIC−20, 300 MILS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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