CS8126

CS8126 5.0 V, 750 mA Low Dropout Linear Regulator with Delayed RESET The CS8126 is a low dropout, high current 5.0 V linear regulator. It is an improved replacement for the CS8156. Improvements include higher accuracy, tighter saturation control, better supply rejection, and enhanced RESET circuitry. Familiar PNP regulator features such as reverse battery protection, overvoltage shutdown, thermal shutdown, and current limit make the CS8126 suitable for use in automotive and battery operated equipment. Additional on−chip filtering has been included to enhance rejection of high frequency transients on all external leads. An active microprocessor RESET function is included on−chip with externally programmable delay time. During power−up, or after detection of any error in the regulated output, the RESET lead will remain in the low state for the duration of the delay. Types of errors include short circuit, low input voltage, overvoltage shutdown, thermal shutdown, or others that cause the output to become unregulated. This function is independent of the input voltage and will function correctly with an output voltage as low as 1.0 V. Hysteresis is included in both the reset and Delay comparators for enhanced noise immunity. A latching discharge circuit is used to discharge the Delay capacitor, even when triggered by a relatively short fault condition. This circuit improves upon the commonly used SCR structure by providing full capacitor discharge (0.2 V type). Note: The CS8126 is lead compatible with the LM2927 and LM2926. Features http://onsemi.com TO−220−5 T SUFFIX CASE 314D 1 5 TO−220−5 TVA SUFFIX CASE 314K Pin 1. VIN 2. VOUT 3. GND 4. Delay 5. RESET 1 TO−220−5 THA SUFFIX CASE 314A 1 5 TO−220−5 THE SUFFIX CASE 314J 1 5 • • • • • • Low Dropout Voltage (0.6 V at 0.5 A) 3.0% Output Accuracy Active RESET External RESET Delay for Reset Protection Circuitry − Reverse Battery Protection − +60 V, −50 V Peak Transient Voltage − Short Circuit Protection − Internal Thermal Overload Protection Pb−Free Packages are Available D2PAK−7 DPS SUFFIX CASE 936AB 1 7 Pin 1. VIN 2. VOUT 3. VOUT(SENSE) 4. GND 5. Delay 6. RESET 7. NC ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 9 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 1 February, 2006 − Rev. 16 Publication Order Number: CS8126/D CS8126 VIN Over Voltage Shutdown VOUT Pre−Regulator Regulated Supply for Circuit Bias Bandgap Reference Error Amp − + Anti−Saturation and Current Limit Internally connected on TO−220−5 VOUT(SENSE) Charge Current Generator Thermal Shutdown Delay Latching Discharge − Q S R − + VDischarge + − Delay Comparator RESET + Reset Comparator GND Figure 1. Block Diagram http://onsemi.com 2 CS8126 MAXIMUM RATINGS* Rating Power Dissipation Peak Transient Voltage (46 V Load Dump) Output Current ESD Susceptibility (Human Body Model) Package Thermal Resistance, TO−220−5: Junction−to−Case, RqJC Junction−to−Ambient, RqJA Package Thermal Resistance, D2PAK−7: Junction−to−Case, RqJC Junction−to−Ambient, RqJA Junction Temperature Range Storage Temperature Range Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) Value Internally Limited −50, 60 Internally Limited 4.0 2.1 50 2.1 10−50** −40 to +150 −55 to +150 260 peak 230 peak Unit − V − kV °C/W °C/W °C/W °C/W °C °C °C °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. 10 second maximum. 2. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. **Depending on thermal properties of substrate. RqJA = RqJC + RqCA. ELECTRICAL CHARACTERISTICS (TA = −40°C to +125°C, TJ = −40°C to +150°C, VIN = 6.0 to 26 V, IO = 5.0 to 500 mA, RRESET = 4 .7 kW t o VCC, unless otherwise noted.) Characteristic Output Stage (VOUT) Output Voltage Dropout Voltage Supply Current IOUT1 = 500 mA IOUT ≤ 10 mA IOUT ≤ 100 mA IOUT ≤ 500 mA VIN = 6.0 to 26 V, IOUT = 50 mA IOUT = 50 to 500 mA, VIN = 14 V f = 120 Hz, VIN = 7.0 to 17 V, IOUT = 250 mA − − VOUT ≤ 5.5 V VOUT ≥ −0.6 V, 10 W Load 1.0% Duty Cycle, T < 100 ms, 10 W Load Note 3 − 4.85 − − − − − − 54 0.75 32 − −15 − 150 5.00 0.35 2.0 6.0 55 5.0 10 75 1.20 − 95 −30 −80 180 5.15 0.60 7.0 12 100 50 50 − − 40 − − − 210 V V mA mA mA mV mV dB A V V V V °C Test Conditions Min Typ Max Unit Line Regulation Load Regulation Ripple Rejection Current Limit Overvoltage Shutdown Maximum Line Transient Reverse Polarity Input Voltage DC Reverse Polarity Input Voltage Transient Thermal Shutdown 3. Guaranteed By Design http://onsemi.com 3 CS8126 ELECTRICAL CHARACTERISTICS (continued) (TA = −40°C to +125°C, TJ = −40°C to +150°C, VIN = 6.0 to 26 V, IO = 5.0 to 500 mA, RRESET = 4 .7 kW t o VCC, unless otherwise noted.) Characteristic RESET and Delay Functions Delay Charge Current RESET Threshold RESET Hysteresis Delay Threshold Delay Hysteresis RESET Output Voltage Low RESET Output Leakage Current Delay Capacitor Discharge Voltage Delay Time * Delay Time + CDelay ICharge Test Conditions Min Typ Max Unit VDelay = 2.0 V VOUT Increasing, VRT(ON) VOUT Decreasing, VRT(OFF) VRH = VRT(ON) − VRT(OFF) Charge, VDC(HI) Discharge, VDC(LO) − 1.0 V < VOUT < VRTL, 3.0 kW to VOUT VOUT > VRT(ON) Discharge Latched “ON”, VOUT > VRT CDelay = 0.1 mF*. Note 4 VDelayThreshold Charge + CDelay 3.2 5.0 4.65 4.50 150 3.25 2.85 200 − − − 16 10 4.90 4.70 200 3.50 3.10 400 0.1 0 0.2 32 15 VOUT − 0.01 VOUT − 0.15 250 3.75 3.35 800 0.4 10 0.5 48 mA V V mV V V mV V mA V ms 4. Assumes Ideal Capacitor PACKAGE LEAD DESCRIPTION PACKAGE LEAD # TO−220−5 1 2 3 4 5 − − D2PAK−7 1 2 4 5 6 3 7 LEAD SYMBOL VIN VOUT GND Delay RESET VOUT(SENSE) NC Unregulated supply voltage to IC. Regulated 5.0 V output. Ground connection. Timing capacitor for RESET function. CMOS/TTL compatible output lead. RESET goes low after detection of any error in the regulated output or during power up. Remote sensing of output voltage. No Connection. FUNCTION http://onsemi.com 4 CS8126 TYPICAL PERFORMANCE CHARACTERISTICS RLOAD = 25 W 55 50 45 40 ICQ (mA) 35 30 25 20 15 10 5.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 −40°C 25°C 125°C Room Temp. 120 110 100 90 80 ICQ (mA) 70 60 50 40 30 20 10 0 0 1.0 2.0 3.0 4.0 5.0 RLOAD = 6.67 RLOAD = 10 RLOAD = 25 RLOAD = NO LOAD 6.0 7.0 8.0 9.0 10 VIN (V) VIN (V) Figure 2. ICQ vs. VIN Over Temperature RLOAD = 25 W 5.5 5.0 4.5 4.0 VOUT (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1.0 25°C Figure 3. ICQ vs. VIN Over RLOAD Room Temp. 5.5 5.0 4.5 4.0 VOUT (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 RLOAD = 10 RLOAD = NO LOAD RLOAD = 6.67 3.5 125°C −40°C 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 VIN (V) VIN (V) Figure 4. VOUT vs. VIN Over Temperature Figure 5. VOUT vs. VIN Over RLOAD 100 80 60 Line Regulation (mV) 40 20 0 −20 −40 −60 −80 −100 0 VIN 6.0−26 V 6.0 4.0 Load Regulation (mV) 2.0 0 −2.0 −4.0 −6.0 −8.0 −10 −12 −14 TEMP = −40°C TEMP = 25°C TEMP = 40°C TEMP = 25°C VIN = 14 V TEMP = 125°C TEMP = 125°C 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 700 800 Output Current (mA) Output Current (mA) Figure 6. Line Regulation vs. Output Current Over Temperature http://onsemi.com 5 Figure 7. Load Regulation vs. Output Current Over Temperature CS8126 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 900 800 Dropout Voltage (mV) 700 600 500 400 300 200 100 0 0 100 200 300 400 500 600 700 800 −40°C 125°C 25°C 100 90 Quiescent Current (mA) 80 70 60 50 40 30 20 10 0 0 100 200 300 400 500 VIN = 14 V 25°C 125°C −40°C 600 700 800 Output Current (mA) Output Current (mA) Figure 8. Dropout Voltage vs. Output Current Over Temperature Figure 9. Quiescent Current vs. Output Current Over Temperature 90 80 70 Rejection (dB) 60 ESR (W) 50 40 30 20 10 0 100 101 102 103 104 105 106 107 108 COUT = 10 mF, ESR = 1.0 W COUT = 0 F, ESR = 1 COUT= 110mmF, & 0.1= F, & 0.1 = 0 ESR = 0 ESR m 1 ESR mF, 103 102 101 100 10−1 10−2 COUT = 10 mF, ESR = 10 W COUT = 47/68 mF Stable Region COUT = 47 mF COUT = 68 mF 10−3 10−4 100 101 102 103 Freq. (Hz) Output Current (mA) Figure 10. Ripple Rejection Figure 11. Output Capacitor ESR RESET CIRCUIT WAVEFORM VOUT VRT(ON) VRT(OFF) VRH (1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max:RESET Voltage (1.0 V) RESET (3) (1) (2) VRL tDelay Delay VDC(HI) VDC(LO) VDH (2) VDIS Figure 12. RESET Circuit Waveform http://onsemi.com 6 CS8126 CIRCUIT DESCRIPTION The CS8126 RESET function, has hysteresis on both the Reset and Delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1.0 V. The RESET circuit output is an open collector type with ON and OFF parameters as specified. The RESET output NPN transistor is controlled by the two circuits described (see Block Diagram). Low Voltage Inhibit Circuit This circuit monitors output voltage, and when the output voltage falls below VRT(OFF), causes the RESET output transistor to be in the ON (saturation) state. When the output voltage rises above VRT(ON), this circuit permits the RESET output transistor to go into the OFF state if allowed by the RESET Delay circuit. RESET Delay Circuit voltage is above VRT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the delay capacitor). The discharge current is latched ON when the output voltage falls below VRT(OFF). The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures a controlled RESET pulse is generated following detection of an error condition. The circuit allows the RESET output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than VDC(H1). The Delay time for the RESET function is calculated from the formula: Delay time + CDelay VDelayThreshold ICharge 3.2 105 Delay time + CDelay This circuit provides a programmable (by external capacitor) delay on the RESET output lead. The Delay lead provides source current to the external delay capacitor only when the “Low Voltage Inhibit” circuit indicates that output If CDelay = 0.1 mF, Delay time (ms) = 32 ms ± 50%: i.e. 16 ms to 48 ms. The tolerance of the capacitor must be taken into account to calculate the total variation in the delay time. VIN C1* 100 nF Delay Delay 0.1 mF GND VOUT CS8126 RESET RRST 4.7 kW C2** 10 mF to 100 mF * C1 is required if the regulator is far from the power source filter. ** C2 is required for stability. Figure 13. Application Diagram APPLICATION NOTES Stability Considerations The output or compensation capacitor helps determine three main characteristics of a linear regulator: start−up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor C2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. http://onsemi.com 7 CS8126 Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. Calculating Power Dissipation in a Single Output Linear Regulator where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: RQJA + 150°C * TA PD (2) The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN VIN IOUT SMART REGULATOR® Control Features VOUT IQ Figure 14. Single Output Regulator With Key Performance Parameters Labeled Heat Sinks A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA. RQJA + RQJC ) RQCS ) RQSA (3) The maximum power dissipation for a single output regulator (Figure 14) is: PD(max) + VIN(max) * VOUT(min) IOUT(max) ) VIN(max)IQ (1) where: RqJC = the junction−to−case thermal resistance, RqCS = the case−to−heatsink thermal resistance, and RqSA = the heatsink−to−ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. http://onsemi.com 8 CS8126 ORDERING INFORMATION Device CS8126−1YT5 CS8126−1YT5G CS8126−1YTVA5 CS8126−1YTVA5G CS8126−1YTHA5 CS8126−1YTHA5G CS8126−1YTHE5 CS8126−1YTHE5G CS8126−1YTHER5 CS8126−1YTHER5G CS8126−1YDPS7 CS8126−1YDPS7G CS8126−1YDPSR7 CS8126−1YDPSR7G Package TO−220−5 STRAIGHT TO−220−5 STRAIGHT (Pb−Free) TO−220−5 VERTICAL TO−220−5 VERTICAL (Pb−Free) TO−220−5 HORIZONTAL TO−220−5 HORIZONTAL (Pb−Free) TO−220−5 SURFACE MOUNT TO−220−5 SURFACE MOUNT (Pb−Free) TO−220−5 SURFACE MOUNT TO−220−5 SURFACE MOUNT (Pb−Free) D2PAK−7 D2PAK−7 (Pb−Free) D2PAK−7 D2PAK−7 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 750 / Tape & Reel 750 / Tape & Reel Shipping † 50 Units/Rail 50 Units/Rail 50 Units/Rail 50 Units/Rail 50 Units/Rail 50 Units/Rail 50 Units/Rail 50 Units/Rail 750 / Tape & Reel 750 / Tape & Reel 50 Units/Rail 50 Units/Rail MARKING DIAGRAMS TO−220−5 T SUFFIX CASE 314D TO−220−5 TVA SUFFIX CASE 314K TO−220−5 THA SUFFIX CASE 314A TO−220−5 THE SUFFIX CASE 314J D2PAK−7 DPS SUFFIX CASE 936AB CS 8126 AWLYWWG CS 8126 AWLYWWG CS 8126 AWLYWWG CS 8126 AWLYWWG CS 8126 AWLYWWG 1 1 1 A WL, L YY, Y WW, W G 1 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Device http://onsemi.com 9 CS8126 PACKAGE DIMENSIONS TO−220−5 T SUFFIX CASE 314D−04 ISSUE E −T− −Q− B C E SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM A B C D E G H J K L Q U INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.067 BSC 0.087 0.112 0.015 0.025 0.990 1.045 0.320 0.365 0.140 0.153 0.105 0.117 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 1.702 BSC 2.210 2.845 0.381 0.635 25.146 26.543 8.128 9.271 3.556 3.886 2.667 2.972 U K 12345 A L G D 5 PL J H M 0.356 (0.014) M TQ TO−220−5 TVA SUFFIX CASE 314K−01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D, INCLUDING PROTRUSION, SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM A B C D E F G J K L M Q R S U W INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.027 0.037 0.045 0.055 0.530 0.545 0.067 BSC 0.014 0.022 0.785 0.800 0.321 0.337 0.063 0.078 0.146 0.156 0.271 0.321 0.146 0.196 0.460 0.475 5_ MILLIMETERS MIN MAX 14.22 14.99 9.78 10.54 4.06 4.83 0.69 0.94 1.14 1.40 13.46 13.84 1.70 BSC 0.36 0.56 19.94 20.32 8.15 8.56 1.60 1.98 3.71 3.96 6.88 8.15 3.71 4.98 11.68 12.07 5_ −T− B −Q− W U 12345 SEATING PLANE C E A L M G J S R F K D 5 PL M 0.356 (0.014) TQ M http://onsemi.com 10 CS8126 PACKAGE DIMENSIONS TO−220−5 THA SUFFIX CASE 314A−03 ISSUE E −T− B −P− OPTIONAL CHAMFER SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 0.043 (1.092) MAXIMUM. INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.570 0.585 0.067 BSC 0.015 0.025 0.730 0.745 0.320 0.365 0.140 0.153 0.210 0.260 0.468 0.505 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 14.478 14.859 1.702 BSC 0.381 0.635 18.542 18.923 8.128 9.271 3.556 3.886 5.334 6.604 11.888 12.827 C E Q U A L F K G 5X 5X J D 0.014 (0.356) M S TP M DIM A B C D E F G J K L Q S U TO−220−5 THE SUFFIX CASE 314J−01 ISSUE O −T− C −Q− B E SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. 4. DIMENSIONS EXCLUSIVE OF MOLD FLASH AND METAL BURRS. 5. FOOTPAD LENGTH MEASURED FROM LEAD TIP WITH REFERENCE TO DATUM −M−. 6. COPLANARITY 0.004" MAX. REFERENCE TO DATUM −N− STANDOFF HEIGHT 0.00 − 0.010". INCHES MIN MAX 0.568 0.583 0.395 0.405 0.170 0.180 0.028 0.036 0.045 0.055 0.543 0.558 0.067 BSC 0.014 0.022 0.073 0.088 0.324 0.339 0.146 0.156 0.000 0.010 0.460 0.475 5° MILLIMETERS MIN MAX 14.43 14.81 10.03 10.29 4.32 4.57 0.71 0.91 1.14 1.40 13.79 14.17 1.70 BSC 0.36 0.56 1.85 2.24 8.23 8.61 3.71 3.96 0.00 0.25 11.68 12.07 5° W A L 1 2 3 4 5 U F D 0.356 (0.014) M 5 PL TQ M J G −M− K DIM A B C D E F G J K L Q S U W S 0.102 (0.004) −N− http://onsemi.com 11 CS8126 PACKAGE DIMENSIONS D2PAK−7 (SHORT LEAD) DPS SUFFIX CASE 936AB−01 ISSUE A A E TERMINAL 8 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E G H K L M N P R S U V INCHES MIN MAX 0.396 0.406 0.326 0.336 0.170 0.180 0.026 0.036 0.045 0.055 0.050 REF 0.539 0.579 0.055 0.066 0.000 0.010 0.100 0.110 0.017 0.023 0.058 0.078 0° 8° 0.095 0.105 0.256 REF 0.305 REF MILLIMETERS MIN MAX 10.05 10.31 8.28 8.53 4.31 4.57 0.66 0.91 1.14 1.40 1.27 REF 13.69 14.71 1.40 1.68 0.00 0.25 2.54 2.79 0.43 0.58 1.47 1.98 0° 8° 2.41 2.67 6.50 REF 7.75 REF K U S B H L P G N R M V D C SOLDERING FOOTPRINT* 9.5 0.374 3.25 0.128 C L 10.54 0.415 C L 3.8 0.150 1 0.96 0.038 SCALE 3:1 mm inches 2.16 0.085 1.27 0.050 8.26 0.325 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan : ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 12 CS8126/D