NCP1593BGEVB

NCP1593A, NCP1593B Synchronous Buck Regulator 1 MHz, 3 A The NCP1593 is a fixed 1 MHz, high−output−current, synchronous PWM converter that integrates a low−resistance, high−side P−channel MOSFET and a low−side N−channel MOSFET. The NCP1593 utilizes internally compensated current mode control to provide good transient response, ease of implementation and excellent loop stability. It regulates input voltages from 4.0 V to 5.5 V down to an output voltage as low as 0.6 V and is able to supply up to 3 A of load current. The NCP1593 includes an internally fixed switching frequency (FSW), and an internal soft−start to limit inrush current. Other features include cycle−by−cycle current limiting, 100% duty cycle operation, short− circuit protection, power saving mode and thermal shutdown. Features • Wide Input Voltage Range: from 4.0 V to 5.5 V • Internal 90 mW High−Side P−Channel MOSFET and 60 mW • • • • • • • • • • http://onsemi.com MARKING DIAGRAMS A L Y W G 1593B ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) Low−Side N−Channel MOSFET Fixed 1 MHz Switching Frequency Cycle−by−Cycle Current Limiting Hiccup Mode Short−Circuit Protection Overtemperature Protection Internal Soft−Start Start−up with Pre−Biased Output Load Adjustable Output Voltage Down to 0.6 V Diode Emulation During Light Load 100% Duty Cycle Operation to Extend the Battery Life These are Pb−Free Devices PIN CONNECTIONS NC 1 10 VCCP LX 2 9 VCCP LX 3 GND PG 4 8 VCCA 7 SS EN 5 6 FB NCP1593A (Top View) LX 1 10 VCCP LX 2 Applications • • • • • • 1593A ALYWG G DFN10 CASE 485C 9 VCCP LX 3 Set−Top Boxes DVD Drives and HDD LCD Monitors and TVs Cable Modems USB Modems Telecom/Networking/Datacom Equipment GND 8 VCCA PG 4 7 NC EN 5 6 FB NCP1593B (Top View) ORDERING INFORMATION Package Shipping† NCP1593AMNTWG DFN10 (Pb−Free) 3000 / Tape & Reel NCP1593BMNTWG DFN10 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2012 August, 2019 − Rev. 2 1 Publication Order Number: NCP1593/D NCP1593A, NCP1593B BLOCK DIAGRAM NCP1593A VCCP VCC Power Reset UVLO THD Hiccup EN SS + CA − Ri OSC + PMOS Soft−Start M1 LX − PWM + + + gm − Vref FB Control Logic LX Rc1 Cc2 PG Power Good Cc1 PGND 0.9 x Vref Figure 1. Block Diagram PIN DESCRIPTIONS Pin No Symbol 1 NC / LX Description No connect pin for NCP1593A. The user may ground this pin or leave it floating. / LX pin for NCP1593B 2, 3 LX The drains of the internal MOSFETs. The output inductor should be connected to these pins. 4 PG Open drain output from the Power Good logic. When the FB voltage is within regulation, this is a high impedance pin. Otherwise it is pulled low. 5 EN Logic input to enable the part. Logic high to turn on the part and a logic low to shut off the part. An internal pullup forces the part into an enable state when no external bias is present on the pin. 6 FB Feedback input pin of the Error Amplifier. Connect a resistor divider from the converter’s output voltage to this pin to set the converter’s regulated voltage. 7 SS / NC An external capacitor on this pin sets the soft−start ramp time. Leaving this pin open sets the soft−start time at 500 ms. For NCP1593B this pin is a no connect and should be left floating. 8 VCC Input supply pin for internal bias circuitry. Connect a 0.1 mF ceramic bypass capacitor to this pin. Directly connect the VCC pin to the VCCP pin on the board. 9, 10 VCCP Input for the power stage EP GND Exposed pad of the package provides both electrical contact to the ground and good thermal contact to the PCB. This pad must be soldered to the PCB for proper operation. http://onsemi.com 2 NCP1593A, NCP1593B APPLICATION CIRCUIT 9,10 8 22 mF 5 4 7 LX 2 LX 3 FB 6 NC 1 VCCP VCCA EN PG NCP1593 4.0 V − 5.5 V Vin 2.2 mH Vout 22 mF R1 22 mF R2 PGND EP SS Figure 2. Recommended Application Circuit ABSOLUTE MAXIMUM RATINGS Rating Power Supply Pin (Pins 8, 9, 10) to GND Symbol Value Unit Vin 6.5 −0.3 (DC) −1.0 (t < 100 ns) V Vin + 0.7 Vin + 1.0 (t < 20 ns) −0.7 (DC) −5.0 (t < 100 ns) V 6.0 −0.3 (DC) −1.0 (t < 100 ns) V LX to GND All other pins Operating Ambient Temperature Range (Note 1) TA −40 to +85 °C Operating Junction Temperature Range (Note 1) TJ −40 to +125 °C TJ(MAX) +150 °C TS −55 to +150 °C RqJA 68 °C/W Maximum Junction Temperature Storage Temperature Range Thermal Resistance Junction−to−Air (Note 2) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The maximum package power dissipation limit must not be exceeded. PD + T J(max) * T A R qJA 2. RqJA measured on approximately 1x1 inch sq. of 1 oz. Copper FR−4 or G−10 board. http://onsemi.com 3 NCP1593A, NCP1593B ELECTRICAL CHARACTERISTICS (−40°C < TJ < 125°C, VCC = 4.0 V − 5.5 V, for min/max values unless noted otherwise) Parameter Input Voltage Range VCC UVLO Threshold UVLO Hysteresis Symbol Test Conditions Min VIN 4.0 VUVLO 2.4 Typ 2.5 Max Unit 5.5 V 2.9 V VUVLO_hys 320 mV VCC Quiescent Current IINVCC 1.0 1.5 mA VCCP Quiescent Current IINVCCP 20 50 mA Shutdown Supply Current IQSHDN 1.8 3.0 mA 0.591 0.6 0.609 V 0.594 0.6 0.606 V 10 100 nA −65 dB FEEDBACK VOLTAGE Reference Voltage VFB Reference Voltage VFB Feedback Input Bias Current IFB Feedback Voltage Line Regulation (Note 3) TJ = 25°C VCC = 4.0 V to 5.5 V PWM Maximum Duty Cycle (Regulating) d.c.MAX Maximum Duty Cycle (LDO mode) d.c.LDO Minimum Controllable On Time tONmin 95 Vout > d.c.MAX * VIN % 100 % 35 ns 5.1 A Current Limit Cycle-by-cycle Current Limit (Note 3) ILIM VCC = 5.0 V, TJ = 25°C Oscillator Switching Frequency fSW 0.87 1.0 1.13 MHz 90 190 mW 10 mA 90 mW 10 mA MOSFET’s High-Side MOSFET On Resistance High-Side MOSFET Leakage Low-Side MOSFET On Resistance Low-Side MOSFET Leakage RDSonH IDS = 100 mA, VIN = 5.0 V IlkgH LX = 0 V RDSonL IDS = 100 mA, VIN = 5.0 V IlkgL LX = 5 V 60 POWER GOOD Power Good Rising Threshold Power Good Falling Threshold Power Good Hysteresis (High-to-Low) Power Good Pulldown Voltage VPGH 0.51 0.54 VPHL 0.48 0.51 V 30 mV VPGhys VRPG IPG = 2.5 mA 130 V 250 mV ENABLE Enable High Threshold VENHI 1.4 V Enable Low Threshold VENLO Enable Hysteresis VENhys 200 IEN 1.4 3.0 mA 0.58 0.65 ms Enable Pullup Current 0.4 V mV Soft-Start Default Soft-start Ramp Time tSS SS = open; fSW = 1MHz Maximum Soft-start Ramp time tSS SS = max cap; fSW = 1MHz 0.5 Hiccup Timer Soft-start Current ISS 0.51 10 ms 4 * tSS ms 0.7 0.87 mA Thermal Shutdown Thermal Shutdown Threshold 185 °C Thermal Shutdown Hysteresis 30 °C 3. Guaranteed by Characterization. http://onsemi.com 4 NCP1593A, NCP1593B TYPICAL CHARACTERISTICS 100 100 95 95 EFFICIENCY (%) EFFICIENCY (%) VIN = 4.5 V 90 VIN = 5.0 V 85 80 75 70 0.01 0.1 1 0.1 1 10 IOUT, OUTPUT CURRENT (A) Figure 3. Efficiency vs. Output Current (3.3 V) Figure 4. Efficiency vs. Output Current (1.8 V) 3.40 90 VOUT, OUTPUT VOLTAGE (V) EFFICIENCY (%) 0.01 IOUT, OUTPUT CURRENT (A) VIN = 4.0 V 85 VIN = 5.0 V 80 75 70 0.01 0.1 1 10 3.38 3.36 3.34 VIN = 5.0 V 3.32 3.30 VIN = 4.5 V 3.28 3.26 3.24 3.22 3.20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.6 1.4 IOUT, OUTPUT CURRENT (A) IOUT, OUTPUT CURRENT (A) Figure 5. Efficiency vs. Output Current (1.05 V) Figure 6. Load Regulation (3.3 V) 1.90 1.15 1.88 1.13 VOUT, OUTPUT VOLTAGE (V) VOUT, OUTPUT VOLTAGE (V) 80 70 10 95 1.86 1.84 1.82 VIN = 5.0 V 1.80 1.78 VIN = 4.5 V 1.76 1.74 1.72 1.70 VIN = 5.0 V 85 75 100 65 VIN = 4.0 V 90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.11 1.09 1.07 VIN = 5.0 V 1.05 1.03 VIN = 4.5 V 1.01 0.99 0.97 0.95 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 IOUT, OUTPUT CURRENT (A) IOUT, OUTPUT CURRENT (A) Figure 7. Load Regulation (1.8 V) Figure 8. Load Regulation (1.05 V) http://onsemi.com 5 1.8 2.0 1.8 2.0 NCP1593A, NCP1593B TYPICAL CHARACTERISTICS 5.50 5.25 4.75 PEAK CURRENT LIMIT (A) PEAK CURRENT LIMIT (A) 5.00 VIN = 5.0 V 4.50 4.25 4.00 3.75 3.50 −40 −25 −10 5 20 35 50 65 80 5.00 4.75 4.50 4.25 4.00 3.75 3.50 95 110 125 4.00 4.25 4.50 4.75 5.00 5.25 TJ, JUNCTION TEMPERATURE (°C) INPUT VOLTAGE (V) Figure 9. Current Limit vs. Temperature Figure 10. Current Limit vs. Input Voltage 5.50 125 115 RDS(ON) (mW) 105 P−MOSFET (HS) 95 85 75 N−MOSFET (LS) 65 55 45 −40 −15 10 35 60 85 110 (VIN = 5 V, VOUT = 1.05 V, IOUT = 0.5 A to 3.0 A) Upper Trace: Output Voltage, 50 mV / div Lower Trace: Output Current, 2 A / div Time = 200 ms/div TJ, JUNCTION TEMPERATURE (°C) Figure 11. RDS(ON) vs. Temperature Figure 12. Load Transient Response (VIN = 5 V, VOUT = 1.05 V, IOUT = 0.5 A to 3.0 A) Upper Trace: Output Voltage, 50 mV / div Lower Trace: Output Current, 2 A / div Time = 200 ms/div (VIN = 5 V, VOUT = 1.05 V, IOUT = 0 A) Upper Trace: LX Pin Switching Waveforms, 5 V / div Middle Trace: Output Voltage, 20 mV / div Lower Trace: Inductor Current, 100 mA / div Time = 20 ms / div Figure 13. Load Transient Response Figure 14. No Load Switching (1.05 V) http://onsemi.com 6 NCP1593A, NCP1593B TYPICAL CHARACTERISTICS (VIN = 5 V, VOUT = 1.8 V, IOUT = 0 A) Upper Trace: LX Pin Switching Waveforms, 5 V / div Middle Trace: Output Voltage, 20 mV / div Lower Trace: Inductor Current, 100 mA / div Time = 10 ms / div (VIN = 5 V, VOUT = 3.3 V, IOUT = 0 A) Upper Trace: LX Pin Switching Waveforms, 5 V / div Middle Trace: Output Voltage, 20 mV / div Lower Trace: Inductor Current, 200 mA / div Time = 10 ms / div Figure 15. No Load Switching (1.8 V) Figure 16. No Load Switching (3.3 V) (VIN = 5 V, VOUT = 1.05 V, IOUT = 100 mA) Upper Trace: LX Pin Switching Waveforms, 5 V / div Middle Trace: Output Voltage, 20 mV / div Lower Trace: Inductor Current, 200 mA / div Time = 500 ns / div (VIN = 5 V, VOUT = 1.8 V, IOUT = 150 A) Upper Trace: LX Pin Switching Waveforms, 5 V / div Middle Trace: Output Voltage, 20 mV / div Lower Trace: Inductor Current, 200 mA / div Time = 500 ns / div Figure 17. DCM Switching (1.05 V) Figure 18. DCM Switching (1.8 V) (VIN = 5 V, VOUT = 3.3 V, IOUT = 100 mA) Upper Trace: LX Pin Switching Waveforms, 5 V / div Middle Trace: Output Voltage, 20 mV / div Lower Trace: Inductor Current, 200 mA / div Time = 500 ns / div (VIN = 5 V, VOUT = 1.8 V, IOUT = 3 A) Upper Trace: LX Pin Switching Waveforms, 5 V / div Middle Trace: Output Voltage, 20 mV / div Lower Trace: Inductor Current, 2 A / div Time = 500 ns / div Figure 19. DCM Switching (3.3 V) Figure 20. CCM Switching (1.8 V) http://onsemi.com 7 NCP1593A, NCP1593B TYPICAL CHARACTERISTICS (VIN = 5 V, VOUT = 1.8 V, IOUT = 3 A) Upper Trace: Input Voltage, 5 V / div Second Trace: Power Good Pin Voltage, 5 V / div Third Trace: Output Voltage, 2 V / div Lower Trace: Inductor Current, 2 A / div Time = 1 ms / div (VIN = 5 V, VOUT = 1.8 V, IOUT = 3 A) Upper Trace: Input Voltage, 5 V / div Second Trace: Power Good Pin Voltage, 5 V / div Third Trace: Output Voltage, 2 V / div Lower Trace: Inductor Current, 2 A / div Time = 200 ms / div (VIN = 5 V, VOUT = 1.8 V, IOUT = 3 A, no CSS) Upper Trace: Enable Pin Voltage, 5 V / div Second Trace: Power Good Pin Voltage, 5 V / div Third Trace: Output Voltage, 2 V / div Lower Trace: Inductor Current, 2 A / div Time = 2 ms / div (VIN = 5 V, VOUT = 1.8 V, IOUT = 3 A, CSS = 4.7 nF) Upper Trace: Enable Pin Voltage, 5 V / div Second Trace: Power Good Pin Voltage, 5 V / div Third Trace: Output Voltage, 2 V / div Lower Trace: Inductor Current, 2 A / div Time = 2 ms / div Figure 23. Power On from Enable Figure 24. Power On from Enable CSS = 4.7 n Figure 21. Power On from Input Voltage Figure 22. Power Off from Input Voltage (VIN = 5 V, VOUT = 1.8 V, IOUT = Current Limit, no CSS) Upper Trace: LX Pin Voltage, 5 V / div Middle Trace: Output Voltage, 2 V / div Lower Trace: Inductor Current, 2 A / div Time = 500 ms / div (VIN = 5 V, VOUT = 1.8 V, IOUT = 3 A) Upper Trace: Enable Pin Voltage, 5 V / div Second Trace: Power Good Pin Voltage, 5 V / div Third Trace: Output Voltage, 2 V / div Lower Trace: Inductor Current, 2 A / div Time = 200 ms / div Figure 25. Power Off from Enable Figure 26. Short Circuit Operation http://onsemi.com 8 NCP1593A, NCP1593B DETAILED DESCRIPTION Overview The NCP1593 is a synchronous PWM controller that incorporates all the control and protection circuitry necessary to satisfy a wide range of applications. The NCP1593 employs current mode control to provide fast transient response, simple compensation, and excellent stability. The features of the NCP1593 include a precision reference, fixed 1 MHz switching frequency, a transconductance error amplifier, an integrated high−side P−channel MOSFET and low−side N−Channel MOSFET, internal soft−start, and very low shutdown current. The protection features of the NCP1593 include internal soft−start, pulse−by−pulse current limit, and thermal shutdown. t SS + ǒC SS V FBǓ I SS (eq. 1) Where: VFB: Reference voltage, typically 0.6 V ISS: Soft−start current, typically 0.7 mA Output MOSFETs The NCP1593 includes low RDS(on), both high−side P−channel and low−side N−channel MOSFETs capable of delivering up to 3.0 A of current. When the controller is disabled or during a Fault condition, the controller’s output stage is tri−stated by turning OFF both the upper and lower MOSFETs. Reference Voltage Pulse Width Modulation The NCP1593 incorporates an internal reference that allows output voltages as low as 0.6 V. The tolerance of the internal reference is guaranteed over the entire operating temperature range of the controller. The reference voltage is trimmed using a test configuration that accounts for error amplifier offset and bias currents. A high−speed PWM comparator, capable of pulse widths as low as 35 ns, is included in the NCP1593. The inverting input of the comparator is connected to the output of the error amplifier. The non−inverting input is connected to the the current sense signal. At the beginning of each PWM cycle, the CLK signal sets the PWM flip−flop and the upper MOSFET is turned ON. When the current sense signal rises above the error amplifier’s voltage then the comparator will reset the PWM flip−flop and the upper MOSFET will be turned OFF. Oscillator Frequency A fixed precision oscillator is provided. The oscillator frequency range is 1 MHz with $13% variation. Transconductance Error Amplifier Current Sense The transconductance error amplifier’s primary function is to regulate the converter’s output voltage using a resistor divider connected from the converter’s output to the FB pin of the controller, as shown in the applications schematic. If a Fault occurs, the amplifier’s output is immediately pulled to GND and PWM switching is inhibited. The NCP1593 monitors the current in the upper MOSFET. The current signal is required by the PWM comparator and the pulse−by−pulse current limiter. Soft−Start To limit the startup inrush current, a soft−start circuit is used to ramp up the reference voltage from 0 V to its final value linearly. This soft−start time is internally set to a typical value of 500 ms, or it can be externally adjusted by adding a capacitor (CSS) from the SS pin to GND. The following formulas show how to set the externally adjustable soft-start time. The maximum allowable CSS is 10 nF. http://onsemi.com 9 NCP1593A, NCP1593B PROTECTIONS Undervoltage Lockout (UVLO) Pre−Bias Startup The under voltage lockout feature prevents the controller from switching when the input voltage is too low to power the internal power supplies and reference. Hysteresis is incorporated in the UVLO comparator to prevent resistive drops in the wiring or PCB traces from causing ON/OFF cycling of the controller during heavy loading at power up or power down. In some applications the controller will be required to start switching when it’s output capacitors are charged anywhere from slightly above 0 V to just below the regulation voltage. This situation occurs for a number of reasons: the converter’s output capacitors may have residual charge on them or the converter’s output may be held up by a low current standby power supply. NCP1593 supports pre−bias start up by holding off switching off until the soft start ramp reaches the FB Pin voltage. Overcurrent Protection (OCP) NCP1593 detects high side switch current and then compares to a voltage level representing the overcurrent threshold limit. If the current through the high side FET exceeds the overcurrent threshold limit for seven consecutive switching cycles, overcurrent protection is triggered. Once the overcurrent protection occurs, hiccup mode engages. First, hiccup mode, turns off both FETs and discharges the internal compensation network at the output of the OTA. Next, the IC waits typically 4 x tSS ms and then resets the overcurrent counter. After this reset, the circuit attempts another normal soft−start. Hiccup mode reduces input supply current and power dissipation during a short circuit. It also allows for much improved system up−time, allowing auto−restart upon removal of a temporary short−circuit. Power Good Power Good (PG) is an open-drain output that requires a pull−up resistor. It is actively held low in soft−start, standby, and shutdown. PG releases when the FB voltage and thus the output voltage rises above 90% of nominal regulation point. The PG goes low when the FB voltage falls below 85% of the regulation point. Thermal Shutdown The NCP1593 protects itself from over heating with an internal thermal monitoring circuit. If the junction temperature exceeds the thermal shutdown threshold both the upper and lower MOSFETs will be shut OFF. http://onsemi.com 10 NCP1593A, NCP1593B APPLICATION INFORMATION Programming the Output Voltage The output voltage is set using a resistive voltage divider from the output voltage to FB pin (see Figure 27). So the output voltage is calculated according to Eq.1. V out + V FB @ R1 ) R2 C OUT(min) + (eq. 4) 8 @ f @ V ripple Where Vripple is the allowed output voltage ripple. The required ESR for this amount of ripple can be calculated by equation 5. (eq. 2) R2 I ripple ESR + Vout V ripple (eq. 5) I ripple Based on Equation 3 to choose capacitor and check its ESR according to Equation 4. If ESR exceeds the value from Eq.4, multiple capacitors should be used in parallel. Ceramic capacitor can be used in most of the applications. In addition, both surface mount tantalum and through−hole aluminum electrolytic capacitors can be used as well. R1 FB R2 Input Capacitor Selection The input capacitor can be calculated by Equation 6. Figure 27. Output divider C in(min) + I out(max) @ D max @ The inductor is the key component in the switching regulator. The selection of inductor involves trade−offs among size, cost and efficiency. The inductor value is selected according to the equation 2. L+ f @ I ripple ǒ @ 1* V out V in(max) Ǔ f @ V in(ripple) (eq. 6) Where Vin(ripple) is the required input ripple voltage. Inductor Selection V out 1 D max + V out V in(min) is the maximum duty cycle. (eq. 7) Power Dissipation The NCP1593 is available in a thermally enhanced 10−pin, DFN package. When the die temperature reaches +185°C, the NCP1593 shuts down (see the Thermal−Overload Protection section). The power dissipated in the device is the sum of the power dissipated from supply current (PQ), power dissipated due to switching the internal power MOSFET (PSW), and the power dissipated due to the RMS current through the internal power MOSFET (PON). The total power dissipated in the package must be limited so the junction temperature does not exceed its absolute maximum rating of +150°C at maximum ambient temperature. Calculate the power lost in the NCP1593 using the following equations: 1. High side MOSFET The conduction loss in the top switch is: (eq. 3) Where Vout − the output voltage; f − switching frequency, 1.0 MHz; Iripple − Ripple current, usually it’s 20% − 30% of output current; Vin(max) − maximum input voltage. Choose a standard value close to the calculated value to maintain a maximum ripple current within 30% of the maximum load current. If the ripple current exceeds this 30% limit, the next larger value should be selected. The inductor’s RMS current rating must be greater than the maximum load current and its saturation current should be about 30% higher. For robust operation in fault conditions (start−up or short circuit), the saturation current should be high enough. To keep the efficiency high, the series resistance (DCR) should be less than 0.1 W, and the core material should be intended for high frequency applications. P HSON + I Where: Output Capacitor Selection I RMS_FET + The output capacitor acts to smooth the dc output voltage and also provides energy storage. So the major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of the converter. This ripple is related to capacitance and the ESR. The minimum capacitance required for a certain output ripple can be calculated by Equation 4. 2 RMS_HSFET Ǹǒ I out 2 ) R DS(on)HS DI PP 12 Ǔ (eq. 8) 2 D (eq. 9) DIPP is the peak−to−peak inductor current ripple. The power lost due to switching the internal power high side MOSFET is: http://onsemi.com 11 NCP1593A, NCP1593B P HSSW + V in @ I out @ ǒt r ) t fǓ @ f SW die temperature reaches the thermal shutdown threshold the NCP1593 shut down and does not restart again until the die temperature cools by 30°C. (eq. 10) 2 tr and tf are the rise and fall times of the internal power MOSFET measured at SW node. Typical rise times are 4 ns (rising) and 2 ns (falling). 2. Low side MOSFET The power dissipated in the top switch is: P LSON + I RMS_LSFET 2 @ R DS(on)LS Where: I RMS_LSFET + Ǹǒ I out 2 ) DI PP 12 Ǔ Layout Consideration As with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. For 1.0MHz switching frequency, switch rise and fall times are typically in few nanosecond range. To prevent noise both radiated and conducted the high speed switching current path must be kept as short as possible. Shortening the current path will also reduce the parasitic trace inductance of approximately 25 nH/inch. At switch off, this parasitic inductance produces a flyback spike across the NCP1593 switch. When operating at higher currents and input voltages, with poor layout, this spike can generate voltages across the NCP1593 that may exceed its absolute maximum rating. A ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise. The FB component should be kept as far away as possible from the switch node. The ground for these components should be separated from the switch current path. Failure to do so will result in poor stability or subharmonic like oscillation. Board layout also has a significant effect on thermal resistance. Reducing the thermal resistance from ground pin and exposed pad onto the board will reduce die temperature and increase the power capability of the NCP1593. This is achieved by providing as much copper area as possible around the exposed pad. Adding multiple thermal vias under and around this pad to an internal ground plane will also help. Similar treatment to the inductor pads will reduce any additional heating effects. (eq. 11) 2 @ (1 * D ) (eq. 12) DIPP is the peak−to−peak inductor current ripple. The switching loss for the low side MOSFET can be ignored. The power lost due to the quiescent current (IQ) of the device is: P Q + V in @ I Q (eq. 13) IQ is the switching quiescent current of the NCP1593. P TOTAL + P HSON ) P HSSW ) P LSON ) P Q (eq. 14) Calculate the temperature rise of the die using the following equation: T J + T C ) ǒP TOTAL @ q JAǓ (eq. 15) qJC is the junction−to−case thermal resistance equal to 68°C/W. TA is the ambient temperature and TJ is the junction temperature, or die temperature. Solder the underside−exposed pad to a large copper GND plane. If the http://onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN10, 3x3, 0.5P CASE 485C ISSUE F SCALE 2:1 DATE 16 DEC 2021 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot *This information is generic. Please refer to Y = Year device data sheet for actual part marking. W = Work Week Pb−Free indicator, “G” or microdot “G”, may G = Pb−Free Package or may not be present. Some products may (Note: Microdot may be in either location) not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON03161D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFN10, 3X3 MM, 0.5 MM PITCH PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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