NCP1597BGEVB

NCP1597B Buck Regulator Synchronous 1 MHz, 2 A The NCP1597B is a fixed 1 MHz, high−output−current, synchronous PWM converter that integrates a low−resistance, high−side P−channel MOSFET and a low−side N−channel MOSFET. The NCP1597B utilizes internally compensated current mode control to provide good transient response, ease of implementation and excellent loop stability. It regulates input voltages from 4.0 V to 5.5 V down to an output voltage as low as 0.8 V and is able to supply up to 2 A. The NCP1597B has features including fixed internal switching frequency (FSW), and an internal soft−start to limit inrush current. Using the EN pin, shutdown supply current is reduced to 3 mA maximum. Other features include cycle−by−cycle current limiting, short− circuit protection, power saving mode and thermal shutdown. Features • Input Voltage Range: from 4.0 V to 5.5 V • Internal 140 mW High−Side Switching P−Channel MOSFET and • • • • • • • • 90 mW Low−Side N−Channel MOSFET Fixed 1 MHz Switching Frequency Cycle−by−Cycle Current Limiting Overtemperature Protection Internal Soft−Start Start−up with Pre−Biased Output Load Adjustable Output Voltage Down to 0.8 V Power Saving Mode During Light Load These are Pb−Free Devices August, 2019 − Rev. 2 1597B ALYWG G DFN10 CASE 485C 1597B = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS EN 1 10 PGND VCC 2 9 PGND VCCP 3 8 LX AGND 4 7 LX FB 5 6 NC ORDERING INFORMATION Device DSP Power Hard Disk Drivers Computer Peripherals Home Audio Set−Top Boxes Networking Equipment LCD TV Wireless and DSL/Cable Modem USB Power Devices © Semiconductor Components Industries, LLC, 2013 MARKING DIAGRAM (Top View) Applications • • • • • • • • • http://onsemi.com NCP1597BMNTWG Package Shipping† DFN10 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 Publication Order Number: NCP1597B/D NCP1597B BLOCK DIAGRAM NCP1597B VCCP VCC Power Reset UVLO THD Hiccup EN + CA − OSC + PMOS Soft−Start M1 LX Vref FB − PWM + + + gm − Control Logic LX AGND PGND Figure 1. Block Diagram PIN DESCRIPTIONS Pin No Symbol 1 EN Logic input to enable the part. Logic high turns on the part and a logic low disables it. An internal pullup forces the part into an enable state when no external bias is present on the pin. 2 VCC Input supply pin for internal bias circuitry. A 0.1 mF ceramic bypass capacitor is preferred to connect to this pin. 3 VCCP Power input for the power stage 4 AGND Analog ground pin. Connect to thermal pad. 5 FB Feedback input pin of the Error Amplifier. Connect a resistor divider from the converter’s output voltage to this pin to set the converter’s output voltage. 6 NC No connection The drains of the internal MOSFETs. The output inductor should be connected to these pins. 7, 8 LX 9, 10 PGND EP PAD Description Power ground pins. Connect to thermal pad. Exposed pad of the package provides both electrical contact to the ground and good thermal contact to the PCB. This pad must be soldered to the PCB for proper operation. http://onsemi.com 2 NCP1597B APPLICATION CIRCUIT 22 mF 2 VCC 3 VCCP 1 EN 6 NC NCP1597B 4.0 V − 5.5 V Vin 4 AGND LX 8 LX 7 FB 5 PGND 10 PGND 0.8 V − 3.3 V Vout 3.3 mH 22 mF R1 22 mF R2 9 Figure 2. Recommended Schematic for NCP1597B ABSOLUTE MAXIMUM RATINGS Rating Power Supply Pin (Pin 4, 5) to GND Symbol Value Unit Vin 6.5 −0.3 (DC) −1.0 (t < 100 ns) V Vin + 0.7 Vin + 1.0 (t < 20 ns) −0.7 (DC) −5.0 (t < 100 ns) V 6.0 −0.3 (DC) −1.0 (t < 100 ns) V LX to GND All other pins Operating Temperature Range TA −40 to +85 °C Junction Temperature TJ −40 to +150 °C Storage Temperature Range TS −55 to +150 °C RqJA 68.5 °C/W Thermal Resistance Junction−to−Air (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. RqJA measured on approximately 1x1 inch sq. of 1 oz. Copper. http://onsemi.com 3 NCP1597B ELECTRICAL CHARACTERISTICS (Vin = 4.0 V − 5.5 V, Vout = 1.2 V, TJ = +25°C for typical value; −40°C < TA < 85°C for min/max values unless noted otherwise) Parameter Symbol Vin Input Voltage Range Test Conditions Vin Min Typ 4.0 VCC UVLO Threshold 3.2 UVLO Hysteresis 3.5 Max Unit 5.5 V 3.8 V 335 mV VCC Quiescent Current IinVCC Vin = 5 V,VFB = 1.5 V, (No Switching) 1.7 2.0 mA VCCP Quiescent Current IinVCCP Vin = 5 V,VFB = 1.5 V, (No Switching) 25 Vin Shutdown Supply Current (Note 2) IQSHDN EN = 0 V 1.8 3.0 mA 0.800 0.812 V VFB = 0.8 V 10 100 nA Vin = 4.0 V to 5.5 V 0.06 %/V 85 % 50 ns mA FEEDBACK VOLTAGE Reference Voltage VFB Feedback Input Bias Current IFB 0.788 Feedback Voltage Line Regulation PWM 82 Maximum Duty Cycle (regulating) Minimum Controllable ON Time (Note 2) PULSE−BY−PULSE CURRENT LIMIT Pulse−by−Pulse Current Limit (Regulation) ILIM 2.7 3.9 4.3 A Pulse−by−Pulse Current Limit (Soft−Start) ILIMSS 4.0 5.3 6.1 A FSW 0.87 1.0 1.13 MHz 140 200 mW 10 mA 125 mW 10 mA OSCILLATOR Oscillator Frequency MOSFET High Side MOSFET ON Resistance High Side MOSFET Leakage (Note 2) Low Side MOSFET ON Resistance Low Side MOSFET Leakage (Note 2) RDS(on) HS IDS = 100 mA, VGS = 5 V RDS(on) LS IDS = 100 mA, VGS = 5 V VEN = 0 V, VSW = 0 V 90 VEN = 0 V, VSW = 5 V ENABLE EN HI Threshold ENHI EN LO Threshold ENLO 1.4 V 0.4 EN Hysteresis 200 EN Pullup Current 1.4 V mV 3.0 mA SOFT−START 1.0 ms 2.0 ms Thermal Shutdown Threshold 185 °C Thermal Shutdown Hysteresis 30 °C Soft−Start Ramp Time tSS FSW = 1 MHz Hiccup Timer THERMAL SHUTDOWN 2. Guaranteed by design. Not production tested. http://onsemi.com 4 NCP1597B TYPICAL OPERATING CHARACTERISTICS 3.7 VFB, FB INPUT THRESHOLD (V) 815 3.6 UVLO (V) 3.5 UVLO Rising Threshold 3.4 3.3 UVLO Falling Threshold 3.2 3.1 −40 −15 10 35 800 795 790 10 35 60 TA, AMBIENT TEMPERATURE (°C) Figure 3. Undervoltage Lockout vs. Temperature Figure 4. Feedback Input Threshold vs. Temperature 85 6.0 1.2 ILIM (Soft−Start) 5.5 gm (mS) 1.1 1.0 0.9 5.0 4.5 −15 10 35 3.5 −40 85 60 TA, AMBIENT TEMPERATURE (°C) −15 10 35 60 85 TA, AMBIENT TEMPERATURE (°C) Figure 5. Switching Frequency vs. Temperature Figure 6. Current Limit vs. Temperature 2.0 1.8 1.8 ICC, DISABLED (mA) 2.0 1.6 1.4 1.2 1.0 −40 ILIM (Regulation) 4.0 0.8 0.7 −40 ICC, SWITCHING (mA) −15 TA, AMBIENT TEMPERATURE (°C) 1.3 fSW, SWITCH FREQUENCY (MHz) 805 785 −40 85 60 810 1.6 1.4 1.2 −15 10 35 1.0 −40 85 60 −15 10 35 60 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 7. Quiescent Current Into VCC vs. Temperature Figure 8. Quiescent Current Into VCC vs. Temperature http://onsemi.com 5 85 NCP1597B TYPICAL OPERATING CHARACTERISTICS 100 VOUT = 3.3 V L = 3.3 mH COUT = 2 x 22 mF 3.38 3.36 3.34 3.30 VIN = 5.0 V 3.28 3.26 VIN = 4.0 V 3.24 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 70 60 50 40 VOUT = 3.3 V L = 3.3 mH COUT = 2 x 22 mF 30 3.22 0 VIN = 5.0 V 80 3.32 3.20 VIN = 4.0 V 90 EFFICIENCY (%) VOUT, OUTPUT VOLTAGE (V) 3.40 20 0.01 2.0 0.1 Figure 9. Load Regulation for VOUT = 3.3 V 1.86 1.84 VIN = 4.0 V 90 80 1.82 EFFICIENCY (%) VOUT, OUTPUT VOLTAGE (V) 100 VOUT = 1.8 V L = 3.3 mH COUT = 2 x 22 mF 1.88 VIN = 5.0 V 1.80 1.78 VIN = 4.0 V 1.76 1.74 VIN = 5.0 V 70 60 50 40 VOUT = 1.8 V L = 3.3 mH COUT = 2 x 22 mF 30 1.72 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 20 0.01 2.0 IOUT, OUTPUT CURRENT (A) 1 10 Figure 12. Efficiency vs. Output Current for VOUT = 1.8 V 1.30 100 VOUT = 1.2 V L = 3.3 mH COUT = 2 x 22 mF 1.28 1.26 1.24 90 VIN = 4.0 V 80 1.22 EFFICIENCY (%) VOUT, OUTPUT VOLTAGE (V) 0.1 IOUT, OUTPUT CURRENT (A) Figure 11. Load Regulation for VOUT = 1.8 V VIN = 5.0 V 1.20 1.18 VIN = 4.0 V 1.16 1.14 VIN = 5.0 V 70 60 50 40 VOUT = 1.2 V L = 3.3 mH COUT = 2 x 22 mF 30 1.12 1.10 10 Figure 10. Efficiency vs. Output Current for VOUT = 3.3 V 1.90 1.70 1 IOUT, OUTPUT CURRENT (A) IOUT, OUTPUT CURRENT (A) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 20 0.01 IOUT, OUTPUT CURRENT (A) 0.1 1 IOUT, OUTPUT CURRENT (A) Figure 13. Load Regulation for VOUT = 1.2 V Figure 14. Efficiency vs. Output Current for VOUT = 1.2 V http://onsemi.com 6 10 NCP1597B (VIN = 5 V, ILOAD = 100 mA, L = 3.3 mH, COUT = 2 x 22 mF) Upper Trace: LX Pin Switching Waveform, 2 V/div Middle Trace: Output Ripple Voltage, 20 mV/div Lower Trace: Inductor Current, 1 A/div Time Scale: 1.0 ms/div (VIN = 5 V, ILOAD = 700 mA, L = 3.3 mH, COUT = 2 x 22 mF) Upper Trace: LX Pin Switching Waveform, 2 V/div Middle Trace: Output Ripple Voltage, 20 mV/div Lower Trace: Inductor Current, 1 A/div Time Scale: 1.0 ms/div Figure 15. DCM Switching Waveform for VOUT = 3.3 V Figure 16. CCM Switching Waveform for VOUT = 3.3 V (VIN = 5 V, ILOAD = 100 mA, L = 3.3 mH, COUT = 2 x 22 mF) Upper Trace: LX Pin Switching Waveform, 2 V/div Middle Trace: Output Ripple Voltage, 20 mV/div Lower Trace: Inductor Current, 200 mA/div Time Scale: 1.0 ms/div (VIN = 5 V, ILOAD = 400 mA, L = 3.3 mH, COUT = 2 x 22 mF) Upper Trace: LX Pin Switching Waveform, 2 V/div Middle Trace: Output Ripple Voltage, 20 mV/div Lower Trace: Inductor Current, 1 A/div Time Scale: 1.0 ms/div Figure 17. DCM Switching Waveform for VOUT = 1.2 V Figure 18. CCM Switching Waveform for VOUT = 1.2 V (VIN = 5 V, ILOAD = 100 mA, L = 3.3 mH, COUT = 2 x 22 mF) Upper Trace: EN Pin Voltage, 2 V/div Middle Trace: Output Voltage, 1 V/div Lower Trace: Inductor Current, 100 mA/div Time Scale: 500 ms/div (VIN = 5 V, ILOAD = 100 mA, L = 3.3 mH, COUT = 2 x 22 mF) Upper Trace: EN Pin Voltage, 2 V/div Middle Trace: Output Voltage, 1 V/div Lower Trace: Inductor Current, 100 mA/div Time Scale: 500 ms/div Figure 19. Soft−Start Waveforms for VOUT = 3.3 V Figure 20. Soft−Start Waveforms for VOUT = 1.2 V http://onsemi.com 7 NCP1597B (VIN = 5 V, ILOAD = 100 mA, L = 3.3 mH, COUT = 2 x 22 mF) Upper Trace: Output Dynamic Voltage, 100 mV/div Lower Trace: Output Current, 500 mA/div Time Scale: 200 ms/div (VIN = 5 V, ILOAD = 100 mA, L = 3.3 mH, COUT = 2 x 22 mF) Upper Trace: Output Dynamic Voltage, 100 mV/div Lower Trace: Output Current, 500 mA/div Time Scale: 200 ms/div Figure 21. Transient Response for VOUT = 3.3 V Figure 22. Transient Response for VOUT = 3.3 V (VIN = 5 V, ILOAD = 100 mA, L = 3.3 H, COUT = 2 x 22 mF) Upper Trace: Output Dynamic Voltage, 100 mV/div Lower Trace: Output Current, 500 mA/div Time Scale: 200 ms/div (VIN = 5 V, ILOAD = 100 mA, L = 3.3 H, COUT = 2 x 22 mF) Upper Trace: Output Dynamic Voltage, 100 mV/div Lower Trace: Output Current, 500 mA/div Time Scale: 200 ms/div Figure 23. Transient Response for VOUT = 1.2 V Figure 24. Transient Response for VOUT = 1.2 V http://onsemi.com 8 NCP1597B DETAILED DESCRIPTION Overview delivering up to 2.0 A of current. When the controller is disabled or during a Fault condition, the controller’s output stage is tri−stated by turning OFF both the upper and lower MOSFETs. The NCP1597B is a synchronous PWM controller that incorporates all the control and protection circuitry necessary to satisfy a wide range of applications. The NCP1597B employs internally compensated current mode control to provide good transient response, ease of implementation and excellent stability. The features of the NCP1597B include a precision reference, fixed 1 MHz switching frequency, a transconductance error amplifier, an integrated high−side P−channel MOSFET and low−side N−Channel MOSFET, internal soft−start, and very low shutdown current. The protection features of the NCP1597B include internal soft−start, pulse−by−pulse current limit, and thermal shutdown. Adaptive Dead Time Gate Driver In a synchronous buck converter, a certain dead time is required between the low side drive signal and high side drive signal to avoid shoot through. During the dead time, the body diode of the low side FET freewheels the current. The body diode has much higher voltage drop than that of the MOSFET, which reduces the efficiency significantly. The longer the body diode conducts, the lower the efficiency. In NCP1597B, the drivers and MOSFETs are integrated in a single chip. The parasitic inductance is minimized. Adaptive dead time control method is used in NCP1597B to prevent the shoot through from happening and minimizing the diode conduction loss at the same time. Reference Voltage The NCP1597B incorporates an internal reference that allows output voltages as low as 0.8 V. The tolerance of the internal reference is guaranteed over the entire operating temperature range of the controller. The reference voltage is trimmed using a test configuration that accounts for error amplifier offset and bias currents. Pulse Width Modulation A high−speed PWM comparator, capable of pulse widths as low as 50 ns, is included in the NCP1597B. The inverting input of the comparator is connected to the output of the error amplifier. The non−inverting input is connected to the the current sense signal. At the beginning of each PWM cycle, the CLK signal sets the PWM flip−flop and the upper MOSFET is turned ON. When the current sense signal rises above the error amplifier’s voltage then the comparator will reset the PWM flip−flop and the upper MOSFET will be turned OFF. Oscillator Frequency A fixed precision oscillator is provided. The oscillator frequency range is 1 MHz with $13% variation. Transconductance Error Amplifier The transconductance error amplifier’s primary function is to regulate the converter’s output voltage using a resistor divider connected from the converter’s output to the FB pin of the controller, as shown in the applications Schematic. If a Fault occurs, the amplifier’s output is immediately pulled to GND and PWM switching is inhibited. Power Save Mode If the load current decreases, the converter will enter power save mode operation automatically. During power save mode, the converter skips switching and operates with reduced frequency, which minimizes the quiescent current and maintain high efficiency. Internal Soft−Start To limit the startup inrush current, an internal soft start circuit is used to ramp up the reference voltage from 0 V to its final value linearly. The internal soft start time is 1 ms typically. Current Sense The NCP1597B monitors the current in the upper MOSFET. The current signal is required by the PWM comparator and the pulse−by−pulse current limiter. Output MOSFETs The NCP1597B includes low RDS(on), both high−side P−channel and low−side N−channel MOSFETs capable of http://onsemi.com 9 NCP1597B PROTECTIONS Undervoltage Lockout (UVLO) overcurrent detection while charging the output capacitors. Hiccup mode reduces input supply current and power dissipation during a short circuit. It also allows for much improved system up−time, allowing auto−restart upon removal of a temporary short−circuit. The under voltage lockout feature prevents the controller from switching when the input voltage is too low to power the internal power supplies and reference. Hysteresis must be incorporated in the UVLO comparator to prevent resistive drops in the wiring or PCB traces from causing ON/OFF cycling of the controller during heavy loading at power up or power down. Pre−Bias Startup In some applications the controller will be required to start switching when its output capacitors are charged anywhere from slightly above 0 V to just below the regulation voltage. This situation occurs for a number of reasons: the converter’s output capacitors may have residual charge on them or the converter’s output may be held up by a low current standby power supply. NCP1597B supports pre−bias start up by holding the low side FETs off till soft start ramp reaches the FB Pin voltage. Overcurrent Protection (OCP) NCP1597B detects high side switch current and then compares to a voltage level representing the overcurrent threshold limit. If the current through the high side FET exceeds the overcurrent threshold limit for seven consecutive switching cycles, overcurrent protection is triggered. Once the overcurrent protection occurs, hiccup mode engages. First, hiccup mode, turns off both FETs and discharges the internal compensation network at the output of the OTA. Next, the IC waits typically 2 ms and then resets the overcurrent counter. After this reset, the circuit attempts another normal soft−start. During soft−start, the overcurrent protection threshold is increased to prevent false Thermal Shutdown The NCP1597B protects itself from over heating with an internal thermal monitoring circuit. If the junction temperature exceeds the thermal shutdown threshold both the upper and lower MOSFETs will be shut OFF. http://onsemi.com 10 NCP1597B APPLICATION INFORMATION Programming the Output Voltage The output voltage is set using a resistive voltage divider from the output voltage to FB pin (see Figure 25). So the output voltage is calculated according to Eq.1. V out + V FB @ R1 ) R2 C OUT(min) + (eq. 3) 8 @ f @ V ripple Where Vripple is the allowed output voltage ripple. The required ESR for this amount of ripple can be calculated by equation 5. (eq. 1) R2 I ripple ESR + Vout V ripple (eq. 4) I ripple Based on Equation 2 to choose capacitor and check its ESR according to Equation 3. If ESR exceeds the value from Eq.4, multiple capacitors should be used in parallel. Ceramic capacitors can be used in most of the applications. In addition, both surface mount tantalum and through−hole aluminum electrolytic capacitors can be used as well. R1 FB R2 Maximum Output Capacitor NCP1597B family has internal 1 ms fixed soft−start and overcurrent limit. It limits the maximum allowed output capacitor to startup successfully. The maximum allowed output capacitor can be determined by the equation: Figure 25. Output divider Inductor Selection The inductor is the key component in the switching regulator. The selection of inductor involves trade−offs among size, cost and efficiency. The inductor value is selected according to the equation 2. L+ V out f @ I ripple ǒ @ 1* V out V in(max) Ǔ C out(max) + I limss(min) * I load(max) * Di p−p 2 V outńT SS(min) (eq. 5) Where TSS(min) is the soft−start period (1ms); DiPP is the current ripple. This is assuming that a constant load is connected. For example, with 3.3 V/2.0 A output and 20% ripple, the max allowed output capacitance is 546 mF. (eq. 2) Where Vout − the output voltage; f − switching frequency, 1.0 MHz; Iripple − Ripple current, usually it’s 20% − 30% of output current; Vin(max) − maximum input voltage. Choose a standard value close to the calculated value to maintain a maximum ripple current within 30% of the maximum load current. If the ripple current exceeds this 30% limit, the next larger value should be selected. The inductor’s RMS current rating must be greater than the maximum load current and its saturation current should be about 30% higher. For robust operation in fault conditions (start−up or short circuit), the saturation current should be high enough. To keep the efficiency high, the series resistance (DCR) should be less than 0.1 W, and the core material should be intended for high frequency applications. Input Capacitor Selection The input capacitor can be calculated by Equation 6. C in(min) + I out(max) @ D max @ 1 f @ V in(ripple) (eq. 6) Where Vin(ripple) is the required input ripple voltage. D max + V out V in(min) is the maximum duty cycle. (eq. 7) Power Dissipation The NCP1597B is available in a thermally enhanced 6−pin, DFN package. When the die temperature reaches +185°C, the NCP1597B shuts down (see the Thermal−Overload Protection section). The power dissipated in the device is the sum of the power dissipated from supply current (PQ), power dissipated due to switching the internal power MOSFET (PSW), and the power dissipated due to the RMS current through the internal power MOSFET (PON). The total power dissipated in the package must be limited so the junction temperature does not exceed its absolute maximum rating of +150°C at Output Capacitor Selection The output capacitor acts to smooth the dc output voltage and also provides energy storage. So the major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of the converter. This ripple is related to capacitance and the ESR. The minimum capacitance required for a certain output ripple can be calculated by Equation 4. http://onsemi.com 11 NCP1597B T J + T C ) ǒP TOTAL @ q JCǓ maximum ambient temperature. Calculate the power lost in the NCP1597B using the following equations: 1. High side MOSFET The conduction loss in the top switch is: P HSON + I Where: I RMS_FET + 2 R DS(on)HS RMS_HSFET Ǹǒ I out 2 ) DI PP 12 Ǔ qJC is the junction−to−case thermal resistance equal to 1.7°C/W. TC is the temperature of the case and TJ is the junction temperature, or die temperature. The case−to−ambient thermal resistance is dependent on how well heat can be transferred from the PC board to the air. Solder the underside−exposed pad to a large copper GND plane. If the die temperature reaches the thermal shutdown threshold the NCP1597B shut down and does not restart again until the die temperature cools by 30°C. (eq. 8) 2 D (eq. 9) DIPP is the peak−to−peak inductor current ripple. The power lost due to switching the internal power high side MOSFET is: P HSSW + V in @ I out @ ǒt r ) t fǓ @ f SW Layout As with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. To prevent noise both radiated and conducted, the high speed switching current path must be kept as short as possible. Shortening the current path will also reduce the parasitic trace inductance of approximately 25 nH/inch. At switch off, this parasitic inductance produces a flyback spike across the NCP1597B switch. When operating at higher currents and input voltages, with poor layout, this spike can generate voltages across the NCP1597B that may exceed its absolute maximum rating. A ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise. The FB component should be kept as far away as possible from the switch node. The ground for these components should be separated from the switch current path. Failure to do so will result in poor stability or subharmonic like oscillation. Board layout also has a significant effect on thermal resistance. Reducing the thermal resistance from the ground pin and exposed pad onto the board will reduce die temperature and increase the power capability of the NCP1597B. This is achieved by providing as much copper area as possible around the exposed pad. Adding multiple thermal vias under and around this pad to an internal ground plane will also help. Similar treatment to the inductor pads will reduce any additional heating effects. (eq. 10) 2 tr and tf are the rise and fall times of the internal power MOSFET measured at SW node. 2. Low side MOSFET The power dissipated in the top switch is: P LSON + I RMS_LSFET 2 @ R DS(on)LS Where: I RMS_LSFET + Ǹǒ I out 2 ) DI PP 12 Ǔ (eq. 11) 2 @ (1 * D ) (eq. 12) DIPP is the peak−to−peak inductor current ripple. The switching loss for the low side MOSFET can be ignored. The power lost due to the quiescent current (IQ) of the device is: P Q + V in @ I Q (eq. 13) IQ is the switching quiescent current of the NCP1597B. P TOTAL + P HSON ) P HSSW ) P LSON ) P Q (eq. 15) (eq. 14) Calculate the temperature rise of the die using the following equation: http://onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN10, 3x3, 0.5P CASE 485C ISSUE F SCALE 2:1 DATE 16 DEC 2021 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot *This information is generic. Please refer to Y = Year device data sheet for actual part marking. W = Work Week Pb−Free indicator, “G” or microdot “G”, may G = Pb−Free Package or may not be present. Some products may (Note: Microdot may be in either location) not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON03161D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFN10, 3X3 MM, 0.5 MM PITCH PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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