NVMFS5C404NLT3G

DATA SHEET www.onsemi.com MOSFET – Power, Single N-Channel V(BR)DSS ID MAX 0.67 mW @ 10 V 40 V 40 V, 0.67 mW, 370 A RDS(ON) MAX 370 A 1.0 mW @ 4.5 V NVMFS5C404NL D (5) Features • • • • • • Small Footprint (5x6 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses NVMFS5C404NLWF − Wettable Flank Option for Enhanced Optical Inspection AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant G (4) S (1,2,3) N−CHANNEL MOSFET MARKING DIAGRAMS DFN5 CASE 506EZ MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 40 V Gate−to−Source Voltage VGS ±20 V ID 370 A Continuous Drain Current RqJC (Notes 1, 3) TC = 25°C Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1, 2, 3) Steady State TC = 100°C TC = 25°C Pulsed Drain Current PD TC = 100°C TA = 25°C Power Dissipation RqJA (Notes 1 & 2) 260 Steady State 100 ID TA = 100°C TA = 25°C W 200 TA = 100°C W 3.9 1.9 IDM 900 A TJ, Tstg −55 to + 175 °C IS 191 A Single Pulse Drain−to−Source Avalanche Energy (IL(pk) = 38 A) EAS 907 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C TA = 25°C, tp = 10 ms Operating Junction and Storage Temperature Source Current (Body Diode) DFNW5 CASE 507BA D XXXXXX AYWZZ D D XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability A 52 37 PD 1 D S S S G ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit Junction−to−Case − Steady State RqJC 0.75 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 39 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2016 August, 2022 − Rev. 9 1 Publication Order Number: NVMFS5C404NL/D NVMFS5C404NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 40 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 21.6 VGS = 0 V, VDS = 40 V mV/°C TJ = 25 °C 10 TJ = 125°C 250 IGSS VDS = 0 V, VGS = 20 V VGS(TH) VGS = VDS, ID = 250 mA 100 mA nA ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance RDS(on) 1.2 2.0 −6.2 VGS = 10 V ID = 50 A 0.52 0.67 VGS = 4.5 V ID = 50 A 0.75 1.0 gFS VDS =15 V, ID = 50 A V mV/°C 270 mW S CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 12168 VGS = 0 V, f = 1 MHz, VDS = 25 V 4538 pF 79.8 Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 20 V; ID = 50 A 81 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 20 V; ID = 50 A 181 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Plateau Voltage VGP 2.7 td(ON) 24 8.5 VGS = 4.5 V, VDS = 20 V; ID = 50 A nC 27.8 23.8 V SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(OFF) VGS = 4.5 V, VDS = 20 V, ID = 50 A, RG = 1.0 W tf 135 ns 87 157 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 50 A TJ = 25°C 0.7 TJ = 125°C 0.61 tRR ta tb 1.2 V 97.4 VGS = 0 V, dIS/dt = 100 A/ms, IS = 50 A QRR 46.5 ns 50.9 190 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NVMFS5C404NL TYPICAL CHARACTERISTICS 3.0 V 700 ID, DRAIN CURRENT (A) 240 200 160 2.8 V 120 80 600 500 400 300 40 100 0 0 0 0.5 1.0 2.0 1.5 2.5 3.0 TJ = 125°C 0 1.0 1.5 2.0 2.5 3.0 3.5 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.0015 4.0 0.0010 0.0013 TJ = 25°C ID = 50 A 0.0012 VGS = 4.5 V 0.0008 0.0011 0.0010 0.0006 0.0009 0.0008 0.0007 VGS = 10 V 0.0004 0.0006 3 4 5 6 7 8 9 VGS, GATE VOLTAGE (V) 10 TJ = 25°C 0.0002 10 50 90 130 170 210 250 290 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1M 2.1 VGS = 10 V ID = 50 A 1.9 TJ = 150°C 100k IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE 0.5 TJ = −55°C VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.0014 0.0005 0.0004 TJ = 25°C 200 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (A) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 800 10 V to 3.2 V 280 1.7 1.5 1.3 1.1 0.9 TJ = 125°C 10k TJ = 85°C 1k 100 0.7 0.5 −50 −25 0 25 50 75 100 125 150 175 10 5 10 15 20 25 30 35 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 40 NVMFS5C404NL 10 CISS COSS VGS = 0 V TJ = 25°C f = 1 MHz CRSS 5 0 15 10 25 20 35 30 40 VGS, GATE−TO−SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 14k 13k 12k 11k 10k 9k 8k 7k 6k 5k 4k 3k 2k 1k 0 30 QT 25 8 20 6 15 4 QGD QGS 2 0 0 10 VDS = 20 V TJ = 25°C ID = 50 A 20 40 60 80 100 120 140 5 0 160 180 VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge VDS, DRAIN−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS 10,000 t, TIME (ns) IS, SOURCE CURRENT (A) 46 VGS = 4.5 V VDD = 20 V ID = 50 A td(off) 1000 tf tr td(on) 100 41 36 31 26 TJ = 125°C 21 16 11 TJ = 150°C TJ = 25°C 6 1000 1 10 1 100 0.3 0.4 0.5 0.6 0.7 TJ = −55°C 0.8 0.9 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1000 TC = 25°C VGS ≤ 10 V 0.01 ms 0.1 ms 100 100 IDS (A) 1 ms dc TJ(initial) = 25°C IPEAK (A) 10 10 ms TJ(initial) = 100°C 10 10 RDS(on) Limit Thermal Limit Package Limit 1 0.1 1 10 1 100 1E−04 1E−03 VDS (V) TIME IN AVALANCHE (s) Figure 11. Safe Operating Area Figure 12. IPEAK vs. Time in Avalanche www.onsemi.com 4 1E−02 NVMFS5C404NL 100 RqJA(t) (°C/W) 50% Duty Cycle 10 20% 10% 5% 1 2% 1% NVMFS5C404NL 650 mm2, 2 oz., Cu Single Layer Pad 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (sec) Figure 13. Thermal Characteristics DEVICE ORDERING INFORMATION Device Case Marking Package Shipping† NVMFS5C404NLT1G 506EZ 5C404L DFN5 (Pb−Free) 1500 / Tape & Reel NVMFS5C404NLWFT1G 507BA 404LWF DFN5 (Pb−Free, Wettable Flanks) 1500 / Tape & Reel NVMFS5C404NLT3G 506EZ 5C404L DFN5 (Pb−Free) 5000 / Tape & Reel NVMFS5C404NLWFT3G 507BA 404LWF DFN5 (Pb−Free, Wettable Flanks) 5000 / Tape & Reel NVMFS5C404NLAFT1G 506EZ 5C404L DFN5 (Pb−Free) 1500 / Tape & Reel NVMFS5C404NLWFAFT1G 507BA 404LWF DFN5 (Pb−Free, Wettable Flanks) 1500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN5 5x6, 1.27P (SO−8FL) CASE 506EZ ISSUE A DATE 25 AUG 2021 1 SCALE 2:1 q q GENERIC MARKING DIAGRAM* 1 XXXXXX AYWZZ XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON24855H DFN5 5x6, 1.27P (SO−8FL) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFNW5 5x6 (FULL−CUT SO8FL WF) CASE 507BA ISSUE A DATE 03 FEB 2021 q q GENERIC MARKING DIAGRAM* 1 XXXXXX AYWZZ XXXXXX A Y W ZZ = Specific Device Code *This information is generic. Please refer to = Assembly Location device data sheet for actual part marking. = Year Pb−Free indicator, “G” or microdot “ G”, = Work Week may or may not be present. Some products = Lot Traceability may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON26450H Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFNW5 5x6 (FULL−CUT SO8FL WF) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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