74ACT138
3 TO 8 LINE DECODER (INVERTING)
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HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V
LOW POWER DISSIPATION:
ICC = 4µA(MAX.) at TA=25°C
COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), V IL = 0.8V (MAX.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
IMPROVED LATCH-UP IMMUNITY
DIP
TSSOP
ORDER CODES
DESCRIPTION
The 74ACT138 is an advanced high-speed CMOS
3 TO 8 LINE DECODER (INVERTING) fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS tecnology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
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SOP
PACKAGE
TUBE
DIP
SOP
TSSOP
74ACT138B
74ACT138M
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T&R
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74ACT138MTR
74ACT138TTR
Three enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
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PIN CONNECTION AND IEC LOGIC SYMBOLS
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April 2001
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74ACT138
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
1, 2, 3
4, 5
6
15, 14, 13,
12, 11, 10, 9,
7
8
16
A, B, C
G2A, G2B
G1
Y0 to Y7
GND
VCC
NAME AND FUNCTION
Address Inputs
Enable Inputs
Enable Input
Outputs
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
ENABLE
SELECT
G2B
G2A
G1
C
B
A
Y0
Y1
Y2
Y3
Y4
X
X
H
L
L
L
L
L
L
L
L
X
H
X
L
L
L
L
L
L
L
L
L
X
X
H
H
H
H
H
H
H
H
X
X
X
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
X
X
X
L
H
L
H
L
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
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X : Don’t Care
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LOGIC DIAGRAM
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This logic diagram has not be used to estimate propagation delays
2/10
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Y5
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H
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H
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L
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Y6
Y7
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
74ACT138
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Supply Voltage
Unit
-0.5 to +7
V
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
V
DC Input Diode Current
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 50
mA
± 400
mA
VI
DC Input Voltage
VO
DC Output Voltage
IIK
ICC or IGND DC VCC or Ground Current
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
V
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Value
Unit
uc
Supply Voltage
4.5 to 5.5
VI
Input Voltage
0 to VCC
VO
Output Voltage
Top
Operating Temperature
dt/dv
1) VIN from 0.8V to 2.0V
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let
Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1)
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V
V
0 to VCC
V
-55 to 125
°C
8
ns/V
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74ACT138
DC SPECIFICATIONS
Test Condition
Symbol
VIH
Parameter
High Level Input
Voltage
VIL
Low Level Input
Voltage
VOH
High Level Output
Voltage
VOL
Low Level Output
Voltage
II
ICCT
Input Leakage Current
Max ICC/Input
TA = 25°C
VCC
(V)
4.5
5.5
4.5
VO = 0.1 V or
VCC-0.1V
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Min.
Typ.
Max.
2.0
1.5
2.0
2.0
1.5
1.5
2.0
0.8
0.8
0.8
1.5
0.8
0.8
0.8
2.0
2.0
V
5.5
4.5
IO=-50 µA
4.4
4.49
4.4
4.4
5.5
IO=-50 µA
5.4
5.49
5.4
5.4
4.5
IO=-24 mA
3.86
3.76
3.7
5.5
IO=-24 mA
4.86
4.76
4.7
4.5
IO=50 µA
0.001
0.1
0.1
0.1
5.5
IO=50 µA
0.001
0.1
0.1
0.1
4.5
IO=24 mA
0.36
0.44
5.5
IO=24 mA
0.36
0.44
5.5
VI = VCC or GND
± 0.1
±1
5.5
VI = VCC - 2.1V
VI = VCC or GND
Quiescent Supply
Current
5.5
IOLD
Dynamic Output
Current (note 1, 2)
5.5
1.5
P
e
let
VOLD = 1.65 V max
VOHD = 3.85 V min
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0.5
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0.6
4
Unit
Max.
VO = 0.1 V or
VCC-0.1V
ICC
IOHD
Value
40
0.5
±1
µA
1.6
mA
80
µA
75
50
mA
-75
-50
mA
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
(t s)
Test Condition
Symbol
Parameter
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P
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tPLH tPHL Propagation Delay
Time A, B, C to Y
tPLH tPHL Propagation Delay
Time G1 to Y
tPLH tPHL Propagation Delay
Time G2A or G2B
to Y
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(*) Voltage range is 5.0V ± 0.5V
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VCC
(V)
Value
TA = 25°C
Min.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Typ.
Max.
Max.
5.0(*)
5.0
9.0
10.0
10.5
ns
5.0(*)
5.0
8.0
9.0
9.5
ns
5.0(*)
5.5
8.5
10.0
10.5
ns
74ACT138
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
Value
TA = 25°C
VCC
(V)
CIN
Input Capacitance
5.0
CPD
Power Dissipation
Capacitance (note
1)
5.0
Min.
fIN = 10MHz
Typ.
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Max.
4
pF
60
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit)
TEST CIRCUIT
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CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
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WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
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74ACT138
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
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74ACT138
Plastic DIP-16 (0.25) MECHANICAL DATA
mm
DIM.
MIN.
a1
0.51
B
0.77
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
I
5.1
L
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3.3
Z
1.27
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0.280
0.201
0.130
0.050
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P001C
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74ACT138
SO-16 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
a1
1.75
0.1
0.068
0.2
a2
MAX.
0.004
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45 (typ.)
D
9.8
10
0.385
E
5.8
6.2
0.228
0.393
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
G
4.6
5.3
0.181
L
0.5
1.27
0.019
M
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0.62
S
8 (max.)
)
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0.244
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0.157
0.208
0.050
0.024
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P013H
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74ACT138
TSSOP16 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
A
MAX.
MIN.
TYP.
MAX.
1.1
0.433
A1
0.05
0.10
0.15
0.002
0.004
0.006
A2
0.85
0.9
0.95
0.335
0.354
0.374
b
0.19
0.30
0.0075
0.0118
c
0.09
0.20
0.0035
0.0079
D
4.9
5
5.1
0.193
0.197
E
6.25
6.4
6.5
0.246
0.252
E1
4.3
4.4
4.48
0.169
0.173
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0.65 BSC
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0.50
A
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b
A1
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4
8
0.60
0.70
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0.256
0.176
0.0256 BSC
o
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A2
)
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0.201
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0
4o
8o
0.020
0.024
0.028
K
c
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D
E1
PIN 1 IDENTIFICATION
1
9/10
74ACT138
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2001 STMicroelectronics - Printed in Italy - All Rights Reserved
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