STP18N55M5

STD18N55M5, STP18N55M5 Datasheet N-channel 550 V, 0.150 Ω typ., 16 A MDmesh M5 Power MOSFETs in a DPAK and TO-220 packages Features TAB Order code TAB 2 3 1 STD18N55M5 TO-220 DPAK 1 D(2, TAB) 2 3 STP18N55M5 VDS @ Tjmax. 600 V • Extremely low RDS(on) • • • Low gate charge and input capacitance Excellent switching performance 100% avalanche tested RDS(on)max. 0.192 Ω Package DPAK TO-220 Applications G(1) • Switching applications S(3) AM01475v1_noZen Description These devices are N-channel Power MOSFETs based on the MDmesh M5 innovative vertical process technology combined with the well-known PowerMESH horizontal layout. The resulting products offer extremely low on-resistance, making them particularly suitable for applications requiring high power and superior efficiency. Product status link STD18N55M5 STP18N55M5 DS6705 - Rev 5 - March 2021 For further information contact your local STMicroelectronics sales office. www.st.com STD18N55M5, STP18N55M5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS ID ID IDM (1) PTOT dv/dt (2) Tj Tstg Parameter Value Unit Gate-source voltage ±25 V Drain current (continuous) at TC = 25 °C 16 A Drain current (continuous) at TC = 100 °C 10 A Drain current (pulsed) 64 A Total power dissipation at TC = 25 °C 110 W Peak diode recovery voltage slope 15 V/ns -55 to 150 °C Operating junction temperature range Storage temperature range 1. Pulse width limited by safe operating area. 2. ISD ≤ 16 A, di/dt ≤ 400 A/μs; VDS peak < V(BR)DSS, VDD = 340 V. Table 2. Thermal data Symbol Parameter RthJC Thermal resistance, junction-to-case RthJA Thermal resistance, junction-to-ambient RthJB (1) Thermal resistance, junction-to-board Value DPAK TO-220 °C/W 1.14 62.5 50 Unit °C/W °C/W 1. When mounted on an 1-inch² FR-4, 2oz Cu board. Table 3. Avalanche characteristics Symbol IAR EAS DS6705 - Rev 5 Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj Max) Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Value Unit 4 A 210 mJ page 2/21 STD18N55M5, STP18N55M5 Electrical characteristics 2 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. On/off states Symbol V(BR)DSS Parameter Drain-source Breakdown voltage Test condition ID = 1 mA, VGS = 0 V Min. Typ. Max. 550 Unit V VGS = 0 V, VDS = 550 V 1 µA VGS = 0 V, VDS = 550 V, TC = 125 °C(1) 100 µA Gate body leakage current VDS = 0 V, VGS = ±25 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source on resistance VGS = 10 V, ID = 8 A 0.150 0.192 Ω Typ. Max. Unit - pF IDSS Zero gate voltage drain current IGSS 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Ciss Parameter Min. Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr) (1) Equivalent capacitance time related Co(er) (2) Test condition Equivalent capacitance energy related 1260 VDS = 100 V, f = 1 MHz, VGS = 0 V - 42 3.6 - 103 - pF - 35 - pF - 2.8 - Ω - nC VDS = 0 to 440 V, VGS = 0 V Rg Gate input resistance f = 1 MHz open drain Qg Total gate charge VDD = 440 V, ID = 8 A, Qgs Gate-source charge Qgd Gate-drain charge VGS = 0 to 10 V (see Figure 18. Test circuit for gate charge behavior) 31 - 8.3 14.2 1. Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol Test condition Min. Typ. td(v) Voltage delay time VDD = 400 V, ID = 10.5 A, 37 tr(v) Voltage rise time RG = 4.7 Ω, VGS = 10 V 7 Crossing time (see Figure 19. Test circuit for inductive load switching and diode recovery times and Figure 22. Switching time waveform) tc(off) tf(i) DS6705 - Rev 5 Parameter Current fall time - 10.3 Max. Unit - ns 8.3 page 3/21 STD18N55M5, STP18N55M5 Electrical characteristics Table 7. Source drain diode Symbol ISD ISDM Parameter Test condition Min. Typ. Source-drain current (1) VSD (2) Max. Unit 16 - Source-drain current (pulsed) Forward on voltage ISD = 16 A, VGS = 0 V trr Reverse recovery time ISD = 16 A, di/dt = 100 A/µs Qrr Reverse recovery charge IRRM Reverse recovery current VDD = 100 V (see Figure 19. Test circuit for inductive load switching and diode recovery times) trr Reverse recovery time ISD = 16 A, di/dt = 100 A/µs Qrr Reverse recovery charge IRRM Reverse recovery current VDD = 100 V, Tj = 150 °C (see Figure 19. Test circuit for inductive load switching and diode recovery times) 64 - - - 1.5 A V 244 ns 2.8 μC 23 A 295 ns 3.7 μC 25 A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%. DS6705 - Rev 5 page 4/21 STD18N55M5, STP18N55M5 Electrical characteristics curves 2.1 Electrical characteristics curves Figure 1. Safe operating area for DPAK AM16074v1 ID (A) is ) 100 100µs 1ms 1 Tj=150°C Tc=25°C Single pulse 0.1 10 1 0.1 GC20460 K 10µs DS (o n Op Lim e ra t it e io n d b in y m t h is a x are a R 10 Figure 2. Thermal impedance for DPAK 10-1 10ms 100 10-2 10-5 VDS(V) Figure 3. Safe operating area for TO-220 10-4 10-3 10-2 tp (s) 10-1 Figure 4. Thermal impedance for TO-220 AM16073v1 ) DS (o n Op Lim e ra t it e io n d b in y m t h is a x are a R is ID (A) 10 10µs 100µs 1ms 1 10ms Tj=150°C Tc=25°C Single pulse 0.1 Zth = k*RthJC δ = tp/t tp 10 1 0.1 100 t VDS(V) Figure 5. Output characterisics ID (A) Figure 6. Transfer characteristics AM16076v1 VGS=9, 10V 8V AM16077v1 ID (A) VDS=25V 35 30 30 25 7V 20 20 15 10 10 5 6V 0 DS6705 - Rev 5 0 5 10 15 20 25 VDS(V) 0 3 4 5 6 7 8 9 VGS(V) page 5/21 STD18N55M5, STP18N55M5 Electrical characteristics curves Figure 7. Gate charge vs gate-source voltage AM16078v1 VDS VGS (V) VDS 12 (V) VDD=440V ID=8A 8 300 250 6 200 4 150 100 2 50 5 10 15 20 25 VGS =10V 400 350 0 AM16079v1 R DS (on) (Ω) 0.18 10 0 Figure 8. Static drain-source on resistance 30 0 35 Qg (nC) Figure 9. Capacitance variations 0.16 0.15 0.14 0.13 0.12 0 2 6 4 8 10 12 14 ID(A) Figure 10. Output capacitance stored energy AM16080v1 C (pF) 0.17 AM16081v1 Eoss (µJ) 5 10000 Ciss 1000 4 3 100 Coss 10 2 1 Crss 1 0.1 1 10 100 VDS(V) Figure 11. Normalized gate threshold voltage vs temperature AM05459v1 VGS (th) (norm) 1.10 VDS = VGS ID = 250 µA 0 0 200 100 300 400 500 VDS(V) Figure 12. Normalized on-resistance vs temperature AM05460v1 RDS(on) (norm) 2.1 VGS = 10 V ID = 8 A 1.9 1.7 1.00 1.5 1.3 0.90 1.1 0.9 0.80 0.7 0.70 -50 -25 DS6705 - Rev 5 0 25 50 75 100 TJ (°C) 0.5 -50 -25 0 25 50 75 100 TJ(°C) page 6/21 STD18N55M5, STP18N55M5 Electrical characteristics curves Figure 13. Drain-source diode forward characteristics AM05461v1 VS D (V) TJ =-50°C Figure 14. Normalized V(BR)DSS vs temperature AM10399v1 VDS 1.08 1.2 ID = 1mA 1.06 1.0 1.04 0.8 1.02 TJ =25°C 1.00 0.6 TJ =150°C 0.98 0.4 0.96 0.2 0 0.94 0 10 20 30 40 0.92 -50 -25 50 IS D(A) 0 25 50 75 100 TJ(°C) Figure 15. Switching energy vs gate resistance E (µJ) AM16082v1 Eon ID=10.5A VDD=440V VGS =10V 150 100 Eoff 50 0 0 10 25 30 35 40 R G (Ω) * Eon including reverse recovery of a SiC diode DS6705 - Rev 5 page 7/21 STD18N55M5, STP18N55M5 Test circuits 3 Test circuits Figure 17. Test circuit for gate charge behavior Figure 16. Test circuit for resistive load switching times VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 18. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 19. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 20. Unclamped inductive waveform Figure 21. Switching time waveform ID V(BR)DSS VDS 90%ID 90%VDS VD IDM VGS 90%VGS ID VDD VDD 10%VDS 10%ID tr VDS td(V) AM01472v1 DS6705 - Rev 5 tf ID tc(off) AM05540v2 page 8/21 STD18N55M5, STP18N55M5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 DPAK (TO-252) type A2 package information Figure 22. DPAK (TO-252) type A2 package outline 0068772_type-A2_rev30 DS6705 - Rev 5 page 9/21 STD18N55M5, STP18N55M5 DPAK (TO-252) type A2 package information Table 8. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS6705 - Rev 5 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 10/21 STD18N55M5, STP18N55M5 DPAK (TO-252) type C2 package information 4.2 DPAK (TO-252) type C2 package information Figure 23. DPAK (TO-252) type C2 package outline 0068772_type-C2_rev30 DS6705 - Rev 5 page 11/21 STD18N55M5, STP18N55M5 DPAK (TO-252) type C2 package information Table 9. DPAK (TO-252) type C2 mechanical data Dim. mm Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.10 E 6.50 E1 5.20 e 2.186 2.286 2.386 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 6.20 5.60 6.60 6.70 5.50 0.90 1.25 0.51 BSC 0.60 L6 DS6705 - Rev 5 6.10 5.46 2.90 REF L3 L4 5.33 0.80 1.00 1.80 BSC θ1 5° 7° 9° θ2 5° 7° 9° V2 0° 8° page 12/21 STD18N55M5, STP18N55M5 DPAK (TO-252) type C2 package information Figure 24. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_30 DS6705 - Rev 5 page 13/21 STD18N55M5, STP18N55M5 DPAK (TO-252) packing information 4.3 DPAK (TO-252) packing information Figure 25. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS6705 - Rev 5 page 14/21 STD18N55M5, STP18N55M5 DPAK (TO-252) packing information Figure 26. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS6705 - Rev 5 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 15/21 STD18N55M5, STP18N55M5 TO-220 type A package information 4.4 TO-220 type A package information Figure 27. TO-220 type A package outline 0015988_typeA_Rev_23 DS6705 - Rev 5 page 16/21 STD18N55M5, STP18N55M5 TO-220 type A package information Table 11. TO-220 type A package mechanical data Dim. mm Min. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.55 c 0.48 0.70 D 15.25 15.75 D1 1.27 E 10.00 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13.00 14.00 L1 3.50 3.93 L20 16.40 L30 28.90 øP 3.75 3.85 Q 2.65 2.95 Slug flatness DS6705 - Rev 5 Typ. 0.03 0.10 page 17/21 STD18N55M5, STP18N55M5 Ordering information 5 Ordering information Table 12. Order codes Order code STD18N55M5 STP18N55M5 DS6705 - Rev 5 Marking 18N55M5 Package Packing DPAK Tape and reel TO-220 Tube page 18/21 STD18N55M5, STP18N55M5 Revision history Table 13. Document revision history Date Version 09-Feb-2010 1 04-Mar-2011 2 Changes First release. – Document status promoted from preliminary data to datasheet; – Added new package, mechanical data: D²PAK. – Updated: title on the cover page and RDS(on) values. – Modified: EAS value and note 3 in Table 2 – Modified: RDS(on) value in Table 4, typical values in Table 5 and 7 – Updated: the entire Table 5 22-Nov-2013 3 – Added: Section 2.1: Electrical characteristics (curves) – Updated: Section 4: Package mechanical data and Section 5: Packaging mechanical data – Updated: Figure 11 and 18 – Minor text changes. The part numbers STB18N55M5 and STF18N55M5 have been moved to a separate datasheet. 03-Aug-2018 4 Removed maturity status indication from cover page. The document status is production data. Updated title in cover page, Section 1 Electrical ratings, Section 2 Electrical characteristics and Section 4 Package information. Minor text changes. Updated title on Figure 12. Normalized gate threshold voltage vs temperature and Figure 13. Normalized on-resistance vs temperature. 24-Mar-2020 5 Updated Section 4 Package information. Minor text changes. DS6705 - Rev 5 page 19/21 STD18N55M5, STP18N55M5 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 4.1 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 DPAK (TO-252) type C2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 TO-220 type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 DS6705 - Rev 5 page 20/21 STD18N55M5, STP18N55M5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS6705 - Rev 5 page 21/21