STP85NF3LL

N-CHANNEL 30V - 0.006Ω - 85A TO-220/I2PAK LOW GATE CHARGE STripFET™ POWER MOSFET PRELIMINARY DATA TYPE STP85NF3LL STB85NF3LL-1 s s s s STP85NF3LL STB85NF3LL-1 VDSS 30 V 30 V RDS(on) < 0.008 Ω < 0.008 Ω ID 85 A 85 A TYPICAL RDS(on) = 0.0075 Ω (@4.5V) OPTIMAL RDS(ON) x Qg TRADE-OFF @4.5V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED 1 3 2 3 12 I2PAK DESCRIPTION This application specific Power MOSFET is the third genaration of STMicroelectronics unique “ Single Feature Size” strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance. TO-220 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS s SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM (q) PTOT Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuos) at TC = 25°C Drain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Storage Temperature Max. Operating Junction Temperature Value 30 30 ± 15 85 60 340 110 0.73 –65 to 175 175 Unit V V V A A A W W/°C °C °C (q) Pulse width limited by safe operating area March 2001 1/9 STP85NF3LL/STB85NF3LL-1 THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 1.36 62.5 300 °C/W °C/W °C ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 µA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 °C VGS = ± 15V Min. 30 1 10 ±100 Typ. Max. Unit V µA µA nA ON (1) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250µA VGS = 10V, ID = 40 A VGS = 4.5V, ID = 40 A Min. 1 0.006 0.0075 0.008 0.0095 Typ. Max. Unit V Ω Ω DYNAMIC Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max, ID = 40 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 30 2210 635 138 Max. Unit S pF pF pF 2/9 STP85NF3LL/STB85NF3LL-1 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 15V, ID = 30A RG = 4.7Ω VGS = 4.5V (see test circuit, Figure 3) VDD = 24V, ID = 60A, VGS = 4.5V Min. Typ. 22 130 30 9 12.5 40 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf td(off) tf tc Parameter Turn-off-Delay Time Fall Time Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 15V, ID = 30A, RG = 4.7Ω, VGS = 4.5V (see test circuit, Figure 3) Vclamp =24V, ID =30A RG = 4.7Ω, VGS = 4.5V (see test circuit, Figure 5) Min. Typ. 36.5 36.5 32 23 40 Max. Unit ns ns ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 85A, VGS = 0 ISD = 85A, di/dt = 100A/µs, VDD = 15V, Tj = 150°C (see test circuit, Figure 5) 65 105 3.4 Test Conditions Min. Typ. Max. 85 340 1.3 Unit A A V ns nC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedence 3/9 STP85NF3LL/STB85NF3LL-1 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/9 STP85NF3LL/STB85NF3LL-1 Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STP85NF3LL/STB85NF3LL-1 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STP85NF3LL/STB85NF3LL-1 TO-220 MECHANICAL DATA DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 inch TYP. MAX. 0.181 0.051 0.107 A C D1 L2 D F1 G1 E Dia. L5 L7 L6 L4 P011C L9 F2 F G H2 7/9 STP85NF3LL/STB85NF3LL-1 TO-262 (I2PAK) MECHANICAL DATA mm MIN. A A1 B B2 C C2 D e E L L1 L2 4.4 2.49 0.7 1.14 0.45 1.23 8.95 2.4 10 13.1 3.48 1.27 TYP. MAX. 4.6 2.69 0.93 1.7 0.6 1.36 9.35 2.7 10.4 13.6 3.78 1.4 MIN. 0.173 0.098 0.027 0.044 0.017 0.048 0.352 0.094 0.393 0.515 0.137 0.050 inch TYP. MAX. 0.181 0.106 0.036 0.067 0.023 0.053 0.368 0.106 0.409 0.531 0.149 0.055 DIM. A C2 B2 B E L1 L2 D L P011P5/E 8/9 e A1 C STP85NF3LL/STB85NF3LL-1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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