SQS401EN
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Vishay Siliconix
Automotive P-Channel 40 V (D-S) 175 °C MOSFET
FEATURES
PowerPAK® 1212-8 Single
• TrenchFET® power MOSFET
D
D 8
D 7
D 6
5
• AEC-Q101 qualified d
• 100 % Rg and UIS tested
3.
• Material categorization:
for definitions of compliance please see
www.vishay.com/doc?99912
3
1
2 S
3 S
4 S
G
Bottom View
m
m
1
3.3
mm
Top View
S
PRODUCT SUMMARY
G
VDS (V)
-40
RDS(on) (Ω) at VGS = -10 V
0.029
RDS(on) (Ω) at VGS = -4.5 V
0.047
ID (A)
P-Channel MOSFET
-16
Configuration
D
Single
Marking Code: Q005
ORDERING INFORMATION
Package
PowerPAK 1212-8
Lead (Pb)-free and halogen-free
SQS401EN
(for detailed order number please see www.vishay.com/doc?79771)
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
-40
Gate-source voltage
VGS
± 20
TC = 25 °C
Continuous drain current a
Continuous source current (diode
TC = 125 °C
conduction) a
Pulsed drain current b
Single pulse avalanche current
Single pulse avalanche energy
Maximum power dissipation b
L = 0.1 mH
TC = 25 °C
TC = 125 °C
Operating junction and storage temperature range
ID
-16
IS
-16
-64
IAS
-26
EAS
33.8
TJ, Tstg
Soldering recommendations (peak temperature) e, f
V
-16
IDM
PD
UNIT
62.5
20
-55 to +175
260
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
PARAMETER
Junction to ambient
Junction to case (drain)
PCB Mount c
SYMBOL
LIMIT
RthJA
81
RthJC
2.4
UNIT
°C/W
Notes
a. Package limited
b. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %
c. When mounted on 1" square PCB (FR4 material)
d. Parametric verification ongoing
e. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection
f. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components
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SPECIFICATIONS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
On-State Drain Current a
Drain-Source On-State Resistance a
Forward
Transconductance b
VDS
VGS = 0, ID = -250 μA
-40
-
-
VGS(th)
VDS = VGS, ID = -250 μA
-1.5
-2.0
-2.5
VDS = 0 V, VGS = ± 20 V
IGSS
IDSS
ID(on)
RDS(on)
gfs
-
-
± 100
VGS = 0 V
VDS = -40 V
-
-
-1
VGS = 0 V
VDS = -40 V, TJ = 125 °C
-
-
-50
VGS = 0 V
VDS = -40 V, TJ = 175 °C
-
-
-150
VGS = -10 V
VDS ≥ 5 V
-20
-
-
VGS = -10 V
ID = -12 A
-
0.020
0.029
VGS = -10 V
ID = -12 A, TJ = 125 °C
-
0.030
0.043
VGS = -10 V
ID = -12 A, TJ = 175 °C
-
0.040
0.051
VGS = -4.5 V
ID = -9 A
-
0.035
0.047
-
12
-
-
1565
1875
-
245
295
-
170
205
VDS = -15 V, ID = -7 A
V
nA
μA
A
Ω
S
Dynamic b
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge c
Qg
Gate-Source Charge c
Qgs
Gate-Drain Charge c
Qgd
Gate Resistance
Turn-On Delay Time c
Rise Time c
Turn-Off Delay Time c
Fall Time c
Rg
VGS = 0 V
VGS = -4.5 V
VDS = -20 V, f = 1 MHz
VDS = -20 V, ID = -9.3 A
f = 1 MHz
td(on)
tr
td(off)
VDD = -20 V, RL = 14.2 Ω
ID ≅ -1.4 A, VGEN = -10 V, Rg = 1 Ω
tf
Source-Drain Diode Ratings and Characteristic
-
17.7
21.2
-
5.6
6.6
-
8.1
9.7
1.1
2.1
4.1
-
11
14
-
10
13
-
36.5
44
-
10.2
13
pF
nC
Ω
ns
b
Pulsed Current a
ISM
Forward Voltage
VSD
IF = -8.8 A, VGS = 0
-
-
-64
A
-
-0.8
-1.1
V
Notes
g. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
h. Guaranteed by design, not subject to production testing.
i. Independent of operating temperature.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S21-1246-Rev. D, 10-Jan-2022
Document Number: 65529
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TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
30
30
VGS = 10 V thru 5 V
24
I D - Drain Current (A)
I D - Drain Current (A)
24
VGS = 4 V
18
12
18
12
TC = 25 °C
6
6
TC = 125 °C
VGS = 3 V
TC = - 55 °C
0
0
0
1
2
3
4
5
VDS - Drain-to-Source Voltage (V)
0
6
1
3
4
5
Transfer Characteristics
Output Characteristics
0.10
30
24
TC = - 55 °C
R DS(on) - On-Resistance (Ω)
g fs - Transconductance (S)
2
VGS - Gate-to-Source Voltage (V)
TC = 25 °C
18
12
TC = 125 °C
6
0.08
0.06
VGS = 4.5 V
0.04
VGS = 10 V
0.02
0.00
0
0
4
8
12
ID - Drain Current (A)
16
0
20
6
12
18
24
30
ID - Drain Current (A)
Transconductance
On-Resistance vs. Drain Current
6
2500
VGS - Gate-to-Source Voltage (V)
VDS = 20 V
ID = 9.3 A
C - Capacitance (pF)
2000
Ciss
1500
1000
Coss
500
5
4
3
2
1
Crss
0
0
0
10
20
30
VDS - Drain-to-Source Voltage (V)
Capacitance
S21-1246-Rev. D, 10-Jan-2022
40
0
5
10
15
20
25
Qg - Total Gate Charge (nC)
Gate Charge
Document Number: 65529
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TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
100
ID = 11 A
1.6
VGS = 10 V
10
I S - Source Current (A)
R DS(on) - On-Resistance (Normalized)
1.8
1.4
VGS = 4.5 V
1.2
1.0
TJ = 150 °C
1
0.1
0.01
0.8
0.6
- 50
- 25
0
25
50
75 100 125
TJ - Junction Temperature (°C)
150
175
0.001
0.0
0.20
0.8
VGS(th) Variance (V)
1.1
0.15
0.10
TJ = 150 °C
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage (V)
0.6
0.8
1.0
1.2
9
ID = 250 µA
0.5
ID = 5 mA
0.2
- 0.1
TJ = 25 °C
0.00
0.4
Source Drain Diode Forward Voltage
0.25
0.05
0.2
VSD - Source-to-Drain Voltage (V)
On-Resistance vs. Junction Temperature
R DS(on) - On-Resistance (Ω)
TJ = 25 °C
10
- 0.4
- 50
- 25
0
On-Resistance vs. Gate-to-Source Voltage
25
50
75 100 125
TJ - Temperature (°C)
150
175
Threshold Voltage
VDS - Drain-to-Source Voltage (V)
- 40
ID = 1 mA
- 42
- 44
- 46
- 48
- 50
- 50
- 25
0
25
50
75 100 125
TJ - Junction Temperature (°C)
150
175
Drain Source Breakdown vs. Junction Temperature
S21-1246-Rev. D, 10-Jan-2022
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THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
IDM Limited
100
ID - Drain Current (A)
ID Limited
100 μs
10 Limited by R
DS(on)*
1 ms
10 ms
100 ms, 1 s,
10 s, DC
1
BVDSS Limited
0.1
TC = 25 °C
Single Pulse
0.01
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
Notes:
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 81 °C/W
0.02
3. TJM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10 -4
10 -3
10 -2
10 -1
1
10
100
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
S21-1246-Rev. D, 10-Jan-2022
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THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
Single Pulse
0.05
0.02
0.01
10-4
10-3
10-2
Square Wave Pulse Duration (s)
10-1
1
Normalized Thermal Transient Impedance, Junction-to-Case
Note
• The characteristics shown in the two graphs
- Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C)
- Normalized Transient Thermal Impedance Junction-to-Case (25 °C)
are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single
pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part
mounted on printed circuit board - FR4, size 1" x 1" x 0.062", double sided with 2 oz. copper, 100 % on both sides. The part capabilities
can widely vary depending on actual application parameters and operating conditions.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65529.
S21-1246-Rev. D, 10-Jan-2022
Document Number: 65529
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Package Information
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Vishay Siliconix
D4
PowerPAK® 1212-8, (Single / Dual)
W
H
E2
E4
L
K
M
θ
e
1
Z
D5
D
D2
2
2
D1
8
1
5
4
θ
4
b
3
L1
E3
A1
Backside view of single pad
H
2
E1
E
Detail Z
L
K
E2
E4
D2 D3(2x) D4
c
A
H
1
D1
2
K1
Notes
1. Inch will govern
2 Dimensions exclusive of mold gate burrs
3. Dimensions exclusive of mold flash and cutting burrs
D2
3
4
b
θ
D5
θ
E3
Backside view of dual pad
DIM.
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.97
1.04
1.12
0.038
0.041
0.044
A1
0.00
-
0.05
0.000
-
0.002
b
0.23
0.30
0.41
0.009
0.012
0.016
c
0.23
0.28
0.33
0.009
0.011
0.013
D
3.20
3.30
3.40
0.126
0.130
0.134
D1
2.95
3.05
3.15
0.116
0.120
0.124
D2
1.98
2.11
2.24
0.078
0.083
0.088
D3
0.48
-
0.89
0.019
-
0.035
D4
0.47 typ.
D5
2.3 typ.
0.0185 typ
0.090 typ
E
3.20
3.30
3.40
0.126
0.130
0.134
E1
2.95
3.05
3.15
0.116
0.120
0.124
E2
1.47
1.60
1.73
0.058
0.063
0.068
E3
1.75
1.85
1.98
0.069
0.073
0.078
E4
0.034 typ.
0.013 typ.
e
0.65 BSC
0.026 BSC
K
0.86 typ.
K1
0.35
-
0.034 typ.
-
0.014
-
-
H
0.30
0.41
0.51
0.012
0.016
0.020
L
0.30
0.43
0.56
0.012
0.017
0.022
L1
0.06
0.13
0.20
0.002
0.005
0.008
0°
-
12°
0°
-
12°
W
0.15
0.25
0.36
0.006
0.010
0.014
M
0.125 typ.
0.005 typ.
ECN: S16-2667-Rev. M, 09-Jan-17
DWG: 5882
Revison: 09-Jan-17
Document Number: 71656
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AN822
Vishay Siliconix
PowerPAK® 1212 Mounting and Thermal Considerations
Johnson Zhao
MOSFETs for switching applications are now available
with die on resistances around 1 mΩ and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvious that degradation of a high performance die by the
package is undesirable. PowerPAK is a new package
technology that addresses these issues. The PowerPAK
1212-8 provides ultra-low thermal impedance in a
small package that is ideal for space-constrained
applications. In this application note, the PowerPAK
1212-8’s construction is described. Following this,
mounting information is presented. Finally, thermal
and electrical performance is discussed.
THE PowerPAK PACKAGE
The PowerPAK 1212-8 package (Figure 1) is a derivative of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
die attach pad is exposed to provide a direct, low resistance thermal path to the substrate the device is
mounted on. The PowerPAK 1212-8 thus translates
the benefits of the PowerPAK SO-8 into a smaller
package, with the same level of thermal performance.
(Please refer to application note “PowerPAK SO-8
Mounting and Thermal Considerations.”)
The PowerPAK 1212-8 has a footprint area comparable to TSOP-6. It is over 40 % smaller than standard
TSSOP-8. Its die capacity is more than twice the size
of the standard TSOP-6’s. It has thermal performance
an order of magnitude better than the SO-8, and 20
times better than TSSOP-8. Its thermal performance is
better than all current SMT packages in the market. It
will take the advantage of any PC board heat sink
capability. Bringing the junction temperature down also
increases the die efficiency by around 20 % compared
with TSSOP-8. For applications where bigger packages are typically required solely for thermal consideration, the PowerPAK 1212-8 is a good option.
Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
space constraints.
PowerPAK 1212 SINGLE MOUNTING
To take the advantage of the single PowerPAK 1212-8’s
thermal performance see Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 single in the index of this
document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance.
Figure 1. PowerPAK 1212 Devices
Document Number 71681
03-Mar-06
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Vishay Siliconix
PowerPAK 1212 DUAL
To take the advantage of the dual PowerPAK 1212-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the PowerPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance.
ture profile used, and the temperatures and time
duration, are shown in Figures 2 and 3. For the lead
(Pb)-free solder profile, see http://www.vishay.com/
doc?73257.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow tempera-
Ramp-Up Rate
+ 6 °C /Second Maximum
Temperature at 155 ± 15 °C
120 Seconds Maximum
Temperature Above 180 °C
70 - 180 Seconds
Maximum Temperature
240 + 5/- 0 °C
Time at Maximum Temperature
20 - 40 Seconds
Ramp-Down Rate
+ 6 °C/Second Maximum
Figure 2. Solder Reflow Temperature Profile
10 s (max)
210 - 220 °C
3 ° C/s (max)
4 ° C/s (max)
183 °C
140 - 170 °C
50 s (max)
3° C/s (max)
60 s (min)
Pre-Heating Zone
Reflow Zone
Maximum peak temperature at 240 °C is allowed.
Figure 3. Solder Reflow Temperatures and Time Durations
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Document Number 71681
03-Mar-06
AN822
Vishay Siliconix
TABLE 1: EQIVALENT STEADY STATE PERFORMANCE
Package
SO-8
TSSOP-8
TSOP-8
PPAK 1212
PPAK SO-8
Configuration
Single
Dual
Single
Dual
Single
Dual
Single
Dual
Single
Dual
Thermal Resiatance RthJC(C/W)
20
40
52
83
40
90
2.4
5.5
1.8
5.5
PowerPAK 1212
Standard SO-8
49.8 °C
2.4 °C/W
Standard TSSOP-8
85 °C
20 °C/W
TSOP-6
149 °C
52 °C/W
125 °C
40 °C/W
PC Board at 45 °C
Figure 4. Temperature of Devices on a PC Board
THERMAL PERFORMANCE
Introduction
Spreading Copper
A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθjc, or the
junction to- foot thermal resistance, Rθjf. This parameter
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the PowerPAK 1212-8, PowerPAK SO-8,
standard TSSOP-8 and SO-8 equivalent steady state
performance.
By minimizing the junction-to-foot thermal resistance, the
MOSFET die temperature is very close to the temperature of the PC board. Consider four devices mounted on
a PC board with a board temperature of 45 °C (Figure 4).
Suppose each device is dissipating 2 W. Using the junction-to-foot thermal resistance characteristics of the
PowerPAK 1212-8 and the other SMT packages, die
temperatures are determined to be 49.8 °C for the PowerPAK 1212-8, 85 °C for the standard SO-8, 149 °C for
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the PowerPAK 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on rDS(ON) whereas a rise
of over 40 °C will cause an increase in rDS(ON) as high
as 20 %.
Designers add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It
is helpful to have some information about the thermal
performance for a given area of spreading copper.
Figure 5 and Figure 6 show the thermal resistance of a
PowerPAK 1212-8 single and dual devices mounted on
a 2-in. x 2-in., four-layer FR-4 PC boards. The two internal layers and the backside layer are solid copper. The
internal layers were chosen as solid copper to model the
large power and ground planes common in many applications. The top layer was cut back to a smaller area and
at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an
area above 0.2 to 0.3 square inches of spreading copper
gives no additional thermal performance improvement.
A subsequent experiment was run where the copper on
the back-side was reduced, first to 50 % in stripes to
mimic circuit traces, and then totally removed. No significant effect was observed.
Document Number 71681
03-Mar-06
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AN822
Vishay Siliconix
130
105
Spreading Copper (sq. in.)
Spreading Copper (sq. in.)
120
95
110
100
RthJ A (°C/W)
RthJA (°C/W)
85
75
65
90
80
50 %
100 %
70
100 %
55
0%
60
50 %
0%
50
45
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
Figure 5. Spreading Copper - Si7401DN
Figure 6. Spreading Copper - Junction-to-Ambient Performance
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK
1212-8 uses the same packaging technology and has
been shown to have the same level of thermal performance while having a footprint that is more than 40 %
smaller than the standard TSSOP-8.
Recommended PowerPAK 1212-8 land patterns are
provided to aid in PC board layout for designs using this
new package.
The PowerPAK 1212-8 combines small size with attractive thermal characteristics. By minimizing the thermal
rise above the board temperature, PowerPAK simplifies
thermal design considerations, allows the device to run
cooler, keeps rDS(ON) low, and permits the device to
handle more current than a same- or larger-size MOSFET die in the standard TSSOP-8 or SO-8 packages.
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4
Document Number 71681
03-Mar-06
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single
0.152
(3.860)
0.039
0.068
(0.990)
(1.725)
0.010
(0.255)
(2.390)
0.094
0.088
(2.235)
0.016
(0.405)
0.026
(0.660)
0.025
0.030
(0.635)
(0.760)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Return to Index
APPLICATION NOTE
Document Number: 72597
Revision: 21-Jan-08
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