SLG59M1558V

 SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch General Description Pin Configuration Features • One 1.0 A MOSFET • Ultra Low Quiescent Current • Low RDSON • 28.5 mΩ at VIN = 5.0 V • 36.4 mΩ at VIN = 3.3 V • 44.3 mΩ at VIN = 2.5 V • 60.8 mΩ at VIN = 1.8 V • 77.6 mΩ at VIN = 1.5 V • VIN = 1.5 V to 5.5 V • Pb-Free / Halogen-Free / RoHS compliant • STDFN 4L, 1.0 x 1.0 x 0.55 mm ON 1 VIN 2 SLG59M1558V The SLG59M1558V is designed for load switching applications with ultra low quiescent current. The part comes with one 28.5 mΩ, 1.0 A rated P-channel MOSFET controlled by a single ON control pin. The product is packaged in an ultra-small 1.0 mm x 1.0 mm package. 4 GND 3 VOUT 4-pin STDFN (Top View) Applications • Notebook Power Rail Switching • Tablet Power Rail Switching • Smartphone Power Rail Switching Block Diagram 1.0 A VIN VOUT CLOAD CIN ON Datasheet CFR0011-120-01 Fixed Slew Rate Control Revision 1.07 Page 1 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch Pin Description Pin # Pin Name Type Pin Description 1 ON Input A low-to-high transition on this pin initiates the operation of the SLG59M1558V. ON is an asserted HIGH, level-sensitive CMOS input with ON_VIL < 0.3 V and ON_VIH > 0.85 V. As the ON pin input circuit does not have an internal pull-down resistor, connect this pin to a general-purpose output (GPO) of a microcontroller, an application processor, or a system controller – do not allow this pin to be open-circuited. 2 VIN MOSFET Input terminal connection of the power MOSFET. Connect a 10 µF (or larger) low-ESR capacitor from this pin to ground. Capacitors used at VIN should be rated at 10 V or higher. 3 VOUT MOSFET Output terminal connection of the power MOSFET. Capacitors used at VOUT should be rated at 10 V or higher. 4 GND GND Ground connection. Connect this pin to system analog or power ground plane. Ordering Information Part Number Type Production Flow SLG59M1558V STDFN 4L Industrial, -40 °C to 85 °C SLG59M1558VTR STDFN 4L (Tape and Reel) Industrial, -40 °C to 85 °C Datasheet CFR0011-120-01 Revision 1.07 Page 2 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch Absolute Maximum Ratings Parameter Description Conditions Min. Typ. Max. Unit -- -- 6 V VIN Load Switch Input Voltage TS Storage Temperature -65 -- 140 °C TJ Junction Temperature -40 -- 150 °C 2000 -- -- V ESDHBM MSL θJA WDIS MOSFET IDSPEAK ESD Protection Human Body Model Moisture Sensitivity Level Thermal Resistance 1 1.0 x 1.0 mm, 4L STDFN; Determined using 1 in2, 2 oz. copper pads under each VIN and VOUT terminals and FR4 pcb material Package Power Dissipation Peak Current from VIN to VOUT For no more than 1 ms with 1% duty cycle -- 122 -- °C/W -- -- 0.5 W -- -- 1.5 A Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Electrical Characteristics TA = -40 °C to 85 °C unless otherwise noted. Typical values are at TA = 25 °C Parameter Description Conditions VIN Load Switch Input Voltage -40 °C to 85 °C IIN Load Switch Input Current (PIN 2) IFET_OFF MOSFET OFF Leakage Current ION_LKG ON Pin Input Leakage RDSON RDSON ON Resistance, TA = 25 °C ON Resistance, TA = 85 °C MOSFET IDS Current from VIN to VOUT Datasheet CFR0011-120-01 Min. Typ. Max. Unit 1.5 -- 5.5 V when OFF, VIN = 5.5 V, No load -- 0.02 1 μA when ON, ON = VIN, No load -- 0.05 0.5 μA ON = LOW; VIN = 5.5 V -- 0.05 1 μA -- -- 0.1 μA VIN = 5.5 V, IDS = 100 mA -- 28.5 32.0 mΩ VIN = 3.3 V, IDS = 100 mA -- 36.4 40.0 mΩ VIN = 2.5 V, IDS = 100 mA -- 44.3 49.0 mΩ VIN = 1.8 V, IDS = 100 mA -- 60.8 65.0 mΩ VIN = 1.5 V, IDS = 100 mA -- 77.6 82.0 mΩ VIN = 5.5 V, IDS = 100 mA -- 34.0 36.0 mΩ VIN = 3.3 V, IDS = 100 mA -- 43.8 46.0 mΩ VIN = 2.5 V, IDS = 100 mA -- 53.3 56.0 mΩ VIN = 1.8 V, IDS = 100 mA -- 72.2 76.0 mΩ VIN = 1.5 V, IDS = 100 mA -- 90.7 94.0 mΩ Continuous -- -- 1.0 A Revision 1.07 Page 3 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch Electrical Characteristics (continued) TA = -40 °C to 85 °C unless otherwise noted. Typical values are at TA = 25 °C Parameter TON_Delay TTotal_ON TVOUT(R) Description ON Delay Time Total Turn ON Time VOUT Rise Time Min. Typ. Max. Unit 50% ON to VOUT Ramp Start; VIN = 5 V, CLOAD = 0.1 μF, RLOAD = 10 Ω Conditions 10 15 27 μs 50% ON to VOUT Ramp Start; VIN = 3.3 V, CLOAD = 0.1 μF, RLOAD = 10 Ω 17 31 40 μs 50% ON to VOUT Ramp Start; VIN = 1.5 V, CLOAD = 0.1 μF, RLOAD = 10 Ω 44 69 96 μs 50% ON to 90% VOUT; VIN = 5.0 V, CLOAD = 0.1 μF, RLOAD = 10 Ω 114 122 134 μs 50% ON to 90% VOUT; VIN = 3.3 V, CLOAD = 0.1 μF, RLOAD = 10 Ω 146 156 176 μs 50% ON to 90% VOUT; VIN = 1.5 V, CLOAD = 0.1 μF, RLOAD = 10 Ω 292 332 399 μs 10% VOUT to 90% VOUT; VIN = 5.0 V, CLOAD = 0.1 μF, RLOAD = 10 Ω 92 97 107 μs 10% VOUT to 90% VOUT; VIN = 3.3 V, CLOAD = 0.1 μF, RLOAD = 10 Ω 116 120 131 μs 10% VOUT to 90% VOUT; VIN = 1.5 V, CLOAD = 0.1 μF, RLOAD = 10 Ω 228 253 296 μs ON_VIH High Input Voltage on ON pin 0.85 -- VIN V ON_VIL Low Input Voltage on ON pin -0.3 0 0.3 V 6.2 6.5 7.0 μs TOFF_Delay Datasheet CFR0011-120-01 OFF Delay Time 50% ON to VOUT Fall Start, VIN = 5 V, RLOAD = 10 Ω, no CLOAD Revision 1.07 Page 4 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch VIN vs. Max IDS, Safe Operation Area 8 7 6 5 VIN (V) 4 SOA Boundary 3 2 1 0 0 0.5 1 1.5 2 2.5 Max IDS (A) TTotal_ON, TON_Delay and Rise Time Measurement ON* 50% ON 50% ON TOFF_Delay 90% VOUT VOUT 90% VOUT TON_Delay 10% VOUT 10% VOUT TVOUT(R) TFALL TTotal_ON *Rise and Fall Times of the ON Signal are 100 ns Datasheet CFR0011-120-01 Revision 1.07 Page 5 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch SLG59M1558V Power-Up/Power-Down Sequence Considerations A nominal power-up sequence is to apply VIN and toggle the ON pin LOW-to-HIGH after VIN is at least 90% of its final value. A nominal power-down sequence is the power-up sequence in reverse order. If VIN ramp is too fast, a voltage glitch may appear on the output pin at VOUT. To prevent glitches at the output, it is recommended to connect at least 0.1uF capacitor from the VOUT pin to GND and to keep the VIN ramp time higher than 2 ms. Power Dissipation Considerations The junction temperature of the SLG59M1558V depends on factors such as board layout, ambient temperature, external air flow over the package, load current, and the RDSON generated voltage drop across each power MOSFET. While the primary contributor to the increase in the junction temperature of the SLG59M1558V is the power dissipation of its power MOSFETs, its power dissipation and the junction temperature in nominal operating mode can be calculated using the following equations: PDTOTAL = RDSON x IDS2 where: PDTOTAL = Total package power dissipation, in Watts (W) RDSON= Power MOSFET ON resistance, in Ohms (Ω) IDS = Output current, in Amps (A) and TJ = PDTOTAL x θJA + TA where: TJ = Die junction temperature, in Celsius degrees (°C) θJA = Package thermal resistance, in Celsius degrees per Watt (°C/W) – highly dependent on pcb layout TA = Ambient temperature, in Celsius degrees (°C) In nominal operating mode, the SLG59M1558V’s power dissipation can also be calculated by taking into account the voltage drop across the load switch (VIN - VOUT) and the magnitude of the switch’s output current (IDS): PDTOTAL = (VIN - VOUT) x IDS or PDTOTAL = (VIN – (RLOAD x IDS)) x IDS where: PDTOTAL = Total package power dissipation, in Watts (W) VIN = Switch input Voltage, in Volts (V) RLOAD = Output Load Resistance, in Ohms (Ω) IDS = Switch output current, in Amps (A) VOUT = Switch output voltage, or RLOAD x IDS Datasheet CFR0011-120-01 Revision 1.07 Page 6 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch SLG59M1558V Layout Suggestion Note: All dimensions shown in micrometers (µm) Datasheet CFR0011-120-01 Revision 1.07 Page 7 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch Layout Guidelines: 1. Since the VIN and VOUT pins dissipate most of the heat generated during high-load current operation, it is highly recommended to make power traces as short, direct, and wide as possible. A good practice is to make power traces with an absolute minimum widths of 15 mils (0.381 mm) per Ampere. A representative layout, shown in Figure 1, illustrates proper techniques for heat to transfer as efficiently as possible out of the device; 2. To minimize the effects of parasitic trace inductance on normal operation, it is recommended to connect input CIN and output CLOAD low-ESR capacitors as close as possible to the SLG59M1558V's VIN and VOUT pins; 3. The GND pin should be connected to system analog or power ground plane. 4. 2 oz. copper is recommended for high current operation. SLG59M1558V Evaluation Board: А GreenFET Evaluation Board for SLG59M1558V is designed according to the statements above and is illustrated on Figure 1. Please note that evaluation board has D_Sense and S_Sense pads. They cannot carry high currents and dedicated only for RDSON evaluation. Please solder your SLG59M1558V here Figure 1. SLG59M1558V Evaluation Board Datasheet CFR0011-120-01 Revision 1.07 Page 8 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch 1 1 VDD C2 1 2 3 4 5 VDD CAP2 GND CAP1 ON1 S2 ON2 S1 D1 D2 C1 10 9 8 7 6 CAP/RILIM ON D_Sense1 1 1 2 3 U1 1 2 3 4 VDD ON D D C3 8 7 6 5 GND CAP S S C4 1 3 5 7 9 S_Sense1 1 C5 R1 C6 2 4 6 8 10 R2 R3 R4 R_Array 1 3 5 7 9 C7 2 4 6 8 10 U2 9 1 2 3 4 D_Sense2 1 ON VDD D D D 8 7 6 5 GND CAP S S S_Sense2 1 C8 U3 1 2 3 4 D_Sense3 1 ON VDD D D 8 7 6 5 GND CAP S S S_Sense3 1 C9 U4 9 1 2 3 4 D_Sense4 1 ON VDD D D D U5 1 2 3 4 D_Sense5 1 8 7 6 5 GND S S S ON VIN VIN VIN 1 2 U6 ON VIN 8 7 6 5 GND VOUT VOUT VOUT GND VOUT S_Sense4 1 S_Sense5 1 4 3 D_Sense6 1 D/VIN D/VIN 1 1 1 1 S_Sense6 1 S/VOUT S/VOUT Figure 2. SLG59M1558V Evaluation Board Connection Circuit Datasheet CFR0011-120-01 Revision 1.07 Page 9 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch Basic Test Setup and Connections Figure 3. SLG59M1558V Evaluation Board Connection Circuit EVB Configuration 1. Connect oscilloscope probes to D/VIN, S/VOUT, ON, etc.; 2. Turn on Power Supply 1 and set desired VIN from 1.5 V…5.5 V range; 3. Toggle the ON signal High or Low to observe SLG59M1558V operation. Datasheet CFR0011-120-01 Revision 1.07 Page 10 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch Package Top Marking System Definition NN Pin 1 Identifier + Serial Number Line 1 Serial Number Line 2 NN - Part Serial Number Field Line 1 where each “N” character can be A-Z and 0-9 + - Part Serial Number Field Line 2 where “+” character can be +, -, =, or blank Datasheet CFR0011-120-01 Revision 1.07 Page 11 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch Package Drawing and Dimensions 4 Lead STDFN Package 1.0 x 1.0 mm Datasheet CFR0011-120-01 Revision 1.07 Page 12 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch Tape and Reel Specifications Max Units Leader (min) Nominal Reel & Package # of Package Size Hub Size Length Type Pins per Reel per Box Pockets [mm] [mm] [mm] STDFN 4L Green 4 1.0 x 1.0 x 0.55 8000 8000 178 / 60 200 400 Trailer (min) Pockets Length [mm] Tape Width [mm] 200 400 8 Part Pitch [mm] 2 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Pocket BTM Length Width STDFN 4L Green Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole Index Hole to Tape to Pocket Tape Width Edge Center A0 B0 K0 P0 P1 D0 E F W 1.16 1.16 0.63 4 2 1.5 1.75 3.5 8 Refer to EIA-481 specification Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 0.55 mm3 (nominal). More information can be found at www.jedec.org. Datasheet CFR0011-120-01 Revision 1.07 Page 13 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1558V An Ultra-small 1.6 mm2, 28.5 mΩ, 1.0 A, Load Switch Revision History Date Version 2/2/2022 1.07 Updated Company name and logo Fixed typos 10/27/2020 1.06 Added MSL to Abs Max Table 6/10/2020 1.05 Updated Style and formatting Added Power Dissipation Considerations Added Layout Guidelines Fixed typos 11/14/2017 1.04 Updated Package Marking Definition 11/30/2016 1.03 Fixed Parameter name from VDD to VIN in Abs. Max Table 6/22/2016 1.02 Added section on Power Up/Down Sequence Considerations Removed IDS_lkg parameter (same as IDD when OFF) Updated Recommended Layout suggestion 9/11/2015 1.01 Updated IDD and Tdelay_ON Datasheet CFR0011-120-01 Change Revision 1.07 Page 14 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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