HV7350K6-G

HV7350 8-Channel High-Speed ±60V ±1A Ultrasound RTZ Pulser Features • • • • • • • • • • • • General Description HVCMOS® Technology for High Performance High-density Integrated Ultrasound Transmitter 0V to ±60V Output Voltage ±1A Source and Sink Current in Pulse Mode ±1A Source and Sink Current in Return-to-Zero (RTZ) Mode Up to 20 MHz Operating Frequency Matched Delay Times Optional Clock Realignment 3.3V CMOS Logic Interface and Reference +3.3V Low-voltage Supply for VDD Built-in Linear Regulators for Floating Gate Drivers Built-in Output Drain Diodes and Bleed Resistors Applications • Portable Medical Ultrasound Imaging • Piezoelectric Transducer Drivers • Pulse Waveform Generator The HV7350 is an 8-channel monolithic high-voltage high-speed pulse generator with built-in fast return to zero-damping FETs. This high-voltage and high-speed integrated circuit is designed for portable medical ultrasound imaging system. The HV7350 consists of a controller logic interface circuit, level translators, MOSFET gate drives, and high-current power P-channel and N-channel MOSFETs as the output stage for each channel. The output peak currents of each channel are guaranteed to be over ±1A with up to ±60V pulse swings as well as Return-to-Zero mode. The gate drivers for the output MOSFETs are powered by built-in linear 5V regulators referenced to VPP and VNN. This direct coupling topology of the gate drivers not only saves four floating voltage supplies or AC coupling capacitors per channel but also makes the PCB layout smaller and easier. An input clock pin is available to realign all the logic input control lines to a master clock. Precise logic timing is always essential in any ultrasound systems. Package Type 56-lead (8 X 8) QFN (Top view) 56 1 See Table 2-1 for pin information.  2016 Microchip Technology Inc. DS20005627A-page 1 HV7350 Typical Application Circuit +3.3V 0.1µF +3.3V +10 to +60V 1.0µF VLL 1.0µF VDD 1.0µF CPOS CPF LRP 1.0µF VPP LRP 1 of 8 Channels REN GND GND RGND P-Driver PIN1 3.3V Logic VPF +5.0V OEN +5.0V NIN1 VPF Logic & Level Translator PIN8 TX1 DMP HVOUT1 VNF -5.0V X1 Rb N-Driver NIN8 RGND -5.0V GND CLK GND SUB DAP GND VNF LRN LRN CNEG GND CNF 1.0µF VNN RGND 1.0µF 1.0µF -10 to -60V DS20005627A-page 2  2016 Microchip Technology Inc. HV7350 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † GND and Substrate Voltage, VSUB ........................................................................................................................... 0V Positive Logic Supply, VLL ....................................................................................................................... –0.5V to +5.5V Positive Logic and Level Translator Supply, VDD ....................................................................................–0.5V to +5.5V Positive Level Translator Decoupling Pin, CPOS to GND ........................................................................ –0.5V to +5.5V Negative Level Translator Decoupling Pin, CNEG to GND ...................................................................... +0.5V to –5.5V Positive Floating Gate Driver Decoupling Pin, VPP–CPF ..........................................................................–0.5V to +5.5V Floating Gate Driver Decoupling Pin, CNF–VNN .......................................................................................–0.5V to +5.5V Differential High-voltage Supply, VPP–VNN ........................................................................................................... +130V High-voltage Positive Supply, VPP ............................................................................................................–0.5V to +65V High-voltage Negative Supply, VNN ......................................................................................................... +0.5V to –65V All Logic Input CLK, PINX, NINX, OEN and REN Voltages ...................................................................... –0.5V to +5.5V Operating Junction Temperature, TJ .....................................................................................................–40°C to +125°C Storage Temperature, TS ......................................................................................................................–65°C to +150°C ESD Rating (Note 1) .................................................................................................................................ESD Sensitive † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Note 1: Devices are ESD sensitive. Handling precautions are recommended. OPERATING SUPPLY VOLTAGES AND CURRENT  (EIGHT ACTIVE CHANNELS) Electrical Specifications: VLL = +3.3V, VDD = +3.3V, VPP = +60V, VNN = –60V, VCLK = +3.3V, TA = 25°C unless otherwise indicated. Parameter VDD Voltage Supply VDD UVLO Logic Voltage Reference Sym. Min. Typ. Max. Unit VDD 2.97 3.3 5.2 V UVLODD 2.3 2.6 2.8 V VLL 2.5 3.3 5 V UVLOLL 1.3 1.55 1.7 V Positive High-voltage Supply VPP +10 — +60 V Negative High-voltage Supply VNN –60 — –10 V VLL Current ILLQ — 8 — VDD Current IDDQ — 1 — VPP Current IPPQ — 5 10 VNN Current INNQ — 5 10 VLL Current ILLEN — 13 20 VDD Current IDDEN — 480 700 VPP Current IPPEN — 220 350 VNN Current INNEN — 300 400 VDD Current IDDCW — 2.3 — VPP Current IPPCW — 80 — VNN Current INNCW — 80 — VLL Current ILL,CLK — 33 — VLL UVLO  2016 Microchip Technology Inc. Conditions μA OEN = REN = 0 μA OEN = REN = 1  5 ms after f = 0 MHz mA f = 5 MHz, continuous, no loads, for calculation reference only μA fCLK = 10 MHz, PIN = NIN = 0 DS20005627A-page 3 HV7350 DC ELECTRICAL CHARACTERISTICS Electrical Specifications: VLL = +3.3V, VDD = +3.3V, VPP = +60V,VNN = –60V, VCLK = +3.3V, TA = 25°C unless otherwise indicated. Parameter Sym. Min. Typ. Max. Unit IOUT RON 1 — 1.5 13.2 — — A Ω ISD = 100 mA IOUT RON 1 — 1.5 8 — — A Ω ISD = 100 mA IOUT RON 1 — 1.5 13 — — A Ω ISD = 100 mA IOUT RON 1 — 1.5 9 — — A Ω ISD = 100 mA Input Logic High Voltage VIH 0.7 • VLL 0.8 • VLL VLL V Input Logic Low Voltage VIL 0 — –10 — — — — — — — — 0.3 • VLL 0.2 • VLL 10 — 5 μA μA pF 12 — 17 — 25 50 kΩ mW PULSER P-CHANNEL MOSFET Output Saturation Current Channel Resistance PULSER P-CHANNEL MOSFET Output Saturation Current Channel Resistance DAMPING P-CHANNEL MOSFET Output Saturation Current Channel Resistance DAMPING N-CHANNEL MOSFET Output Saturation Current Channel Resistance LOGIC INPUT Input Logic High Current IIH Input Logic Low Current IIL Input Logic Capacitance CIN MOSFET DRAIN BLEED RESISTOR Output Bleed Resistance RB1~8 Bleed Resistors Power Limit PRB1~8 Conditions VLL = 2.5V to 3.3V VLL = 5V VLL = 2.5V to 3.3V VLL = 5V V AC ELECTRICAL CHARACTERISTICS Electrical Specifications: VLL = +3.3V, VDD = +3.3V, VPP = +60V, VNN = –60V, VCLK = +3.3V, TA = 25°C unless otherwise indicated. Parameter Sym. Min. Typ. Max. Unit Output Rise Time tr — 30 — ns Output Fall Time tf — 30 — ns Enable Time tEN — 300 500 μs Disable Time tDIS — 2.8 10 μs Delay Time on PINX Rise td1 — 12 — Delay Time on NINX Rise td2 — 12 — Delay Time on Damping Rise td3 — 12 — Delay Time on Damping Fall td4 — 12 — Delay Time on CLK Rise tdc — 9 — ∆tDELAY — ±3 Delay Jitter on Rise or Fall tJ — RTZ FETs Drain Diode trr trr — Delay Time Matching DS20005627A-page 4 Conditions 330 pF//2.5 kΩ load 10%–90% Cap value (See Typical Application Circuit.), OEN = REN ns 1 Ω resistor load, D% < 1% (See Timing Waveforms.) 50% inputs to 50% TX current — ns P to N, channel to channel 30 — ps VPP/VNN = +/–25V, input tr 50% to HVOUT tr or tf 50%, with 330 pF//2.5 kΩ load 25 — ns IF = 1A, IR = 1A, RL = 10Ω  2016 Microchip Technology Inc. HV7350 AC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: VLL = +3.3V, VDD = +3.3V, VPP = +60V, VNN = –60V, VCLK = +3.3V, TA = 25°C unless otherwise indicated. Parameter Sym. Min. Typ. Max. Unit Retiming Clock Frequency fCLK 10 220 — MHz Retiming Clock Rise and Fall Times trc, tfc — 0.5 5 ns Set-up Time, PIN/NIN to CLK tSU 2 — — ns Hold time, CLK to PIN/NIN tH 1 — — ns Clock Time Low tCLK_LO 2 — 100 ns Clock Time High tCLK_HI 2 — 100 ns Clock Recognition Time tCLK_REC — 2 — ns Clock Release Time tCLK_RLS 150 300 800 ns Output Frequency Range fOUT — — 20 MHz Second Harmonic Distortion HD2 — –40 — dB Output Capacitance COSS — 50 — pF Conditions CLK input must have at least one pulse before PIN and NIN inputs are not zero. Be sure to return inputs to zero before stopping clock. 100Ω resistor load VDS = 25V, f = 1 MHz of TX pin total TEMPERATURE SPECIFICATIONS Parameter Sym. Min. Typ. Max. Unit Operating Junction Temperature TJ –40 — +125 °C Storage Temperature TS –65 — +150 °C JA — 21 — °C/W Conditions TEMPERATURE RANGE PACKAGE THERMAL RESISTANCE 56-lead (8 X 8) QFN LOGIC CONTROL TABLE MODE Asynchronous Mode Output Change on PIN/NIN Synchronous Mode Output Change at Retiming Clock (CLK) Rising Edge, registered by PIN/NIN Disabled  2016 Microchip Technology Inc. LOGIC INPUTS TXN, OUTPUT OEN CLK PINX NINX VPP VNN RGND 1 1 1 1 1 1 1 VLL VLL VLL VLL 0 1 0 1 0 1 0 0 0 1 1 0 0 1 OFF ON OFF OFF OFF ON OFF OFF OFF ON OFF OFF OFF ON ON OFF OFF OFF ON OFF OFF 1 1 OFF OFF OFF X X OFF OFF OFF 1 0 X DS20005627A-page 5 HV7350 Timing Waveforms CLK CLK PINn (NINn = 0) NINn (PINn = 0) 50% td1 50% td4 td3 IOUT td2 50% ITXn ITXn 0 0 50% Asynchronous Mode IOUT CLK CLK PINn (NINn = 0) NINn (PINn = 0) tdc tdc tdc tdc IOUT 50% ITXn 0 Synchronous Mode ITXn 0 50% IOUT DS20005627A-page 6  2016 Microchip Technology Inc. HV7350 2.0 PAD DESCRIPTION Table 2-1 details the description of pads in HV7350. Refer to Package Type for the location of pins. TABLE 2-1: PAD FUNCTION TABLE Pin Number Pin Name 1 PIN2 Input logic control of high-voltage output P-FET for Channel 2; High = on; Low = off (See Logic Control Table.) 2 NIN2 Input logic control of high-voltage output N-FET for Channel 2; High = on; Low = off (See Logic Control Table.) 3 PIN3 Input logic control of high-voltage output P-FET for Channel 3; High = on; Low = off (See Logic Control Table.) 4 NIN3 Input logic control of high-voltage output N-FET for Channel 3; High = on; Low = off (See Logic Control Table.) 5 PIN4 Input logic control of high-voltage output P-FET for Channel 4; High = on; Low = off (See Logic Control Table.) 6 NIN4 Input logic control of high-voltage output N-FET for Channel 4; High = on; Low = off (See Logic Control Table.) 7 OEN Output enable; High = on; Low = off (See Logic Control Table.) 8 REN Built-in positive and negative 5V voltage regulators enable; High = on; Low = off If REN = 0, four isolated 5V power supplies may provide, as external supplies, for the VPP to CPF, CNF to VNN, CPOS to GND and GND to CNEG pins. Note that between VPP to CPF and CNF to VNN, two must be floating supplies. (See Logic Control Table.) 9 PIN5 Input logic control of high-voltage output P-FET for Channel 5; High = on; Low = off (See Logic Control Table.) 10 NIN5 Input logic control of high-voltage output N-FET for Channel 5; High = on; Low = off (See Logic Control Table.) 11 PIN6 Input logic control of high-voltage output P-FET for Channel 6; High = on; Low = off (See Logic Control Table.) 12 NIN6 Input logic control of high-voltage output N-FET for Channel 6; High = on; Low = off (See Logic Control Table.) 13 PIN7 Input logic control of high-voltage output P-FET for Channel 7; High = on; Low = off (See Logic Control Table.) 14 NIN7 Input logic control of high-voltage output N-FET for Channel 7; High = on; Low = off (See Logic Control Table.) 15 PIN8 Input logic control of high-voltage output P-FET for Channel 8; High = on; Low = off (See Logic Control Table.) 16 NIN8 Input logic control of high-voltage output N-FET for Channel 8; High = on; Low = off (See Logic Control Table.) 17 VLL Logic supply voltage and reference input (+3.3V) 18 GND Logic and circuit return ground (0V) 19 VDD Positive voltage power supply (+3.3V) 20 VPP 21 VPP 22 VPP 23 CPF Built-in linear voltage VPF regulator output decoupling capacitor pin, 1 uF from VPP to CPF for every CPF pin 24 CNF Built-in linear voltage VNF regulator output decoupling capacitor pin, 1 uF from CNF to VNN for every CNF pin 25 VNN 26 VNN 27 VNN 28 TX8 29 RGND Description Positive high-voltage power supply (+10V to +60V) Negative high-voltage power supply (–10V to –60V) TX pulser Channel 8 output Damping ground and bleed resistors common return ground  2016 Microchip Technology Inc. DS20005627A-page 7 HV7350 TABLE 2-1: Pin Number PAD FUNCTION TABLE (CONTINUED) Pin Name Description 30 TX7 31 RGND 32 TX6 33 RGND 34 TX5 35 CNEG Built-in linear voltage –5V regulator output decoupling capacitor pin, 1 uF from CNEG to GND 36 CPOS Built-in linear voltage +5V regulator output decoupling capacitor pin, 1 uF from CPOS to GND 37 TX4 38 RGND 39 TX3 40 RGND TX pulser Channel 7 output Damping ground and bleed resistors common return ground TX pulser Channel 6 output Damping ground and bleed resistors common return ground TX pulser Channel 5 output TX pulser Channel 4 output Damping ground and bleed resistors common return ground TX pulser Channel 3 output Damping ground and bleed resistors common return ground 41 TX2 42 RGND TX pulser Channel 2 output 43 TX1 44 VNN 45 VNN 46 VNN 47 CNF Built-in linear voltage VNF regulator output decoupling capacitor pin, 1 uF from CNF to VNN for every CNF pin 48 CPF Built-in linear voltage VPF regulator output decoupling capacitor pin, 1 uF from VPP to CPF for every CPF pin 49 VPP 50 VPP Damping ground and bleed resistors common return ground TX pulser Channel 1 output Negative high-voltage power supply (–10V to –60V) Positive high-voltage power supply (+10V to +60V) 51 VPP 52 VDD Positive voltage power supply (+3.3V) 53 GND Logic and circuit return ground (0V) 54 CLK Retiming register clock input. Connect to VLL to disable the retiming function. 55 PIN1 Input logic control of high-voltage output P-FET for Channel 1; High = on; Low = off (See Logic Control Table.) 56 NIN1 Input logic control of high-voltage output N-FET for Channel 1; High = on; Low = off (See Logic Control Table.) VSUB (Thermal Pad) DS20005627A-page 8 Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be connected to GND (0V) externally.  2016 Microchip Technology Inc. HV7350 3.0 FUNCTIONAL DESCRIPTION Follow the steps below to power up and power down the HV7350: POWER-UP AND POWER-DOWN SEQUENCE (Note 1) Power-Up Step 1 2 3 4 5 Note 1: Power-Down Description Step Description All logic signals go to low VLL with logic signal low 1 2 VPP and VNN VDD REN = 1 (external supplies on) 3 REN = 0 (external supplies off) 4 VDD VPP and VNN Logic control signals active 5 VLL Powering up or down in any arbitrary sequence will not damage the device. The power-up sequence and power-down sequence are only recommended to minimize possible inrush current. OUTPUT CURRENT AND RON (Note 1, Note 4) ISC 2 RonP RonN IDMP 3 RonDP RonDN 1.5A 13Ω 6.5Ω 1.5A 13Ω 8Ω Note 1: 2: 3: 4: VPP/VNN = +/-60V; VDD = +3.3V; REN = 1 ISC is current into 1Ω to GND. IDMP is current from +/–30V connected to TX pin. Maximum pulse width for current measurement on TX pin is 20 ns.  2016 Microchip Technology Inc. DS20005627A-page 9 HV7350 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 56-lead QFN XXXXXX e3 YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: DS20005627A-page 10 Example HV7350K6 e3 1621987 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo.  2016 Microchip Technology Inc. HV7350 56-Lead QFN Package Outline (K6) 8.00x8.00mm body, 1.00mm height (max), 0.50mm pitch Note 1 (Index Area D/2 x E/2) D2 D 56 56 1 1 Note 1 (Index Area D/2 x E/2) e E E2 b View B Top View Bottom View Note 3 θ A3 A L Seating Plane L1 Note 2 A1 View B Side View Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. Notes: 1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU a printed indicator. 2. 'HSHQGLQJRQWKHPHWKRGRIPDQXIDFWXULQJDPD[LPXPRIPPSXOOEDFN/PD\EHSUHVHQW 3. 7KHLQQHUWLSRIWKHOHDGPD\EHHLWKHUURXQGHGRUVTXDUH Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 0.18 7.85* 2.75 7.85* 2.75 0.25 8.00 5.70 8.00 5.70 0.30 8.15* 6.70† 8.15* 6.70† e 0.50 BSC L L1 ș 0.30 0.00 0O 0.40 - - 0.50 0.15 14O JEDEC Registration MO-220, Variation VLLD-2, Issue K, June 2006. 7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ ‚7KLVGLPHQVLRQGLIIHUVIURPWKH-('(&GUDZLQJ Drawings are not to scale. S # S 6Q 68 8 0 0 031010   2016 Microchip Technology Inc. DS20005627A-page 11 HV7350 NOTES: DS20005627A-page 12  2016 Microchip Technology Inc. HV7350 APPENDIX A: REVISION HISTORY Revision A (October 2016) • Converted Supertex Doc# DSFP-HV7350 to Microchip DS20005627A • Changed the packaging quantity of 56-lead QFN M937 from 2000/Reel to 3000/Reel • Made minor text changes throughout the document  2016 Microchip Technology Inc. DS20005627A-page 13 HV7350 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. PART NO. Device Device: XX - Package Options HV7350 = X - Environmental X Media Type 8-Channel High-Speed ±60V ±1A Ultrasound RTZ Pulser Package: K6 = 56-lead VQFN Environmental: G Lead (Pb)-free/RoHS-compliant Package Media Type: = (blank) = M937 = DS20005627A-page 14 Examples: a) HV7350K6-G: 8-Channel High-Speed ±60V ±1A Ultrasound RTZ Pulser, 56-lead VQFN, 250/Tray b) HV7350K6-G-M937: 8-Channel High-Speed ±60V ±1A Ultrasound RTZ Pulser, 56-lead VQFN, 3000/Reel 250/Tray for a K6 Package 3000/Reel for a K6 Package  2016 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2016 Microchip Technology Inc. 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Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. 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