MAX24610EXG2

Short Form Data Sheet August 2014 MAX24605, MAX24610 5- or 10-Output Any-to-Any Clock Multiplier / Jitter Attenuator ICs General Description Features The MAX24605 and MAX24610 are flexible, highperformance clock multiplier and jitter attenuator ICs that include a DPLL and two independent APLLs. When locked to one of two input clock signals, the device performs any-to-any frequency conversion. From any input clock frequency 2kHz to 750MHz the device can produce frequency-locked APLL output frequencies up to 750MHz and as many as 10 output clock signals that are integer divisors of the APLL frequencies. Input jitter can be attenuated by an internal low-bandwidth DPLL. The DPLL also provides glitchless switching between input clocks and numerically controlled oscillator capability. Input switching can be manual or automatic. Using only a low-cost crystal or oscillator, the device can also serve as a frequency synthesizer IC. Output jitter is typically 0.18 to 0.3ps RMS for an APLL-only integer multiply and 0.25 to 0.4ps RMS for APLL-only fractional multiply or DPLL+APLL operation. ♦ ♦ ♦ Applications Jitter Attenuation, Frequency Conversion and Frequency Synthesis Applications in a Wide Variety of Equipment Types Ordering Information PART OUTPUTS TEMP RANGE PINPACKAGE MAX24605EXG+ 5 -40 to +85 81-CSBGA MAX24610EXG+ 10 -40 to +85 81-CSBGA +Denotes a lead(Pb)-free/RoHS-compliant package. ♦ Input Clocks ♦ One Crystal Input ♦ Two Differential or CMOS/TTL Inputs ♦ Differential to 750MHz, CMOS/TTL to 160MHz ♦ Continuous Input Clock Quality Monitoring ♦ Automatic or Manual Clock Selection ♦ Glitchless Reference Switching Low-Bandwidth DPLL ♦ Programmable Bandwidth, 4Hz to 400Hz ♦ Attenuates Input Jitter up to Several UI ♦ Manual Phase Adjustment Two APLLs Plus 5 or 10 Output Clocks ♦ APLLs Perform High Resolution Fractional-N Clock Multiplication ♦ Any Output Frequency from