ZL30112LDG1

ZL30112 SLIC/CODEC DPLL Data Sheet Features November 2009 • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input • Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse • Automatic entry and exit from freerun mode on reference fail • Provides DPLL lock and reference fail indication • DPLL bandwidth of 29 Hz for all rates of input references • Less than 0.6 nsecpp intrinsic jitter on all output clocks • 20 MHz external master clock source: clock oscillator or crystal • Simple hardware control interface Ordering Information ZL30112LDG1 32 Pin QFN* *Pb Free Matte Tin -40°C to +85°C Description The ZL30112 SLIC/CODEC DPLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices. The ZL30112 generates TDM clock and framing signals that are phase locked to the input reference. It helps ensure system reliability by monitoring its reference for stability and by maintaining stable output clocks during short periods when the reference is unavailable. Applications • Synchronizer for POTS SLIC/CODEC • Rate convert NTR 8 kHz or GPON physical interface clock to TDM clock REF_FAIL LOCK C2o REF DPLL OSCi OSCo C8o F8ko Reference Monitor RST Trays, Bake & Drypack Mode Control State Machine Master Clock Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2007-2009, Zarlink Semiconductor Inc. All Rights Reserved. ZL30112 1.0 Data Sheet Change Summary Changes from November 2007 Issue. Page, section, figure and table numbers refer to this current issue. Page Item Change 1 Ordering Information Updates to Ordering Information and Package Drawing. 2 Zarlink Semiconductor Inc. ZL30112 Data Sheet Table of Contents 1.0 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Time Interval Error (TIE) Corrector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 Digital Phase Lock Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.0 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.0 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 Jitter Generation (Intrinsic Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.4 Freerun Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.5 Capture Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.6 Lock Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.7 Time Interval Error (TIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.8 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.9 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.10 Phase Lock Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 Zarlink Semiconductor Inc. ZL30112 Data Sheet List of Figures Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections (32 pin 5 mm X 5 mm QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4 - DPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5 - Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9 - Timing Parameter Measurement Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 10 - Output Timing Referenced to F8o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 11 - Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 Zarlink Semiconductor Inc. ZL30112 Data Sheet List of Tables Table 1 - Typical Clock Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2 - Typical Crystal Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Zarlink Semiconductor Inc. 24 22 AGND F8ko 20 AGND Data Sheet AVCORE AVDD IC Pin Connections C8o 2.1 AGND Physical Description C2o 2.0 AVDD ZL30112 18 16 ZL30112 26 AVDD REF IC 14 12 30 OSCi OSCo 33 VDD IC (E-pad) 10 32 6 GND 8 AVCORE IC VCORE 4 LOCK VCORE GND RST IC 2 REF_FAIL IC VDD IC 28 IC IC GND Figure 2 - Pin Connections (32 pin 5 mm X 5 mm QFN) 6 Zarlink Semiconductor Inc. ZL30112 3.0 Data Sheet Pin Description I/O Type Pin # Name Description 1 GND 2 VCORE 3 LOCK O Lock Indicator (LVCMOS). This output goes to a logic high when the PLL is locked to a valid input reference. 4 REF_FAIL O Reference Failure Indicator (LVCMOS). A logic high at this output indicates that the REF input has failed. 5 IC O Internal Connection. Leave unconnected. 6 VCORE Positive Supply Voltage. +1.8 VDC nominal. 7 AVCORE Positive Analog Supply Voltage. +1.8 VDC nominal. 8 GND 9 IC I Internal Connection. Connect to GND. 10 RST I Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300 ns after the power supply pins have reached the minimum supply voltage. When the RST pin goes high, the device will transition into a Reset state for 3 ms. In the Reset state all outputs will be forced into high impedance. 11 OSCo O Oscillator Master Clock (LVCMOS). For crystal operation, a 20 MHz crystal is connected from this pin to OSCi. This output is not suitable for driving other devices. For clock oscillator operation, this pin must be left unconnected. 12 OSCi I Oscillator Master Clock (Input). For crystal operation, a 20 MHz crystal is connected from this pin to OSCo. For clock oscillator operation, this pin must be connected to a clock source. 13 IC I Internal Connection. Connect to GND. 14 VDD 15 AVDD Positive Analog Supply Voltage. +3.3 VDC nominal. 16 GND Ground. 0 V. 17 AGND 18 AVCORE Positive Analog Supply Voltage. +1.8 VDC nominal. 19 AVDD Positive Analog Supply Voltage. +3.3 VDC nominal. 20 IC I Internal Connection. Leave unconnected. 21 C8o O Clock 8.192 MHz (LVCMOS). This is a 8.192 MHz clock output. 22 AGND Analog Ground. 0V. 23 AVDD Positive Analog Supply Voltage. +3.3 VDC nominal. 24 C2o 25 AGND 26 F8ko Ground. 0 V. Positive Supply Voltage. +1.8 VDC nominal. Ground. 0 V. Positive Supply Voltage. +3.3 VDC nominal. Analog Ground. 0V. O Clock 2.048 MHz (LVCMOS). This is a 2.048 MHz clock output. Analog Ground. 0V. O Frame Pulse (LVCMOS). This is an 8 kHz frame pulse which marks the beginning of a 125 us frame. Pulse width is 122 ns. 7 Zarlink Semiconductor Inc. ZL30112 Data Sheet Pin # Name I/O Type 27 REF I Reference Input. This input is used to synchronize the PLL. Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz. 28 IC I Internal Connection. Leave unconnected. 29 IC I Internal Connection. Connect to VDD. 30 IC I Internal Connection. Connect to VDD. 31 VDD 32 IC 33 GND Description Positive Analog Supply Voltage. +3.3 VDC nominal. I Internal Connection. Connect to GND. Ground. 0 V. Package E-pad. This pin is internally connected to device GND. It must be externally connected to GND. 8 Zarlink Semiconductor Inc. ZL30112 4.0 Data Sheet Functional Description The ZL30112 is a SLIC/CODEC DPLL providing timing (clock) and synchronization (frame) signals to network interface cards. Figure 1 is a functional block diagram which is described in the following sections. 4.1 Reference Monitor The input reference is monitored by two reference monitor blocks. The block diagram of reference monitoring is shown in Figure 3. The reference frequency is detected and the clock is continuously monitored for two independent criteria that indicate abnormal behavior of the reference signal, for example; loss of clock or excessive level of frequency error. To ensure proper operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be observed. • Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference clock is 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz and provides this information to the various monitor circuits and the phase detector circuit of the DPLL. • Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of approximately 30 μs to quickly detect large frequency changes. • Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock. Reference Frequency Detector REF_FAIL REF Coarse Frequency Monitor Mode select state machine OR DPLL in FreeRun Mode Single Cycle Monitor Figure 3 - Reference Monitor Circuit Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force the DPLL into FreeRun mode. 9 Zarlink Semiconductor Inc. ZL30112 4.2 Data Sheet Time Interval Error (TIE) Corrector Circuit The TIE Corrector Circuit eliminates phase transients on the output clock that may occur in the course of recovery from Automatic Freerun mode to Normal mode. On recovery from Automatic Freerun mode, the TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL minimizes the phase transient it experiences when it switches to another reference input or recovers from Automatic Freerun mode. 4.3 Digital Phase Lock Loop (DPLL) The DPLL of the ZL30112 consists of a phase detector, an integrated on-chip loop filter, and a digitally controlled oscillator as shown in Figure 4. The data path from the phase detector to the filter is tapped and routed to the lock indicator that provides a lock indication which is output at the LOCK pin. lock indicator virtual reference from TIE corrector circuit phase detector loop filter digitally controlled oscillator LOCK DPLL reference to frequency synthesizer state select from control state machine feedback signal from frequency select MUX Figure 4 - DPLL Block Diagram Phase Detector - the phase detector compares the virtual reference signal from the TIE corrector circuit with the feedback signal and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the loop filter circuit. Loop Filter - the loop filter is similar to a first order low pass filter with bandwidth of 29 Hz suitable to provide timing and synchronization for network interface cards. 10 Zarlink Semiconductor Inc. ZL30112 Data Sheet Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the ZL30112. In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In the Automatic Freerun mode, the DCO is free running at a frequency equal to the frequency that the DCO was generating in Normal Mode. Lock Indicator - the lock detector monitors if the output value of the phase detector is within the phase-lockwindow for a certain time. The selected phase-lock-window guarantees the stable operation of the LOCK pin with maximum network jitter and wander on the reference input. If the DPLL goes into the Automatic Freerun mode, the LOCK pin will initially stay high for 0.1 s. If at that point the DPLL is still in the Automatic Freerun mode, the LOCK pin will go low. 4.4 Frequency Synthesizers The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which are synchronized to the input reference (REF). The frequency synthesizer uses digital techniques to generate output clocks and advanced noise shaping techniques to minimize the output jitter. The clock and frame pulse outputs have limited drive capability and should be buffered when driving high capacitance loads. 4.5 Master Clock The ZL30112 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. 11 Zarlink Semiconductor Inc. ZL30112 5.0 Data Sheet Modes of Operation Normal (locked) REF_DIS=1 REF_DIS=0 RST REF_DIS=1 TIE Correction freerun REF_DIS=0 REF_DIS=1: Current selected reference disrupted (see Figure 3) Figure 5 - Modes of Operation Normal Mode In Normal mode, the ZL30112 provides timing and frame synchronization signals which are synchronized to the reference input (REF). The input reference signal may have a nominal frequency of 8 kHz, 2.048 MHz, 8.192 MHz, or 19.44 MHz. The frequency of the reference inputs are automatically detected by the reference monitors. Automatic Freerun Mode Automatic freerun mode is typically used for short durations while system synchronization is temporarily disrupted. In Automatic freerun mode, the ZL30112 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on the freerun accuracy of the external oscillator. 6.0 Measures of Performance The following are some PLL performance indicators and their corresponding definitions. 6.1 Jitter Generation (Intrinsic Jitter) Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or 20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter numbers, not cycle-to-cycle jitter. 6.2 Jitter Tolerance Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards. 12 Zarlink Semiconductor Inc. ZL30112 6.3 Data Sheet Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. For the ZL30112, the internal low pass loop filter determines the jitter attenuation. Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (for example 75% of the specified maximum tolerable input jitter). 6.4 Freerun Accuracy Frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the ZL30112, the Freerun accuracy is equal to the master clock (OSCi) accuracy. 6.5 Capture Range Also referred to as pull-in range. This is the input frequency range over which the PLL must be able to pull into synchronization. The ZL30112 capture range is equal to ±130 ppm minus the accuracy of the master clock (OSCi). For example, a +32 ppm master clock results in a capture range of +162 ppm on one side and -98 ppm on the other side of frequency range. 6.6 Lock Range This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock range is equal to the capture range for the ZL30112. 6.7 Time Interval Error (TIE) TIE is the time delay between a given timing signal and an ideal timing signal. 6.8 Maximum Time Interval Error (MTIE) MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. 6.9 Phase Continuity Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the PLL after a signal disturbance due to a reference switch or a mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. 13 Zarlink Semiconductor Inc. ZL30112 6.10 Data Sheet Phase Lock Time This is the time it takes the PLL to phase lock to the input signal. Phase lock occurs when the input signal and output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter). Lock time is affected by many factors which include: • initial input to output phase difference • initial input to output frequency difference • PLL loop filter bandwidth • in-lock phase distance The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and frequency. Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. See Section 8.2, “Performance Characteristics“ for Maximum Phase Lock Time. 7.0 Applications This section contains ZL30112 application specific details for power supply decoupling, clock and crystal operation, reset operation, and control operation. 7.1 Power Supply Decoupling Jitter levels on the ZL30112 output clocks may increase if the device is exposed to excessive noise on its power pins. For optimal jitter performance, the ZL30112 device should be isolated from noise on power planes connected to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note ZLAN-178. 7.2 Master Clock The ZL30112 can use either a clock or crystal as the master timing source. Zarlink Application Note ZLAN-68 lists a number of applicable oscillators and crystals that can be used with the ZL30112. 7.2.1 Clock Oscillator When selecting a Clock Oscillator, numerous parameters must be considered. These includes absolute frequency, frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise. 1 Frequency 20 MHz 2 Tolerance As required 3 Rise & Fall Time