AD6122

a FEATURES Fully Compliant with IS98A and PCS Specifications Linear IF Amplifier –63 dB to +34 dB Linear-in-dB Gain Control Temperature-Compensated Gain Control Quadrature Modulator Modulates IFs from 50 MHz to 350 MHz Integral Low Dropout Regulator Accepts 2.9 V to 4.2 V Input from Battery Low Power 10.4 mA at Midgain >R2 Figure 28. Pad Topology   1  R1  L = 20 log  1 1  +  R1 R2 / 2 Z IN = 2R1+ R2 (3) (4) where L is the transducer loss (or loss through the pad) in dB and ZIN is the desired input resistance in ohms. Using these equations, we can design the attenuator circuit to provide whatever amount of attenuation we require. Figure 29 is provided to better understand the different voltage levels you can expect to see at different points of the AD6122. It represents the voltage and power levels expected for a maximum input condition of 500 mV p-p at the I and Q modulator and maximum gain in the IF amplifiers. When trying to make these measurements, a high impedance (10 MΩ) active FET probe (for example, the Tek P6204, from Tektronix) should be used to minimize the effects of loading the circuit with the probe. In order to produce these results, the attenuator is designed to have a 1 kΩ input impedance and the output of the IF amplifiers are loaded with 1 kΩ. The roofing filter is designed to resonate the parasitic capacitance at the IF frequency. MODULATORS I 500mV p-p DIFFERENTIAL LO 2 100mV p-p DIFFERENTIAL Q 500mV p-p DIFFERENTIAL –21dBm (REFERRED TO 1k ) 252.1mV p-p DIFFERENTIAL MODOP VCC –41dBm (REFERRED TO 1k ) 25.21mV p-p IF AMPLIFIERS DIFFERENTIAL IFIN –7dBm (REFERRED TO 1k ) 1.263V p-p DIFFERENTIAL TRANSMIT OUTPUT VGAIN = 2.5V GAIN = +34dB 1k 20dB ATTENUATOR ZIN = 1k ZOUT = 1k Figure 29. Level Diagram – 14 – REV. B AD6122 INPUT INTERFACES The AD6122 interfaces to CDMA baseband converters providing either IF or baseband outputs. The baseband input is provided by direct connection of the baseband converter’s baseband output to the baseband input of the AD6122 (Figure 30). The IF amplifier’s gain control is provided by connection of the transmit AGC DAC’s output on the baseband converter, through a low-pass filter to the VGAIN pin on the AD6122. PD1 TEMPERATURE COMPENSATION GAIN CONTROL SCALE FACTOR VGAIN TX AGC DAC REFIN EXT REF IN PD2 VCC LDOE LDOB LDOC LDOGND LOW DROPOUT REGULATOR REFOUT IFVCC IFGND IIPP I OUTPUT Q LOIPP LOIPN I DVCC QIPN QIPP MODOPP MODOPN 2 IIPN MODCMREF I OUTPUT VCM REF IN Q OUTPUT Q OUTPUT DGND AD6122 VCC VCC CDMA BASEBAND IC TXOPP TXOPN TXVCC IFGND IFINP IFINN Figure 30. Typical Connections to Baseband IC Using I and Q Inputs with SSOP Package REV. B – 15 – AD6122 AD6122 Evaluation Board The AD6122 Evaluation Board consists of an AD6122, I/O connectors, a 20-pin dual header, 2-pin headers and four AD830 high speed video difference amplifiers. It allows the user to evaluate the AD6122’s IF amplifier and modulator together or separately. Because the AD6122 may be used at any IF from 50 MHz to 350 MHz, pads are provided on the LOIPP input, TXOP output, MODOP output and IFIP inputs to allow the user to add matching networks. The board is configured for an IF frequency of 130.38 MHz when shipped. There is no difference between the configuration of the boards with the SSOP or LPCC package. The AD830s are used to provide single-ended to differential conversion and the appropriate phase shift for the I and Q data input pins. As a result, a single-ended signal generator can be used to generate these signals. In order to test the power-down modes of the AD6122, locate the two pin headers on the AD6122 evaluation boards labeled PD1 and PD2. By open-circuiting the pins labeled PD1, the IF amplifiers power down. By open-circuiting the pins labeled PD2, the modulator powers down. Note that the IF amplifiers and modulator are powered down unless the pins on the two pin headers, PD1 and PD2, are short circuited. The IF input port impedance match used during characterization of the AD6122 at Analog Devices is as follows: AD6122 50 1:8 383 511 SIGNAL GENERATOR 383 IFINN IFINP The IF output port impedance match used during characterization at Analog Devices is as follows: AD6122 TXOPP 453 205 TXOPN 453 SPECTRUM ANALYZER 4:1 50 1k Figure 32. IF Output Port Impedance Match Used During Characterization at ADI This is a broadband lossy output match for the 50 MHz to 350 MHz frequency range. The 4:1 ratio in Figure 32 is an impedance ratio and not a voltage ratio. As shipped, the board is configured as follows: 1. J1 is open and J2 is shorted. This enables the LDO regulator. The external PNP transistor should remain in place even when the regulator is bypassed (the Pin LDOB is pulled up by the transistor). 2. X11, X25, X18 and X26 are shorted and X12, X14, X19 and X21 are opened in order to connect the output of the modulator to the input of the IF amplifiers. 3. L4 and L5, the roofing filter components are optimized for an IF frequency of 130.38 MHz. 4. R14, R15 and R16 set the attenuation between the modulator outputs and the IF amplifier inputs to 20 dB. 5. PD1 and PD2 are pulled low by the jumpers on the two pin headers. To power down the chip, set PD1 and PD2 high by removing the jumpers. In order to look at the modulator and IF amplifiers separately, disconnect the output of the modulator from the input of the IF amplifiers. This is accomplished by short circuiting X12, X14, X19 and X20 and open circuiting X11, X18, X25 and X26. 1k Figure 31. IF Input Port Impedance Match Used During Characterization at ADI This is a broadband lossy match used for characterization over the 50 MHz to 350 MHz frequency range. All dBm references in the characterization data collected using this match are referenced to 1 kΩ. Note that the 1:8 ratio in Figure 31 is an impedance ratio and not a voltage ratio. – 16 – REV. B AD6122 Table III describes the high frequency signal connectors on the AD6122 customer sample boards. Table III. Evaluation Board SMA Signal Connector Description Table IV lists the connections for the 20-pin power-supply connector. Table IV. 20-Pin Power Supply Connection Information Pin # Connector I CH Description I Modulator Input. 250 mV p-p into 50 Ω termination, dc coupled. The level shifting and phase splitting is done on board by the AD830 amplifiers. Q Modulator Input. 250 mV p-p into 50 Ω termination, ac coupled. The level shifting and phase splitting is done on board by the AD830 amplifiers. Modulator Output. The differential-to-single ended conversion is performed by a balun on the board. Impedance matched to 50 Ω for 130.38 MHz IF frequency. IF Amplifier Input. Single-ended-to-differential conversion performed by a balun on board. Impedance matched to 50 Ω for 130.38 MHz IF frequency. IF Amplifier Output. Differential-to-singleended conversion performed by a balun on board. Impedance matched to 50 Ω for 130.38 MHz IF frequency. Local oscillator positive input at 2 × IF frequency. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function VPOS for AD6122; 2.9 V to 4.2 V using regulator; 2.7 V to 4.2 V bypassing regulator. VPOS for AD6122; 2.9 V to 4.2 V using regulator; 2.7 V to 3.6 V bypassing regulator. Ground. Ground. Ground. Regulated Output or Input Voltage; Connects to Pin 5 on AD6122. Ground. Ground. Ground. Ground. Ground. PD1; Power-Down 1 Input. Ground. 1.23 V Reference Voltage from AD6122. Ground. VGAIN; Gain Control Voltage Input. –15 V Supply for AD830 Differential Amplifier. +15 V Supply for AD830 Differential Amplifier. MODCMREF; common-mode reference output for baseband converter common-mode reference input. PD2; Power-Down 2 Input. Q CH MODOP IFIP TXOP LOIPP A schematic diagram of the evaluation board is on the next two pages. REV. B – 17 – AD6122 AD6122 PD1 PD2 VPOS 2.9V – 4.2V J2 0 FMMT4403CT-ND LDOE Q1 LDOB LDOC LDOGND DGND X2 0 LOIPP X1 X3 C24 0.1 F VCC C1 10nF C2 10nF LOIPP LOIPN DVCC L2 220nH DVCC TXOPP TXOPN TXVCC L3 220nH C25 10nF TXVCC IFGND REFOUT C29 10nF J1 VREG OUT C23 18pF IFVCC IFGND IIPP IIPN MODCMREF QIPN QIPP MODOPP MODOPN IFINP IFINN C11 10nF R14 = 442 R15 = 100 R16 = 442 R14 X18 0 X26 0 C8 10nF C10 10nF C9 10nF X12 X13 X14 L6 C30 R13 R15 R16 X23 27nH IFIP X22 56nH X24 X21 T3 X25 0 T2 IIPP VREG OUT IIPN MODCMREF QIPN QIPP 8:1 C27 10nF C26 10nF VREG OUT IFVCC REFOUT PD1 PD2 VGAIN REFIN R12 0 C28 10nF VGAIN L4 180nH L5 180nH X16 100nH X15 4pF X17 MODOP X5 100nH TXOP X4 X6 3pF 1:8 X8 C3 10nF 0 X7 X9 T1 X10 C4 0 10nF VCC X11 0 X19 X20 8:1 Figure 33. Schematic Diagram of the Evaluation Board – 18 – REV. B AD6122 C15 0.1 F +15V 1 2 MODCMREF 3 4 V–1 5 ICH R6 50 –15V C16 0.1 F C17 0.1 F +15V 1 2 MODCMREF 3 4 V–1 5 –15V C18 0.1 F V–1 8 U3 A=1 7 R8 50 1 2 TO IIPN MODCMREF 3 4 V–1 5 –15V C22 0.1 F V–1 +15V 8 U5 A=1 7 V–1 A=1 7 8 SOIC PACKAGE U2 R7 50 1 2 TO IIPP MODCMREF 3 4 V–1 5 QCH R9 50 –15V C20 0.1 F C21 0.1 F V–1 A=1 7 +15V 8 SOIC PACKAGE U4 R10 50 TO QIPP C19 0.1 F AD830 AD830 R11 50 TO QIPN AD830 AD830 TO TXVCC C6 18pF R1 10 C13 0.01 F VREG OUT P1 1 3 5 VPOS P2 2 4 6 8 10 12 14 16 18 20 L1 470nH R4 10k R5 10k FROM VPOS 2.9V–4.2V TO DVCC VREG OUT C5 18pF R2 10 C12 0.01 F R3 10 C14 0.01 F 7 9 11 13 PD1 REFOUT VGAIN +15V PD2 PD1 PD2 TO IFVCC C7 18pF 15 –15V MODCMREF 17 19 NOTES: 1. TO USE THE LDO REGULATOR, SHORT J2 AND OPEN J1. 2. TO BYPASS THE REGULATOR, SHORT J1 AND OPEN J2 3. TO CONNECT THE OUTPUT OF THE MODULATOR TO THE INPUT OF THE IF AMP, SHORT J5 AND J6. TO TEST THE MODULATOR AND THE IF AMP SEPARATELY, OPEN J5 AND J6. 4. INDICATES A 50 TRACE. Figure 34. Schematic Diagram of the Evaluation Board REV. B – 19 – AD6122 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead SSOP (RS-28) 0.407 (10.34) 0.397 (10.08) 28 15 1 14 0.078 (1.98) PIN 1 0.068 (1.73) 0.07 (1.79) 0.066 (1.67) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 8° 0.015 (0.38) SEATING 0.009 (0.229) 0° 0.010 (0.25) PLANE 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 32-Leadless Chip Scale Package (LPCC) (CP-32) 0.205 (5.20) 0.197 (5.00) SQ 0.189 (4.80) 25 24 0.128 (3.25) 0.106 (2.70) SQ 0.049 (1.25) 32 1 PIN 1 INDICATOR 0.015 (0.38) 0.012 (0.30) 0.009 (0.23) BOTTOM VIEW 17 16 8 9 0.138 (3.50) BSC 0.010 (0.25) REF 0.020 (0.50) BSC 0.039 (1.00) 0.035 (0.90) 0.031 (0.80) 0.002 (0.05) 0.001 (0.02) 0.000 (0.00) 0.018 (0.45) 0.016 (0.40) 0.014 (0.35) CONTROLLING DIMENSIONS ARE IN MILLIMETERS DIMENSIONS MEET JEDEC MO-220-VHHD-2 – 20 – REV. B PRINTED IN U.S.A. C00946a–.5–6/00 (rev. B) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.