ADF4208BRU

Dual RF PLL Frequency Synthesizers ADF4206/ADF4208 FEATURES GENERAL DESCRIPTION ADF4206: 550 MHz/550 MHz ADF4208: 2.0 GHz/1.1 GHz 2.7 V to 5.5 V power supply Selectable charge pump supply (VP) allows extended tuning voltage in 3 V systems Selectable charge pump currents On-chip oscillator circuit Selectable dual modulus prescaler RF2: 32/33 or 64/65 RF1: 32/33 or 64/65 3-wire serial interface Power-down mode The ADF420x family of dual frequency synthesizers are used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Each synthesizer consists of a low noise, digital, phase frequency detector (PFD); a precision charge pump; a programmable reference divider; programmable A and B counters; and a dual modulus prescaler (P/P + 1). The A (6-bit) and B (11-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. The on-chip oscillator circuitry allows the reference input to be derived from crystal oscillators. APPLICATIONS A complete phase-locked loop (PLL) can be implemented if the synthesizers are used with an external loop filter and voltage controlled oscillators (VCOs). Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Base stations for wireless radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Communications test equipment CATV equipment Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 VP1 VP2 ADF4206/ADF4208 N = BP + A 11-BIT RF2 B-COUNTER RF2INB OSCIN OSCOUT CLK DATA LE PHASE COMPARATOR RF2 PRESCALER CHARGE PUMP 6-BIT RF2 A-COUNTER RF2 LOCK DETECT OSCILLATOR 14-BIT RF2 R-COUNTER 22-BIT DATA REGISTER OUTPUT MUX RF1 LOCK DETECT N = BP + A CHARGE PUMP 11-BIT RF1 B-COUNTER RF1INB MUXOUT SDOUT 14-BIT RF1 R-COUNTER RF1INA CPRF2 CPRF1 PHASE COMPARATOR RF1 PRESCALER 6-BIT RF1 A-COUNTER DGNDRF1 AGNDRF1 DGNDRF2 AGNDRF2 01036-001 RF2INA Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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All rights reserved. ADF4206/ADF4208 TABLE OF CONTENTS Features .............................................................................................. 1 Pulse Swallow Function............................................................. 11 Applications....................................................................................... 1 R Counter .................................................................................... 11 General Description ......................................................................... 1 Phase Frequency Detector (PFD) and Charge Pump............ 12 Functional Block Diagram .............................................................. 1 MUXOUT and Lock Detect...................................................... 12 Revision History ............................................................................... 2 Lock Detect ................................................................................. 12 Specifications..................................................................................... 3 Input Shift Register .................................................................... 12 Timing Specifications .................................................................. 5 Program Modes .............................................................................. 18 Timing Diagram ........................................................................... 5 Power-Down ............................................................................... 18 Absolute Maximum Ratings............................................................ 6 IF Section (RF2) ......................................................................... 18 Transistor Count........................................................................... 6 RF Section (RF1) ........................................................................ 19 ESD Caution.................................................................................. 6 Applications Section....................................................................... 20 Pin Configuration and Function Descriptions............................. 7 Local Oscillator for GSM Handset Receiver........................... 20 Typical Performance Characteristics ............................................. 8 Local Oscillator for WCDMA Receiver .................................. 21 Circuit Description......................................................................... 11 Interfacing ....................................................................................... 22 Reference Input Section............................................................. 11 ADuC812 Interface .................................................................... 22 RF Input Stage............................................................................. 11 ADSP-2181 Interface ................................................................. 22 Prescaler....................................................................................... 11 Outline Dimensions ....................................................................... 23 A and B Counters ....................................................................... 11 Ordering Guide .......................................................................... 24 REVISION HISTORY 2/06—Rev. 0 to Rev. A Updated Format..................................................................Universal Deleted ADF4207 ...............................................................Universal Changes to Table 3............................................................................ 6 Changes to Function Description .................................................. 7 Changes to Table 4............................................................................ 7 Changes to Figure 22 Caption....................................................... 12 Changes to Pulse Swallow Function ............................................ 13 Changes to Figure 29...................................................................... 15 Changes to Figure 31...................................................................... 17 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 3/01—Revision 0: Initial Version Rev. A | Page 2 of 24 ADF4206/ADF4208 SPECIFICATIONS VDD1 = VDD2 = 3 V ± 10%, 5 V ± 10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V; AGNDRF1 = DGNDRF1 = AGNDRF2 = DGNDRF2 = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 1. Parameter RF/IF CHARACTERISTICS (3 V) RF1 Input Frequency (RF1IN) ADF4206 ADF4208 RF Input Sensitivity IF Input Frequency (RF2IN) ADF4206 ADF4208 IF Input Sensitivity Maximum Allowable Prescaler Output Frequency 3 RF CHARACTERISTICS (5 V) RF1 Input Frequency (RF1IN) ADF4206 ADF4208 RF Input Sensitivity IF Input Frequency (RF2IN) ADF4206 ADF4208 IF Input Sensitivity Maximum Allowable Prescaler Output Frequency3 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity 4 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 5 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy ICP Three-State Leakage Current LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage B Version 1 B Chips 2 Unit Test Conditions/Comments See Figure 22 for input circuit 0.05/0.55 0.08/2.0 –15/+4 0.05/0.55 0.08/2.0 −15/+4 GHz min/max GHz min/max dBm min/max For f < 50 MHz ensure SR > 23 V/μs For f < 50 MHz ensure SR > 37 V/μs 0.05/0.55 0.08/1.1 −15/+4 165 0.05/0.55 0.08/1.1 −15/+4 165 GHz min/max GHz min/max dBm min/max MHz max For f < 50 MHz ensure SR > 23 V/μs For f < 50 MHz ensure SR > 37 V/μs 0.05/0.55 0.08/2.0 −10/+4 0.05/0.55 0.08/2.0 −10/+4 For f < 50 MHz ensure SR > 32 V/μs For f < 50 MHz ensure SR > 51 V/μs 0.05/0.55 0.08/1.1 −10/+4 200 0.05/0.55 0.08/1.1 –10/+4 200 GHz min/max GHz min/max dBm min/max MHz min/max GHz min/max GHz min/max dBm min/max MHz max 5/40 −2 10 ±100 5/40 −2 10 ±100 MHz min/max dBm min pF max μA max For f < 5 MHz ensure SR > 9 V/μs 55 55 MHz max 5 1.25 2.5 1 5 1.25 2.5 1 mA typ mA typ % typ nA typ 0.8 × VDD 0.2 × VDD ±1 10 0.8 × VDD 0.2 × VDD ±1 10 V min V max μA max pF max VDD − 0.4 0.4 VDD − 0.4 0.4 V min V max Rev. A | Page 3 of 24 For f < 50 MHz ensure SR > 32 V/μs For f < 50 MHz ensure SR > 51 V/μs IOH = 500 μA IOL = 500 μA ADF4206/ADF4208 Parameter POWER SUPPLIES VDD1 VDD2 VP IDD (IDD1 + IDD2) 6 ADF4206 ADF4208 IDD1 ADF4206 ADF4208 IDD2 ADF4206 ADF4208 IP (IP1 + IP2) Low Power Sleep Mode NOISE CHARACTERISTICS Normalized Phase Noise Floor (RF1) 7 ADF4206 ADF4208 Phase Noise Performance 8 ADF4206 (RF1, RF2) ADF4208 (RF1) ADF4208 (RF1) Spurious Signals RF1, RF2 (20 kHz Loop B/W) B Version 1 B Chips 2 Unit 2.7/5.5 VDD1 VDD1/6.0 2.7/5.5 VDD1 VDD1/6.0 V min/V max V min/V max VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V 14 21 14 21 mA max mA max 9.5 mA typical at VDD = 3 V, TA = 25°C 14 mA typical at VDD = 3 V, TA = 25°C 8 14 8 14 mA max mA max 5.5 mA typical at VDD = 3 V, TA = 25°C 9 mA typical at VDD = 3 V, TA = 25°C 7.5 9 1 0.5 7.5 9 1 0.5 mA max mA max mA max μA typ 5 mA typical at VDD = 3 V, TA = 25°C 5.5 mA typical at VDD = 3 V, TA = 25°C TA = 25°C −213 −217 −213 −217 dBc/Hz typ dBc/Hz typ −92 −85 −91 −92 −85 −91 dBc/Hz typ dBc/Hz typ dBc/Hz typ −80/−84 −80/−84 dB typ 1 Test Conditions/Comments @ VCO output @ 540 MHz output, 200 kHz at PFD @ 1750 MHz output, 200 kHz at PFD @ 900 MHz output, 200 kHz at PFD @ 200 kHz/400 kHz offsets and 200 kHz PFD Operating temperature range for B version: −40°C to +85°C. The B chip specifications are given as typical values. This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 AC coupling ensures AVDD/2 bias. VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels. 5 Guaranteed by design. Sample tested to ensure compliance. 6 Typical values apply for VDD = 3 V; P = 32; RF1IN1/RF2IN2 for ADF4206 = 540 MHz; RF1IN1/RF2IN2 for ADF4208 = 900 MHz. 7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N. 8 The phase noise is measured at 1 kHz, unless otherwise noted. The phase noise is measured with the EVAL-ADF4206EB or the EVAL-ADF4208EB evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). 2 3 Rev. A | Page 4 of 24 ADF4206/ADF4208 TIMING SPECIFICATIONS VDD1 = VDD2 = 3 V ± 10%, 5 V ± 10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V; AGNDRF1 = DGNDRF1 = AGNDRF2 = DGNDRF2 = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 2. Parameter 1 t1 t2 t3 t4 t5 t6 1 Limit at TMIN to TMAX (B Version) 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min Test Conditions/Comments DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width Guaranteed by design but not production tested. TIMING DIAGRAM t3 t4 CLK t2 t1 DATA DB21 (MSB) DB20 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 t5 LE Figure 2. Timing Diagram Rev. A | Page 5 of 24 01036-002 LE ADF4206/ADF4208 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted.1 Table 3. Parameter VDD1 to GND2 VDD1 to VDD2 VP1, VP2 to GND VP1, VP2 to VDD1 Digital I/O Voltage to GND Analog I/O Voltage to GND OSCIN, OSCOUT, RF1IN (A, B), RF2IN (A, B) to GND RFINA to RFINB (RF1, RF2) Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance LFCSP θJA Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature (40 sec) Ratings −0.3 V to +7 V −0.3 V to +0.3 V −0.3 V to +7 V −0.3 V to +5.5 V −0.3 V to DVDD + 0.3 V −0.3 V to VP + 0.3 V −0.3 V to VDD + 0.3 V ±320 mV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TRANSISTOR COUNT 11,749 (CMOS) and 522 (Bipolar). −40°C to +85°C −65°C to +150°C 150°C 112°C/W 30.4°C/W 260°C 1 This device is a high performance RF integrated circuit with an ESD rating of