Data Sheet
ADG5243F
User Defined Fault Protection and Detection, 0.8 pC QINJ, Triple SPDT
FEATURES
►
►
►
►
►
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FUNCTIONAL BLOCK DIAGRAM
User defined supplies set overvoltage level
► Overvoltage protection up to −55 V and +55 V
► Power-off protection up to −55 V and +55 V
► Overvoltage detection on source pins
► Minimum secondary supply level: 4.5 V single-supply
► Interrupt flags indicate fault status
Low charge injection (QINJ): 0.8 pC
Low drain/source on capacitance: 10 pF
Latch-up immune under any circumstance
Known state without digital inputs present
VSS to VDD analog signal range
► ±5 V to ±22 V dual supply operation
► 8 V to 44 V single-supply operation
► Fully specified at ±15 V, ±20 V, +12 V, and +36 V
PRODUCT HIGHLIGHTS
APPLICATIONS
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Figure 1.
Analog input/output modules
Process control/distributed control systems
Data acquisition
Instrumentation
Avionics
Automatic test equipment
Communication systems
Relay replacement
1. The source pins are protected against voltages greater than the
secondary supply rails, up to −55 V and +55 V.
2. The source pins are protected against voltages between −55 V
and +55 V in an unpowered state.
3. Overvoltage detection with the digital output indicates the operating state of the switches.
4. Trench isolation guards against latch-up.
5. Optimized for low charge injection and on-capacitance.
6. The ADG5243F can be operated from a dual supply of ±5 V to
±22 V or a single power supply of 8 V to 44 V.
GENERAL DESCRIPTION
The ADG5243F comprises three independently selectable, singlepole/double-throw (SPDT) switches. All channels exhibit break-before-make switching action that prevents momentary shorting when
switching channels. An EN input enables or disables the device.
When disabled, all channels are switched off. Each switch conducts
equally well in both directions when on, and each switch has an
input signal range that extends to the supplies. The primary supply
voltages define the on-resistance profile, whereas the secondary
supply voltages define the voltage level at which the overvoltage
protection engages.
When no power supplies are present, the channel remains in the off
condition, and the switch inputs are high impedance. Under normal
operating conditions, if the analog input signal levels on any Sx
pin exceed the positive fault voltage (POSFV) or the negative fault
voltage (NEGFV) by a threshold voltage (VT), the channel turns off
and that Sx pin becomes high impedance. If the switch is selected
to be on, then the drain pin is pulled to the secondary supply
voltage that was exceeded. Input signal levels up to −55 V or +55 V
relative to ground are blocked, in both the powered and unpowered
conditions.
The low capacitance and charge injection of these switches make
them ideal solutions for data acquisition and sample-and-hold applications, where low glitch switching and fast settling times are
required.
Note that, throughout this data sheet, multifunction pins, such as
IN1/F1, are referred to either by the entire pin name or by a single
function of the pin, for example, IN1, when only that function is
relevant.
Rev. B
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Data Sheet
ADG5243F
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagram......................................1
Product Highlights................................................. 1
General Description...............................................1
Specifications........................................................ 3
±15 V Dual Supply..............................................3
±20 V Dual Supply..............................................5
12 V Single Supply............................................. 7
36 V Single Supply ............................................ 9
Continuous Current per Channel, Sx or Dx...... 11
Absolute Maximum Ratings.................................12
ESD Caution.....................................................12
Pin Configurations and Function Descriptions.....13
Typical Performance Characteristics................... 15
Test Circuits......................................................... 20
Terminology......................................................... 24
AC Power Supply Rejection Ratio
(ACPSRR) ..................................................... 25
Theory of Operation.............................................26
Switch Architecture...........................................26
User Defined Fault Protection.......................... 26
Applications Information...................................... 28
Power Supply Rails.......................................... 28
Power Supply Sequencing Protection.............. 28
Signal Range....................................................28
Power Supply Recommendations.................... 28
High Voltage Surge Suppression..................... 28
Intelligent Fault Detection.................................28
Large Voltage, High Frequency Signals........... 29
Outline Dimensions............................................. 30
Ordering Guide.................................................30
Evaluation Boards............................................ 30
REVISION HISTORY
11/2022—Rev. A to Rev. B
Changes to Drain Leakage Current, ID, With Overvoltage Parameter; Table 2............................................... 5
Updated Outline Dimensions......................................................................................................................... 30
10/2015—Revision 0: Initial Version
analog.com
Rev. B | 2 of 30
Data Sheet
ADG5243F
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
+25°C
−40°C to
+85°C
250
270
250
270
1
4
1
4
7
8.5
1.5
3.5
0.7
±0.1
±1
±0.1
±1
±0.3
±1.5
335
395
335
395
5
5
5
5
9.5
9.5
4.5
4.5
±10
±66
±78
µA typ
±25
±40
µA typ
±5
±2
±5
±5
±2
nA typ
±15
Power Supplies Floating
±100
±50
±100
±50
analog.com
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
±2
±8
±5
Digital Input Capacitance, CIN
Unit
Test Conditions/Comments
VDD = +13.5 V, VSS = −13.5 V, see Figure 35
VDD to VSS
Power Supplies Grounded
DIGITAL INPUTS/OUTPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
±0.7
±1.1
5.0
±50
nA max
nA typ
±100
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
VS = ±10 V, IS = −1 mA
VS = ±9 V, IS = −1 mA
VS = ±10 V, IS = −1 mA
VS = ±9 V, IS = −1 mA
VDD = +15 V, VSS = −15 V, VS = ±10 V, IS = −1 mA
VDD = +15 V, VSS = −15 V, VS = ±9 V, IS = −1 mA
See Figure 27
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD = ∓10 V, see Figure 33
VS = ±10 V, VD = ∓10 V, see Figure 33
VS = VD = ±10 V, see Figure 34
VDD = +16.5 V, VSS = −16.5 V, GND = 0 V, VS = ±55 V,
see Figure 32
VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, INx = 0 V or floating, VS = ±55 V, see Figure 31
VDD = +16.5 V, VSS = −16.5 V, GND = 0 V, VS = ±55 V,
see Figure 32
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, INx = 0
V, see Figure 31
VDD = floating, VSS = floating, GND = 0 V,
VS = ±55 V, INx = 0 V, see Figure 31
VIN = GND or VDD
Rev. B | 3 of 30
Data Sheet
ADG5243F
SPECIFICATIONS
Table 1. (Continued)
Parameter
Output Voltage
High, VOH
Low, VOL
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
+25°C
−40°C to
+85°C
−40°C to
+125°C
2.0
0.4
160
195
165
205
70
90
115
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
analog.com
90
115
745
945
90
65
900
−0.8
−74
−83
0.005
Test Conditions/Comments
V min
V max
210
215
220
230
110
110
85
Overvoltage Response Time, tRESPONSE
Unit
130
130
965
970
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
dB typ
% typ
350
10.5
4
4
10
MHz typ
dB typ
pF typ
pF typ
pF typ
1.3
0.15
2
0.75
1.25
0.65
0.2
0.95
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
2.1
1.4
1.0
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 47
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 45
RL = 1 kΩ, CL = 5 pF, see Figure 40
RL = 1 kΩ, CL = 5 pF, see Figure 41
CL = 12 pF, see Figure 42
CL = 12 pF, see Figure 43
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 44
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 39
RL = 10 kΩ, VS = 15 V p-p, f = 20 Hz to 20 kHz, see
Figure 36
RL = 50 Ω, CL = 5 pF, see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = POSFV = +16.5 V, VSS = NEGFV = −16.5 V,
GND = 0 V, digital inputs = 0 V, 5 V, or VDD
VS = ±55 V, all channels in fault
1.4
0.2
2.5
0.9
1.8
0.55
0.2
2.8
1.9
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
Rev. B | 4 of 30
Data Sheet
ADG5243F
SPECIFICATIONS
Table 1. (Continued)
Parameter
ISS + INEGFV
VDD/VSS
1
+25°C
−40°C to
+85°C
1.0
−40°C to
+125°C
Unit
Test Conditions/Comments
1.1
±5
±22
mA max
V min
V max
GND = 0 V
GND = 0 V
Guaranteed by design; not subject to production test.
±20 V DUAL SUPPLY
VDD = 20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
Power Supplies Grounded
analog.com
+25°C
−40°C to
+85°C
−40°C to
+125°C
Unit
Test Conditions/Comments
VDD = +18 V, VSS = −18 V, see Figure 35
VDD to VSS
270
290
250
270
1
4
1
4
27
29.5
5
6.5
0.7
±0.1
±1
±0.1
±1
±0.3
±1.5
355
410
335
395
5
5
5
5
29.5
29.5
8.5
8.5
±2
±5
±2
±5
±5
±10
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
±66
µA typ
±25
µA typ
±2
nA typ
±2
±5
±2
±2
μA max
nA typ
VS = ±15 V, IS = −1 mA
VS = ±13.5 V, IS = −1 mA
VS = ±15 V, IS = −1 mA
VS = ±13.5 V, IS = −1 mA
VDD = +20 V, VSS = −20 V, VS = ±15 V, IS = −1 mA
VDD = +20 V, VSS = −20 V, VS = ±13.5 V, IS = −1
mA
See Figure 27
VDD = +22 V, VSS = −22 V
VS = ±15 V, VD = ∓15 V, see Figure 33
VS = ±15 V, VD = ∓15 V, see Figure 33
VS = VD = ±15 V, see Figure 34
VDD = +22 V, VSS = −22 V, GND = 0 V,
VS = ±55 V, see Figure 32
VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, INx = 0 V or floating, VS = ±55 V, see Figure
31
VDD = +22 V, VSS = −22 V, GND = 0 V,
VS = ±55 V, see Figure 32
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, INx
= 0 V, see Figure 31
Rev. B | 5 of 30
Data Sheet
ADG5243F
SPECIFICATIONS
Table 2. (Continued)
Parameter
Power Supplies Floating
DIGITAL INPUTS/OUTPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
Output Voltage
High, VOH
Low, VOL
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
+25°C
−40°C to
+85°C
−40°C to
+125°C
Unit
±100
±50
±100
±50
±100
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±0.7
±1.1
5.0
±1.2
2.0
0.4
165
210
170
215
70
85
120
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
analog.com
75
105
820
1100
75
65
1000
−1.2
−74
−82
0.005
VDD = floating, VSS = floating, GND = 0 V,
VS = ±55 V, INx = 0 V, see Figure 31
VIN = GND or VDD
V min
V max
230
235
240
250
115
115
85
Overvoltage Response Time, tRESPONSE
Test Conditions/Comments
105
105
1250
1400
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
dB typ
% typ
350
10.5
4
4
10
MHz typ
dB typ
pF typ
pF typ
pF typ
1.3
0.15
2
0.75
1.25
0.65
mA typ
mA typ
mA max
mA typ
mA max
mA typ
2.1
1.4
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 47
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 45
RL = 1 kΩ, CL = 5 pF, see Figure 40
RL = 1 kΩ, CL = 5 pF, see Figure 41
CL = 12 pF, see Figure 42
CL = 12 pF, see Figure 43
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 44
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 39
RL = 10 kΩ, VS = 20 V p-p, f = 20 Hz to 20 kHz,
see Figure 36
RL = 50 Ω, CL = 5 pF, see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = POSFV = +22 V, VSS = NEGFV = −22 V,
GND = 0 V, digital inputs = 0 V, 5 V, or VDD
Rev. B | 6 of 30
Data Sheet
ADG5243F
SPECIFICATIONS
Table 2. (Continued)
Parameter
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
VDD/VSS
1
−40°C to
+85°C
+25°C
0.2
1.0
−40°C to
+125°C
Unit
1.0
mA typ
mA max
Test Conditions/Comments
VS = ±55 V, all channels in fault
1.4
0.2
2.5
0.9
1.8
0.55
0.2
1.0
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
2.8
1.9
1.1
±5
±22
GND = 0 V
GND = 0 V
Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
analog.com
+25°C
−40°C to
+85°C
−40°C to
+125°C
Unit
Test Conditions/Comments
VDD = 10.8 V, VSS = 0 V, see Figure 35
0 V to VDD
630
690
270
290
6
19
1
5
380
440
25
27
0.7
±0.1
±1
±0.1
±1
±0.3
±1.5
±63
710
730
355
410
19
19
5
5
460
460
28
28
±2
±5
±2
±5
±5
±10
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
µA typ
VS = 0 V to 10 V, IS = −1 mA
VS = 3.5 V to 8.5 V, IS = −1 mA
VS = 0 V to 10 V, IS = −1 mA
VS = 3.5 V to 8.5 V, IS = −1 mA
VS = 0 V to 10 V, IS = −1 mA
VS = 3.5 V to 8.5 V, IS = −1 mA
See Figure 27
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 33
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 33
VS = VD = 1 V/10 V, see Figure 34
VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS = ±55 V, see
Figure 32
Rev. B | 7 of 30
Data Sheet
ADG5243F
SPECIFICATIONS
Table 3. (Continued)
Parameter
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
+25°C
−40°C to
+85°C
Unit
Test Conditions/Comments
±25
µA typ
VDD = 0 V or floating, VSS = 0 V or floating, GND = 0 V,
INx = 0 V or floating, VS = ±55 V, see Figure 31
±2
nA typ
VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS = ±55 V, see
Figure 32
±8
±5
±15
Power Supplies Grounded
Power Supplies Floating
±100
±50
±100
±50
DIGITAL INPUTS/OUTPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
Output Voltage
High, VOH
Low, VOL
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
−40°C to
+125°C
±0.7
±1.1
5.0
±50
±100
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
2.0
0.4
140
170
145
170
95
115
80
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
analog.com
110
145
500
655
95
65
900
0.8
−74
−82
0.044
320
10.5
4
5
10
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, INx = 0
V, see Figure 31
VDD = floating, VSS = floating, GND = 0 V, VS = ±55 V,
INx = 0 V, see Figure 31
VIN = GND or VDD
V min
V max
185
195
185
200
125
125
60
Overvoltage Response Time, tRESPONSE
nA max
nA typ
145
145
720
765
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
dB typ
% typ
MHz typ
dB typ
pF typ
pF typ
pF typ
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 47
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 45
RL = 1 kΩ, CL = 5 pF, see Figure 40
RL = 1 kΩ, CL = 5 pF, see Figure 41
CL = 12 pF, see Figure 42
CL = 12 pF, see Figure 43
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 44
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 39
RL = 10 kΩ, VS = 6 V p-p, f = 20 Hz to 20 kHz, see
Figure 36
RL = 50 Ω, CL = 5 pF, see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = POSFV = 13.2 V, VSS = NEGFV = 0 V, GND = 0
V, digital inputs = 0 V, 5 V, or VDD
Rev. B | 8 of 30
Data Sheet
ADG5243F
SPECIFICATIONS
Table 3. (Continued)
Parameter
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
VDD/VSS
1
−40°C to
+85°C
+25°C
−40°C to
+125°C
1.3
0.15
2
0.75
1.4
0.55
0.2
0.95
2.1
1.5
1.0
Unit
Test Conditions/Comments
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
VS = ±55 V, all channels in fault
1.4
0.2
2.5
0.9
1.8
0.55
0.2
1.0
2.8
1.9
1.1
8
44
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
Digital inputs = 5 V
VS = ±55 V, VD = 0 V
GND = 0 V
GND = 0 V
Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
analog.com
+25°C
−40°C to
+85°C
−40°C to
+125°C
Unit
Test Conditions/Comments
VDD = 32.4 V, VSS = 0 V, see Figure 35
0 V to VDD
310
335
250
270
3
7
3
6.5
62
70
1.5
3.5
0.7
±0.1
±1
±0.1
415
480
335
395
16
18
11
12
85
100
4
±2
4
±5
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
nA typ
VS = 0 V to 30 V, IS = −1 mA
VS = 4.5 V to 28 V, IS = −1 mA
VS = 0 V to 30 V, IS = −1 mA
VS = 4.5 V to 28 V, IS = −1 mA
VS = 0 V to 30 V, IS = −1 mA
VS = 4.5 V to 28 V, IS = −1 mA
See Figure 27
VDD = 39.6 V, VSS = 0 V
VS = 1 V/30 V, VD = 30 V/1 V, see Figure 33
VS = 1 V/30 V, VD = 30 V/1 V, see Figure 33
Rev. B | 9 of 30
Data Sheet
ADG5243F
SPECIFICATIONS
Table 4. (Continued)
Parameter
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
+25°C
±1
±0.3
±1.5
−40°C to
+85°C
−40°C to
+125°C
±2
±5
±5
µA typ
±2
nA typ
Power Supplies Floating
±100
±50
±100
±50
tOFF (EN)
Break-Before-Make Time Delay, tD
±0.7
±1.1
5.0
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
2.0
0.4
155
190
160
195
95
115
100
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
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60
80
1400
1900
85
65
1600
−1.4
−74
−85
0.007
nA max
nA typ
±100
±50
VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS = +55 V, −40 V,
see Figure 32
VDD = 0 V or floating, VSS = 0 V or floating, GND = 0 V,
INx = 0 V or floating, VS = +55 V, −40 V, see Figure 31
VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS = +55 V, −40 V,
see Figure 32
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = +55 V, −40 V, INx
= 0 V, see Figure 31
VDD = floating, VSS = floating, GND = 0 V, VS = +55 V,
−40 V, INx = 0 V, see Figure 31
VIN = VGND or VDD
V min
V max
205
210
210
220
125
130
70
Overvoltage Response Time, tRESPONSE
VS = VD = 1 V/30 V, see Figure 34
±25
±15
tON (EN)
nA max
nA typ
nA max
µA typ
±8
±5
Digital Input Capacitance, CIN
Output Voltage
High, VOH
Low, VOL
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
Test Conditions/Comments
±58
Power Supplies Grounded
DIGITAL INPUTS/OUTPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
±10
Unit
85
85
2100
2200
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
dB typ
% typ
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 47
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 46
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 45
RL = 1 kΩ, CL = 5 pF, see Figure 40
RL = 1 kΩ, CL = 5 pF, see Figure 41
CL = 12 pF, see Figure 42
CL = 12 pF, see Figure 43
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 44
VS = 18 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 39
RL = 10 kΩ, VS = 18 V p-p, f = 20 Hz to 20 kHz, see
Figure 36
Rev. B | 10 of 30
Data Sheet
ADG5243F
SPECIFICATIONS
Table 4. (Continued)
Parameter
+25°C
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
−40°C to
+125°C
Unit
Test Conditions/Comments
355
10.5
4
4
9
MHz typ
dB typ
pF typ
pF typ
pF typ
RL = 50 Ω, CL = 5 pF, see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = POSFV = 39.6 V, VSS = NEGFV = 0 V, GND = 0 V,
digital inputs = 0 V, 5 V, or VDD
1.3
0.15
2
0.75
1.4
0.55
0.2
0.95
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
2.1
1.5
1.0
VS = +55 V, −40 V, all channels in fault
1.4
0.2
2.5
0.9
1.8
0.55
0.2
1.0
ISS
INEGFV
ISS + INEGFV
VDD/VSS
1
−40°C to
+85°C
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
2.8
1.9
1.1
8
44
GND = 0 V
GND = 0 V
Guaranteed by design; not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, SX OR DX
Sx is the S1A to S3A and S1B to S3B pins.
Table 5.
Parameter
20-LEAD TSSOP
θJA = 112.6°C/W
20-LEAD LFCSP
θJA = 30.4°C/W
analog.com
25°C
85°C
125°C
Unit
Test Conditions/Comments
17
10
11
7
7
5
mA max
mA max
VS = VSS to VDD − 4.5 V
VS = VSS to VDD
29
17
18
11
9
7
mA max
mA max
VS = VSS to VDD − 4.5 V
VS = VSS to VDD
Rev. B | 11 of 30
Data Sheet
ADG5243F
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
Rating
VDD to VSS
VDD to GND
VSS to GND
POSFV to GND
NEGFV to GND
Sx Pins
Sx to VDD or VSS
VS to VD
Dx Pins1
48 V
−0.3 V to +48 V
−48 V to +0.3 V
−0.3 V to VDD +0.3 V
VSS − 0.3 V to +0.3 V
−55 V to +55 V
80 V
80 V
NEGFV − 0.7 V to POSFV + 0.7 V or
30 mA, whichever occurs first
GND − 0.7 V to 48 V or 30 mA,
whichever occurs first
44.5 mA (pulsed at 1 ms, 10% duty
cycle maximum)
Data2 + 15%
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
1 mA
−40°C to +125°C
−65°C to +150°C
150°C
Digital Inputs
Peak Current, Sx or Dx Pins
Continuous Current, Sx or Dx Pins
Digital Outputs
Stresses at or above those listed under Absolute Maximum Ratings
cause permanent damage to the product. This is a stress rating
only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Dx Pins, Overvoltage State, Load Current
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Thermal Impedance, θJA
20-Lead TSSOP, Thermal
112.6°C/W
Impedance (4-Layer Board)
20-Lead LFCSP, Thermal Impedance (4- 30.4°C/W
Layer Board)
Reflow Soldering Peak Temperature, PbAs per JEDEC J-STD-020
Free
1
Overvoltages at the Dx pins are clamped by internal diodes. Limit the current to
the maximum ratings given.
2
See Table 5.
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Rev. B | 12 of 30
Data Sheet
ADG5243F
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 2. ADG5243F Pin Configuration (TSSOP)
Figure 3. ADG5243F Pin Configuration (LFCSP)
Table 7. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
Description
1
19
IN1/F1
2
20
IN2/F2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
S1A
D1
S1B
S2B
D2
S2A
NEGFV
10
8
SF
11
9
FF
12
10
POSFV
13
14
15
16
17
18
19
11
12
13
14
15
16
17
S3A
D3
S3B
VSS
VDD
GND
EN/F0
20
18
IN3
Logic Control Input (IN1) (See Table 8.)
Decoder Pin (F1). This pin is used together with the specific fault pin (SF) to indicate which input is in a fault condition (see Table
9).
Logic Control Input (IN2) (See Table 8).
Decoder Pin (F2). This pin is used together with the specific fault pin (SF) to indicate which input is in a fault condition (see Table
9).
Overvoltage Protected Source Terminal 1A. This pin can be an input or an output.
Drain Terminal 1. This pin can be an input or an output.
Overvoltage Protected Source Terminal 1B. This pin can be an input or an output.
Overvoltage Protected Source Terminal 2B. This pin can be an input or an output.
Drain Terminal 2. This pin can be an input or an output.
Overvoltage Protected Source Terminal 2A. This pin can be an input or an output.
Negative Fault Voltage. This pin is the negative supply voltage that determines the overvoltage protection level. If a secondary
supply is not used, connect this pin to VSS.
Specific Fault Digital Output. This pin has a high output when the device is in normal operation or a low output when a fault
condition is detected on a specific pin, depending on the state of F0, F1, and F2 as shown in Table 9. The SF pin has a weak
internal pull-up resistor, nominally 3 V output.
Fault Flag Digital Output. This pin has a high output when the device is in normal operation, or a low output when a fault
condition occurs on any of the Sx inputs. The FF pin has a weak internal pull-up resistor that allows multiple signals to be
combined into a single interrupt for larger modules that contain multiple devices.
Positive Fault Voltage. This pin is the positive supply voltage that determines the overvoltage protection level. If a secondary
supply is not used, connect this pin to VDD.
Overvoltage Protected Source Terminal 3A. This pin can be an input or an output.
Drain Terminal 3. This pin can be an input or an output.
Overvoltage Protected Source Terminal 3B. This pin can be an input or an output.
Most Negative Power Supply Potential.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Active Low Digital Input. When this pin is high, the device is disabled and all switches are off. When this pin is low, the INx logic
inputs determine the on switches.
Decoder Pin (F0). This pin is used together with the specific fault pin (SF) to indicate which input is in a fault condition (see Table
9).
Logic Control Input (See Table 8).
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Rev. B | 13 of 30
Data Sheet
ADG5243F
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions (Continued)
Pin No.
TSSOP
LFCSP
Mnemonic
Description
Exposed
Pad
EP
The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is
recommended that the pad be soldered to the substrate, VSS.
Table 8. Switch Selection Truth Table
EN
INx
SxA
SxB
1
0
0
X1
Off
Off
On
Off
On
Off
1
0
1
X means don’t care.
Table 9. Fault Diagnostic Output Truth Table
State of Specific Flag (SF) with Control Inputs (F2, F1, F0)
Switch in Fault1
0, 0, 0
0, 1, 0
1, 0, 0
1, 0, 1
1, 1, 0
1, 1, 1
State of Fault Flag (FF)
None
S1A
S1B
S2B
S2A
S3B
S3A
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
1
More than one switch can be in fault. See the Applications Information section for more information.
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Rev. B | 14 of 30
Data Sheet
ADG5243F
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. RON as a Function of VS, VD, Dual Supply
Figure 5. RON as a Function of VS, VD, 12 V Single Supply
Figure 7. RON as a Function of VS, VD for Different Temperatures, ±15 V Dual
Supply
Figure 8. RON as a Function of VS, VD for Different Temperatures, ±20 V Dual
Supply
Figure 6. RON as a Function of VS, VD, 36 V Single Supply
Figure 9. RON as a Function of VS, VD for Different Temperatures, 12 V Single
Supply
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Rev. B | 15 of 30
Data Sheet
ADG5243F
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 10. RON as a Function of VS, VD for Different Temperatures, 36 V
Single Supply
Figure 13. Leakage Current vs. Temperature, 12 V Single Supply
Figure 14. Leakage Current vs. Temperature, 36 V Single Supply
Figure 11. Leakage Current vs. Temperature, ±15 V Dual Supply
Figure 15. Overvoltage Leakage Current vs. Temperature, ±15 V Dual Supply
Figure 12. Leakage Current vs. Temperature, ±20 V Dual Supply
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Rev. B | 16 of 30
Data Sheet
ADG5243F
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 16. Overvoltage Leakage Current vs. Temperature, ±20 V Dual Supply
Figure 19. Off Isolation vs. Frequency, ±15 V Dual Supply
Figure 17. Overvoltage Leakage Current vs. Temperature, 12 V Single Supply
Figure 20. Crosstalk vs. Frequency, ±15 V Dual Supply
Figure 18. Overvoltage Leakage Current vs. Temperature, 36 V Single Supply
Figure 21. Charge Injection vs. Source Voltage (VS), Single Supply
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Rev. B | 17 of 30
Data Sheet
ADG5243F
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 22. Charge Injection vs. Source Voltage (VS), Dual Supply
Figure 25. Bandwidth vs. Frequency
Figure 23. ACPSRR vs. Frequency, ±15 V Dual Supply
Figure 26. tTRANSITION vs. Temperature
Figure 24. THD + N vs. Frequency
Figure 27. Threshold Voltage (VT) vs. Temperature
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Rev. B | 18 of 30
Data Sheet
ADG5243F
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 28. Drain Output Response to Positive Overvoltage (RL = 1 kΩ)
Figure 30. Large Signal Voltage Tracking vs. Frequency
Figure 29. Drain Output Response to Negative Overvoltage (RL = 1 kΩ)
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Rev. B | 19 of 30
Data Sheet
ADG5243F
TEST CIRCUITS
Figure 31. Switch Unpowered Leakage
Figure 36. THD + N
Figure 32. Switch Overvoltage Leakage
Figure 37. Off Isolation
Figure 33. Off Leakage
Figure 34. On Leakage
Figure 38. Bandwidth
Figure 35. On Resistance
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Rev. B | 20 of 30
Data Sheet
ADG5243F
TEST CIRCUITS
Figure 39. Channel-to-Channel Crosstalk
Figure 40. Overvoltage Response Time, tRESPONSE
Figure 41. Overvoltage Recovery Time, tRECOVERY
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Rev. B | 21 of 30
Data Sheet
ADG5243F
TEST CIRCUITS
Figure 42. Interrupt Flag Response Time, tDIGRESP
Figure 43. Interrupt Flag Recovery Time, tDIGREC
Figure 44. Interrupt Flag Recovery Time, tDIGREC, with a 1 kΩ Pull-Up Resistor
Figure 45. Break-Before-Make Time Delay, tD
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Rev. B | 22 of 30
Data Sheet
ADG5243F
TEST CIRCUITS
Figure 46. Enable Delay, tON (EN), tOFF (EN)
Figure 47. Digital Control Input to Output Switching Time, tTRANSITION
Figure 48. Charge Injection, QINJ
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Rev. B | 23 of 30
Data Sheet
ADG5243F
TERMINOLOGY
IDD
CD (Off)
IDD represents the positive supply current.
CD (off) represents the off switch drain capacitance, which is measured with reference to ground.
ISS
ISS represents the negative supply current.
CS (Off)
IPOSFV
CS (off) represents the off switch source capacitance, which is
measured with reference to ground.
IPOSFV represents the positive secondary supply current.
CD (On), CS (On)
INEGFV
INEGFV represents the negative secondary supply current.
CD (on) and CS (on) represent the on switch capacitances, which
are measured with reference to ground.
VD
CIN
VD represents the analog voltage on the Dx pins.
CIN is the digital input capacitance.
VS
tON (EN)
VS represents the analog voltage on the Sx pins.
tON (EN represents the delay between applying the digital control
input and the output switching on (see Figure 46).
RON
RON represents the ohmic resistance between the Dx pins and the
Sx pins.
∆RON
∆RON represents the difference between the RON of any two channels.
RFLAT(ON)
RFLAT(ON) is the flatness that is defined as the difference between
the maximum and minimum value of on resistance measured over
the specified analog signal range.
IS (Off)
IS (off) is the source leakage current with the switch off.
ID (Off)
ID (off) is the drain leakage current with the switch off.
tOFF (EN)
tOFF (EN) represents the delay between applying the digital control
input and the output switching off (see Figure 46).
tTRANSITION
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when switching from one switch state to another.
tD
tD represents the off time measured between the 80% points of both
switches when switching from one state to another.
tDIGRESP
tDIGRESP is the time required for the FF pin to go low (0.3 V),
measured with respect to the voltage on the source pin exceeding
the supply voltage by 0.5 V.
ID (On), IS (On)
tDIGREC
ID (on) and IS (on) represent the channel leakage currents with the
switch on.
tDIGREC is the time required for the FF pin to return high, measured
with respect to the voltage on the Sx pin falling below the supply
voltage plus 0.5 V.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the digital
inputs.
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tRESPONSE
tRESPONSE represents the delay between the source voltage exceeding the supply voltage by 0.5 V and the drain voltage falling to
90% of the supply voltage.
tRESPONSE(EN)
tRESPONSE (EN) represents the delay between the enable pin being
asserted and the drain reaching 90% of POSFV or NEGFV for a
switch that is in fault.
Rev. B | 24 of 30
Data Sheet
ADG5243F
TERMINOLOGY
tRECOVERY
AC Power Supply Rejection Ratio (ACPSRR)
tRECOVERY represents the delay between an overvoltage on a Sx pin
falling below the supply voltage plus 0.5 V and the drain voltage
rising from 0 V to 10% of the supply voltage.
ACPSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. ACPSRR is a measure of the ability of
the device to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of 0.62 V p-p.
Off Isolation
Off isolation is a measure of unwanted signal coupling through an
off switch.
Charge Injection
Charge injection is a measure of the glitch impulse transferred from
the digital input to the analog output during switching.
Channel to Channel Crosstalk
Channel to channel crosstalk is a measure of unwanted signal that
is coupled through from one channel to another as a result of
parasitic capacitance.
On Response
On response is the frequency response of the on switch.
VT
VT is the voltage threshold at which the overvoltage protection
circuitry engages (see Figure 27).
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of the
signal to the fundamental.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
−3 dB Bandwidth
−3 dB bandwidth is the frequency at which the output is attenuated
by 3 dB.
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Rev. B | 25 of 30
Data Sheet
ADG5243F
THEORY OF OPERATION
SWITCH ARCHITECTURE
Each channel of the ADG5243F consists of a parallel pair of
N-channel diffused metal-oxide semiconductor (NDMOS) and Pchannel DMOS (PDMOS) transistors. This construction provides
excellent performance across the signal range. The ADG5243F
channels operate as standard switches when input signals with a
voltage between POSFV and NEGFV are applied. For example, the
on resistance is 250 Ω typically and opening or closing the switch is
controlled using the appropriate control pins.
Additional internal circuitry enables the switch to detect overvoltage
inputs by comparing the voltage on a source pin with POSFV and
NEGFV. A signal is considered overvoltage if it exceeds these secondary supply voltages by the voltage threshold, VT. The threshold
voltage is typically 0.7 V, but can range from 0.8 V at −40°C down
to 0.6 V at +125°C. See Figure 27 to see the change in VT with
operating temperature.
The maximum voltage that can be applied to any source input is
+55 V or −55 V. When the device is powered using a single supply
of 25 V or greater, the maximum negative signal level is reduced.
It reduces from −55 V at VDD = +25 V to −40 V at VDD = +40 V to
remain within the 80 V maximum rating. Construction of the process
allows the channel to withstand 80 V across the switch when it is
opened. These overvoltage limits apply whether the power supplies
are present or not.
pin is unselected, only nanoamperes of leakage appear on the
drain pin. However, if the source is selected, the pin is pulled to
the supply rail. The device that pulls the drain pin to the rail has
an impedance of approximately 40 kΩ; thus, the Dx pin current
is limited to approximately 1 mA during a shorted load condition.
This internal impedance also determines the minimum external load
resistance required to ensure that the drain pin is pulled to the
desired voltage level during a fault.
When an overvoltage event occurs, the channels undisturbed by
the overvoltage input continue to operate normally without additional crosstalk.
ESD Performance
The drain pins have ESD protection diodes to the secondary supply
rails and the voltage at these pins must not exceed the secondary
supply voltages, POSFV and NEGFV. The source pins have specialized ESD protection that allows the signal voltage to reach ±55 V
regardless of supply voltage level. Exceeding ±55 V on any source
input can damage the ESD protection circuitry on the device. See
Figure 49 for an overview of the switch channel.
Trench Isolation
In the ADG5243F, an insulating oxide layer (trench) is placed
between the NDMOS and the PDMOS transistors of each switch.
Parasitic junctions, which occur between the transistors in junctionisolated switches, are eliminated, and the result is a switch that
is latch-up immune under all circumstances. The device passes a
JESD78D latch-up test of ±500 mA for 1 sec, which is the harshest
test in the specification.
Figure 49. Switch Channel and Control Function
When an overvoltage condition is detected on a source pin (Sx),
the switch automatically opens regardless of the digital logic state
and the source pin becomes high impedance. If a source pin is
selected that is in fault, the drain pin is pulled to the supply that was
exceeded. For example, if the source voltage exceeds POSFV, the
drain output pulls to POSFV. If the source voltage exceeds NEGFV,
the drain output pulls to NEGFV. In Figure 28, the voltage on the
drain pin can be seen to follow the voltage on the source pin until
the switch turns off completely. The drain pin then pulls to GND
due to the 1 kΩ load resistor; otherwise, it pulls to the POSFV
supply. The maximum voltage on the drain is limited by the internal
ESD diodes and the rate at which the output voltage discharges is
dependent on the load at the pin.
During overvoltage conditions, the leakage current into and out of
the source pins is limited to tens of microamperes. If the source
analog.com
Figure 50. Trench Isolation
USER DEFINED FAULT PROTECTION
POSFV and NEGFV are required secondary power supplies that
set the level at which the overvoltage protection is engaged.
POSFV can be supplied from 4.5 V to VDD, and NEGFV can be
supplied from VSS to 0 V. If a secondary supply is not available,
connect these pins to VDD (POSFV) and VSS (NEGFV). The overRev. B | 26 of 30
Data Sheet
ADG5243F
THEORY OF OPERATION
voltage protection then engages at the primary supply voltages.
When the voltages at the source inputs exceed POSFV or NEGFV
by VT, the switch turns off or, if the device is unpowered, the switch
remains off. The switch input remains high impedance regardless
of the digital input state and if it is selected, the drain pulls to
either POSFV or NEGFV. Signal levels up to +55 V and −55 V are
blocked in both the powered and unpowered condition as long as
the 80 V limitation between the source and supply pins is met.
Power-On Protection
The following conditions must be satisfied for the switch to be in the
on condition:
The primary supply must be VDD to VSS ≥ 8 V.
► For POSFV, the secondary supply must be between 4.5 V and
VDD, and for NEGFV, the secondary supply must be between
VSS and 0 V.
► The input signal must be between NEGFV − VT and POSFV +
V T.
► The digital logic control input has selected the switch.
►
When the switch is turned on, signal levels up to the secondary
supply rails are passed.
The switch responds to an analog input that exceeds POSFV or
NEGFV by a threshold voltage, VT, by turning off. The absolute
input voltage limits are −55 V and +55 V, while maintaining an
80 V limit between the source pin and the supply rails. The switch
remains off until the voltage at the source pin returns to between
POSFV and NEGFV.
The fault response time (tRESPONSE) when powered by ±15 V dual
supply is typically 90 ns and the fault recovery time (tRECOVERY) is
745 ns. These vary with supply voltages and output load conditions.
The maximum stress across the switch channel is 80 V, therefore,
the user must pay close attention to this limit under a fault condition.
For example, consider the case where the device is set up in a
multiplexer configuration as shown in Figure 51.
VDD/VSS and POSFV/NEGFV = ±22 V, S1A = S2B = +22 V, S1B
= +55 V, and S2A = −55 V.
► S1A and S2A are selected.
► The voltage between S1B and D1 = +55 V − (22 V) = +33 V.
► The voltage between S2B and D2 = +22 V − (−55 V) = +77 V.
►
These calculations are all within device specifications: a 55 V
maximum fault on the source inputs and a maximum of 80 V across
the off switch channel.
Figure 51. ADG5243F in an Overvoltage Condition
Power-Off Protection
When no power supplies are present, the switch remains in the
off condition, and the switch inputs are high impedance. This state
ensures that no current flows and prevents damage to the switch or
downstream circuitry. The switch output is a virtual open circuit.
The switch remains off regardless of whether the VDD and VSS
supplies are 0 V or floating. A GND reference must always be
present to ensure proper operation. Signal levels of up to ±55 V are
blocked in the unpowered condition.
Digital Input Protection
The ADG5243F can tolerate digital input signals being present
on the device without power. When the device is unpowered, the
switch is guaranteed to be in the off state, regardless of the state of
the digital logic signals.
The digital inputs are protected against positive faults of up to
44 V. The digital inputs do not offer protection against negative
overvoltages. ESD protection diodes connected to GND are present
on the digital inputs.
Overvoltage Interrupt Flag
The voltages on the source inputs of the ADG5243F are continuously monitored, and the state of the switches is indicated by an
active low digital output pin, FF.
The voltage on the FF pin indicates if any of the source input
pins are experiencing a fault condition. The output of the FF pin
is a nominal 3 V when all source pins are within normal operating
range. If any source pin voltage exceeds the secondary supply
voltage by VT, the FF output reduces to below 0.4 V.
Use the specific fault digital output pin, SF, to decode which inputs
are experiencing a fault condition. The SF pin reduces to below
0.4 V when a fault condition is detected on a specific pin, depending on the state of F0, F1, and F2 (see Table 9).
analog.com
Rev. B | 27 of 30
Data Sheet
ADG5243F
APPLICATIONS INFORMATION
The overvoltage protected family of switches and multiplexers provides robust solutions for instrumentation, industrial, automotive,
aerospace, and other harsh environments where overvoltage signals can be present and the system must remain operational both
during and after the overvoltage has occurred.
put. These rails can be used to power the ADG5243F, an amplifier,
and/or a precision converter in a typical signal chain.
POWER SUPPLY RAILS
To guarantee correct operation of the device, 0.1 µF decoupling
capacitors are required on the primary and secondary supplies. If
they are driven from the same supply, one set of 0.1 µF decoupling
capacitors is sufficient.
The secondary supplies (POSFV and NEGFV) provide the current
required to operate the fault protection and, thus, must be low impedance supplies. Therefore, they can be derived from the primary
supplies by using a resistor divider and buffer.
The secondary supply rails (POSFV and NEGFV) must not exceed
the primary supply rails (VDD and VSS) because this can lead to a
signal passing through the switch unintentionally.
The ADG5243F can operate with bipolar supplies between ±5 V
and ±22 V. The supplies on VDD and VSS need not be symmetrical,
but the VDD to VSS range must not exceed 44 V. The ADG5243F
can also operate with single supplies between 8 V and 44 V with
VSS connected to GND.
The ADG5243F device is fully specified at ±15 V, ±20 V, +12 V, and
+36 V supply ranges.
POWER SUPPLY SEQUENCING PROTECTION
The switch channel remains open when the device is unpowered
and signals from −55 V to +55 V can be applied without damaging
the device. The switch channel closes only when the supplies are
connected, a suitable digital control signal is placed on the control
pins, and the signal is within normal operating range. Placing the
ADG5243F between external connectors and sensitive components
offers protection in systems where a signal is presented to the
source pins before the supply voltages are available.
SIGNAL RANGE
The primary supplies define the on-resistance profile of the channel, whereas the secondary supplies define the signal range. Using
voltages on POSFV and NEGFV that are lower than VDD and VSS,
the required signal can benefit from the flat on resistance in the
center of the full signal capabilities of the device.
POWER SUPPLY RECOMMENDATIONS
Figure 52. Bipolar Power Solution
Table 10. Recommended Power Management Devices
Product
Description
ADP5070
1 A/0.6 A, dc-to-dc switching regulator with independent positive
and negative outputs
20 V, 200 mA, low noise, CMOS LDO
40 V, 200 mA, low noise, CMOS LDO
−28 V, −200 mA, low noise, linear regulator
ADP7118
ADP7142
ADP7182
HIGH VOLTAGE SURGE SUPPRESSION
The ADG5243F is not intended for use in very high voltage applications. The maximum operating voltage of the transistor is 80
V. In applications where the inputs are likely to be subject to overvoltages exceeding the breakdown voltage, use transient voltage
suppressors (TVSs) or similar.
INTELLIGENT FAULT DETECTION
The ADG5243F digital output pin, FF, can interface with a microprocessor or control system and can be used as an interrupt flag.
This feature provides real-time diagnostic information on the state
of the device and the system to which it connects.
The control system can use the digital interrupt, FF, to start a
variety of actions, as follows:
Initiating an investigation into the source of an overvoltage fault.
► Shutting down critical systems in response to the overvoltage
condition.
► Using data recorders to mark data during these events as unreliable or out of specification.
►
For systems that are sensitive during a start-up sequence, the
active low operation of the flag allows the system to ensure that the
ADG5243F is powered on and that all input voltages are within the
normal operating range before initiating operation.
The FF pin has a weak internal pull-up resistor, which allows the
signals to combine into a single interrupt for larger modules that
contain multiple devices.
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance signal
chains.
The recovery time, tDIGREC, can be decreased from a typical 65 µs
to 900 ns by using a 1 kΩ pull-up resistor.
An example of a bipolar power solution is shown in Figure 52. The
ADP7118 and ADP7182 can be used to generate clean positive
and negative rails from the ADP5070 dual switching regulator out-
The specific fault digital output, SF decodes which inputs are
experiencing a fault condition. The SF pin reduces to below 0.4 V
when a fault condition is detected on a specific pin, depending on
the state of the F0, F1, and F2 pins (see Table 9).
analog.com
Rev. B | 28 of 30
Data Sheet
ADG5243F
APPLICATIONS INFORMATION
LARGE VOLTAGE, HIGH FREQUENCY
SIGNALS
Figure 30 illustrates the voltage range and frequencies that the
ADG5243F can reliably convey. For signals that extend across the
full signal range from VSS to VDD, keep the frequency below 1 MHz.
If the required frequency is greater than 1 MHz, decrease the signal
range appropriately to ensure signal integrity.
analog.com
Rev. B | 29 of 30
Data Sheet
ADG5243F
OUTLINE DIMENSIONS
Figure 53. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Figure 54. 20–Lead, Lead Frame Chip Scale Package [LFCSP]
4 mm x 4 mm Body and 0.75 mm Package Height
(CP-20-8)
Dimensions shown in millimeters
Updated: October 25, 2022
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
ADG5243FBCPZ-RL7
ADG5243FBRUZ
ADG5243FBRUZ-RL7
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
20-Lead LFCSP (4mm x 4mm w/ EP)
20-Lead TSSOP
20-Lead TSSOP
Reel, 1500
1
Reel, 1000
Package
Option
CP-20-8
RU-20
RU-20
Z = RoHS Compliant Part.
EVALUATION BOARDS
Model1
Description
EVAL-ADG5243FEBZ
Evaluation Board
1
Z = RoHS Compliant Part.
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Rev. B | 30 of 30
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