FEATURES
FUNCTIONAL BLOCK DIAGRAMS
User defined secondary supplies set overvoltage level
Overvoltage protection up to −55 V and +55 V
Power-off protection up to −55 V and +55 V
Overvoltage detection on source pins
Minimum secondary supply level: 4.5 V single-supply
Interrupt flags indicate fault status
Low charge injection (QINJ): 0.8 pC
Low drain/source on capacitance
ADG5248F: 19 pF
ADG5249F: 14 pF
Latch-up immune under any circumstance
Known state without digital inputs present
VSS to VDD analog signal range
±5 V to ±22 V dual-supply operation
8 V to 44 V single-supply operation
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
ADG5248F
S1
D
S8
FAULT DETECTION
AND
SWITCH DRIVER
FF
SF
13072-001
Data Sheet
User Defined Fault Protection and Detection,
0.8 pC QINJ, 8:1/Dual 4:1 Multiplexers
ADG5248F/ADG5249F
A0 A1 A2 EN POSFV NEGFV
Figure 1. ADG5248F Functional Block Diagram
ADG5249F
S1A
DA
APPLICATIONS
S4A
Analog input/output modules
Process control/distributed control systems
Data acquisition
Instrumentation
Avionics
Automatic test equipment
Communication systems
Relay replacement
S1B
DB
S4B
A0 A1 EN POSFV NEGFV
SF
Figure 2. ADG5249F Functional Block Diagram
GENERAL DESCRIPTION
The ADG5248F and ADG5249F are 8:1 and dual 4:1 analog
multiplexers. The ADG5248F switches one of eight inputs to a
common output, and the ADG5249F switches one of four differential inputs to a common differential output. Each channel conducts
equally well in both directions when on, and each channel has an
input signal range that extends to the supplies. The primary supply
voltages define the on-resistance profile, whereas the secondary
supply voltages define the voltage level at which the overvoltage
protection engages.
When no power supplies are present, the channel remains in the off
condition, and the switch inputs are high impedance. Under normal
operating conditions, if the analog input signal levels on any Sx pin
exceed positive fault voltage (POSFV) or negative fault voltage
(NEGFV) by a threshold voltage (VT), the channel turns off and
that Sx pin becomes high impedance. If the switch on, the drain pin
is pulled to the secondary supply voltage that was exceeded. Input
signal levels up to +55 V or −55 V relative to ground are blocked, in
both the powered and unpowered conditions.
Rev. A
FF
13072-002
FAULT DETECTION
AND
SWITCH DRIVER
The low capacitance and charge injection of these switches make
them ideal solutions for data acquisition and sample-and-hold
applications, where low glitch switching and fast settling times
are required.
Note that, throughout this data sheet, multifunction pins, such as
A0/F0, are referred to either by the entire pin name or by a single
function of the pin, for example, A0, when only that function is
relevant.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
Source pins are protected against voltages greater than the
secondary supply rails, up to −55 V and +55 V.
Source pins are protected against voltages between −55 V
and +55 V in an unpowered state.
Overvoltage detection with digital output indicates
operating state of switches.
Trench isolation guards against latch-up.
Optimized for low charge injection and on capacitance.
The ADG5248F/ADG5249F can be operated from a dual
supply of ±5 V to ±22 V or a single power supply of 8 V to 44 V.
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ADG5248F/ADG5249F
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits ..................................................................................... 23
Applications ....................................................................................... 1
Terminology .................................................................................... 28
Functional Block Diagrams ............................................................. 1
Theory of Operation ...................................................................... 30
General Description ......................................................................... 1
Switch Architecture .................................................................... 30
Product Highlights ........................................................................... 1
User Defined Fault Protection .................................................. 31
Revision History ............................................................................... 2
Applications Information .............................................................. 32
Specifications..................................................................................... 3
Power Supply Rails ..................................................................... 32
±15 V Dual Supply ....................................................................... 3
Power Supply Sequencing Protection ...................................... 32
±20 V Dual Supply ....................................................................... 5
Signal Range ................................................................................ 32
12 V Single Supply ........................................................................ 7
Power Supply Recommendations............................................. 32
36 V Single Supply ........................................................................ 9
High Voltage Surge Suppression .............................................. 32
Continuous Current per Channel, Sx, D, or Dx ..................... 12
Intelligent Fault Detection ........................................................ 33
Absolute Maximum Ratings.......................................................... 13
Large Voltage, High Frequency Signals ................................... 33
ESD Caution ................................................................................ 13
Outline Dimensions ....................................................................... 34
Pin Configurations and Function Descriptions ......................... 14
Ordering Guide .......................................................................... 34
Typical Performance Characteristics ........................................... 18
REVISION HISTORY
7/2016—Rev. 0 to Rev. A
Added 20-Lead LFCSP....................................................... Universal
Changes to Table 5 .......................................................................... 12
Changes to Table 6 .......................................................................... 13
Added Figure 4; Renumbered Sequentially ................................ 14
Changes to Table 7 .......................................................................... 14
Added Figure 6 ................................................................................ 16
Changes to Table 10 ........................................................................ 16
Updated Outline Dimensions ....................................................... 34
Changes to Ordering Guide .......................................................... 34
4/2015—Revision 0: Initial Version
Rev. A | Page 2 of 34
Data Sheet
ADG5248F/ADG5249F
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
+25°C
−40°C to
+85°C
VDD to VSS
250
270
250
270
2.5
6
2.5
6
6.5
8
1.5
3.5
0.7
±0.1
±1
±0.1
±1
±0.3
±1.5
335
395
335
395
12
13
12
13
9
9
4
4
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
±5
±5
±10
±20
±25
nA typ
nA max
nA typ
nA max
nA typ
nA max
±66
±78
µA typ
±25
±40
µA typ
±10
±70
Power Supplies Grounded
±50
±500
Power Supplies Floating
±700
±50
±700
±50
Digital Input Capacitance, CIN
Unit
±2
Power Supplies Grounded or
Floating
Drain Leakage Current, ID
With Overvoltage
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
−40°C to
+125°C
±0.7
±1.1
5.0
nA typ
±90
nA max
nA typ
±700
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
Rev. A | Page 3 of 34
Test Conditions/Comments
VDD = +13.5 V, VSS = −13.5 V, see Figure 38
VS = ±10 V, IS = −1 mA
VS = ±9 V, IS = −1 mA
VS = ±10 V, IS = −1 mA
VS = ±9 V, IS = −1 mA
VS = ±10 V, IS = −1 mA
VS = ±9 V, IS = −1 mA
See Figure 30
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD = ∓10 V, see Figure 36
VS = ±10 V, VD = ∓10 V, see Figure 36
VS = VD = ±10 V, see Figure 37
VDD = +16.5 V, VSS = −16.5 V, GND = 0 V, VS = ±55 V,
see Figure 35
VDD = 0 V or floating, VSS = 0 V or floating, GND = 0 V,
Ax = 0 V or floating, VS = ±55 V, see Figure 34
VDD = +16.5 V, VSS = −16.5 V, GND = 0 V, VS = ±55 V,
see Figure 35
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, Ax =
0 V, see Figure 34
VDD = floating, VSS = floating, GND = 0 V, VS = ±55 V,
Ax = 0 V, see Figure 34
VIN = GND or VDD
ADG5248F/ADG5249F
Parameter
Output Voltage
High, VOH
Low, VOL
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Data Sheet
+25°C
−40°C to
+85°C
−40°C to
+125°C
2.0
0.8
210
290
200
280
105
120
155
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Adjacent Channels
Nonadjacent Channels
Total Harmonic Distortion Plus Noise,
THD + N
−3 dB Bandwidth
ADG5248F
ADG5249F
Insertion Loss
CS (Off )
CD (Off )
ADG5248F
ADG5249F
CD (On), CS (On)
ADG5248F
ADG5249F
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
90
115
745
945
90
65
900
−0.8
−75
Test Conditions/Comments
V min
V max
305
310
295
315
160
160
90
Overvoltage Response Time, tRESPONSE
Unit
130
130
965
970
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
−75
−88
0.005
dB typ
dB typ
% typ
190
320
10.5
4
MHz typ
MHz typ
dB typ
pF typ
13
8
pF typ
pF typ
19
14
pF typ
pF typ
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 50
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 49
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 49
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 48
RL = 1 kΩ, CL = 5 pF, see Figure 43
RL = 1 kΩ, CL = 5 pF, see Figure 44
CL = 12 pF, see Figure 45
CL = 12 pF, see Figure 46
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 47
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 51
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 41, worst
case channel
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
RL = 10 kΩ, VS = 15 V p-p, f = 20 Hz to 20 kHz, see
Figure 39
RL = 50 Ω, CL = 5 pF, see Figure 42
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 42
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = POSFV = +16.5 V; VSS = NEGFV = −16.5 V;
GND = 0 V; digital inputs = 0 V, 5 V, or VDD
1.15
0.15
2
0.75
1.25
0.45
0.2
0.8
2
1.25
0.85
Rev. A | Page 4 of 34
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
Data Sheet
Parameter
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
VDD/VSS
1
ADG5248F/ADG5249F
+25°C
−40°C to
+85°C
1.4
0.2
2.2
0.9
1.6
0.45
0.2
1.0
−40°C to
+125°C
2.3
1.7
1.1
±5
±22
Unit
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
Test Conditions/Comments
VS = ±55 V
GND = 0 V
GND = 0 V
Guaranteed by design; not subject to production test.
±20 V DUAL SUPPLY
VDD = 20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
+25°C
−40°C to
+85°C
−40°C to
+125°C
VDD to VSS
260
280
250
270
2.5
6
2.5
6
12.5
14
1.5
3.5
0.7
±0.1
±1
±0.1
±1
±0.3
±1.5
345
405
335
395
12
13
12
13
15
15
4
4
±2
±5
±5
±10
±20
±25
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
±66
µA typ
±25
µA typ
Rev. A | Page 5 of 34
Test Conditions/Comments
VDD = +18 V, VSS = −18 V, see Figure 38
VS = ±15 V, IS = −1 mA
VS = ±13.5 V, IS = −1 mA
VS = ±15 V, IS = −1 mA
VS = ±13.5 V, IS = −1 mA
VS = ±15 V, IS = −1 mA
VS = ±13.5 V, IS = −1 mA
See Figure 30
VDD = +22 V, VSS = −22 V
VS = ±15 V, VD = ∓15 V, see Figure 36
VS = ±15 V, VD = ∓15 V, see Figure 36
VS = VD = ±15 V, see Figure 37
VDD = 22 V, VSS = −22 V, GND = 0 V, VS = ±55 V,
see Figure 35
VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, Ax = 0 V or floating, VS = ±55 V, see Figure 34
ADG5248F/ADG5249F
Parameter
Drain Leakage Current, ID
With Overvoltage
Data Sheet
+25°C
−40°C to
+85°C
±10
±2
±500
±2
Power Supplies Grounded
Power Supplies Floating
±700
±50
±700
±50
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
Output Voltage
High, VOH
Low, VOL
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
−40°C to
+125°C
±0.7
±1.1
5.0
±2
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Adjacent Channels
Nonadjacent Channels
Total Harmonic Distortion Plus Noise,
THD + N
−3 dB Bandwidth
ADG5248F
ADG5249F
Insertion Loss
CS (Off )
CD (Off )
ADG5248F
ADG5249F
75
105
820
1100
75
65
1000
−1.2
−75
nA typ
VDD = +22 V, VSS = −22 V, GND = 0 V, VS = ±55 V,
see Figure 35
µA max
nA typ
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, Ax =
0 V, see Figure 34
VDD = floating, VSS = floating, GND = 0 V, VS =
±55 V, Ax = 0 V, see Figure 34
VIN = GND or VDD
V min
V max
340
340
340
340
155
155
95
Overvoltage Response Time, tRESPONSE
Test Conditions/Comments
±700
±50
2.0
0.8
230
335
225
325
100
135
175
Unit
105
105
1250
1400
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
−75
−88
0.005
dB typ
dB typ
% typ
190
320
10.5
4
MHz typ
MHz typ
dB typ
pF typ
13
8
pF typ
pF typ
Rev. A | Page 6 of 34
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 50
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 49
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 49
RL = 1 kΩ, CL = 35 pF
VS = 10 V, see Figure 48
RL = 1 kΩ, CL = 5 pF, see Figure 43
RL = 1 kΩ, CL = 5 pF, see Figure 44
CL = 12 pF, see Figure 45
CL = 12 pF, see Figure 46
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 47
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 51
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 41,
worst case channel
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
RL = 10 kΩ, VS = 20 V p-p, f = 20 Hz to 20 kHz,
see Figure 39
RL = 50 Ω, CL = 5 pF, see Figure 42
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 42
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
Data Sheet
Parameter
CD (On), CS (On)
ADG5248F
ADG5249F
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
VDD/VSS
1
ADG5248F/ADG5249F
+25°C
−40°C to
+85°C
−40°C to
+125°C
19
14
Unit
Test Conditions/Comments
VS = 0 V, f = 1 MHz
pF typ
pF typ
VDD = POSFV = +22 V; VSS = NEGFV = −22 V;
digital inputs = 0 V, 5 V, or VDD
1.15
0.15
2
0.75
1.25
0.45
0.2
0.8
2
1.25
0.85
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
VS = ±55 V
1.4
0.2
2.2
0.9
1.6
0.45
0.2
1.0
2.3
1.7
1.1
±5
±22
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
GND = 0 V
GND = 0 V
Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
+25°C
−40°C to
+85°C
−40°C to
+125°C
0 V to VDD
630
690
270
290
6
17
3
6.5
380
440
25
27
0.7
±0.1
±1
710
730
355
410
19
19
11
12
460
460
28
28
±2
±5
Rev. A | Page 7 of 34
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
nA typ
nA max
Test Conditions/Comments
VDD = 10.8 V, VSS = 0 V, see Figure 38
VS = 0 V to 10 V, IS = −1 mA
VS = 3.5 V to 8.5 V, IS = −1 mA
VS = 0 V to 10 V, IS = −1 mA
VS = 3.5 V to 8.5 V, IS = −1 mA
VS = 0 V to 10 V, IS = −1 mA
VS = 3.5 V to 8.5 V, IS = −1 mA
See Figure 30
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 36
ADG5248F/ADG5249F
Parameter
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
Data Sheet
+25°C
±0.1
±1
±0.3
±1.5
−40°C to
+85°C
−40°C to
+125°C
±5
±10
±20
±25
Unit
nA typ
nA max
nA typ
nA max
Test Conditions/Comments
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 36
±63
µA typ
±25
µA typ
VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS = ±55 V,
see Figure 35
VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, Ax = 0 V or floating, VS = ±55 V, see Figure 34
±10
nA typ
±50
±500
±70
Power Supplies Grounded
Power Supplies Floating
±700
±50
±700
±50
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
Output Voltage
High, VOH
Low, VOL
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
±0.7
±1.1
5.0
±90
±700
±50
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
2.0
0.8
165
205
160
200
125
150
100
Overvoltage Recovery Time, tRECOVERY
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Adjacent Channels
Nonadjacent Channels
Total Harmonic Distortion Plus Noise,
THD + N
110
145
500
655
95
65
900
0.2
−75
VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS = ±55 V,
see Figure 35
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, Ax =
0 V, see Figure 34
VDD = floating, VSS = floating, GND = 0 V, VS =
±55 V, Ax = 0 V, see Figure 34
VIN = GND or VDD
V min
V max
215
230
215
230
155
155
60
Overvoltage Response Time, tRESPONSE
nA max
nA typ
VS = VD = 1 V/10 V, see Figure 37
145
145
720
765
−75
−88
0.044
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
dB typ
dB typ
% typ
Rev. A | Page 8 of 34
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 50
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 49
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 49
RL = 1 kΩ, CL = 35 pF
VS = 8 V, see Figure 48
RL = 1 kΩ, CL = 5 pF, see Figure 43
RL = 1 kΩ, CL = 5 pF, see Figure 44
CL = 12 pF, see Figure 45
CL = 12 pF, see Figure 46
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 47
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 51
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 41,
worst case channel
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
RL = 10 kΩ, VS = 6 V p-p, f = 20 Hz to 20 kHz,
see Figure 39
Data Sheet
Parameter
−3 dB Bandwidth
ADG5248F
ADG5249F
Insertion Loss
CS (Off )
CD (Off )
ADG5248F
ADG5249F
CD (On), CS (On)
ADG5248F
ADG5249F
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
ADG5248F/ADG5249F
+25°C
−40°C to
+85°C
Unit
175
290
10.5
4
MHz typ
MHz typ
dB typ
pF typ
14
8
pF typ
pF typ
20
14
pF typ
pF typ
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF, see Figure 42
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 42
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V; VSS = 0 V; digital inputs = 0 V, 5 V,
or VDD
1.15
0.15
2
0.75
1.4
0.3
0.2
0.65
2
1.4
0.7
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
VS = ±55 V
1.4
0.2
2.2
0.9
1.6
0.45
0.2
1.0
2.3
1.7
1.1
8
44
VDD
1
−40°C to
+125°C
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
Digital inputs = 5 V
VS = ±55 V, VD = 0 V
GND = 0 V
GND = 0 V
Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
+25°C
−40°C to
+85°C
−40°C to
+125°C
0 V to VDD
310
335
250
270
3
7
3
6.5
415
480
335
395
16
18
11
12
Rev. A | Page 9 of 34
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
VDD = 32.4 V, VSS = 0 V, see Figure 38
VS = 0 V to 30 V, IS = −1 mA
VS = 4.5 V to 28 V, IS = −1 mA
VS = 0 V to 30 V, IS = −1 mA
VS = 4.5 V to 28 V, IS = −1 mA
ADG5248F/ADG5249F
Parameter
On-Resistance Flatness, RFLAT(ON)
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
Power Supplies Grounded or
Floating
Drain Leakage Current, ID
With Overvoltage
Data Sheet
+25°C
62
70
1.5
3.5
0.7
±0.1
±1
±0.1
±1
±0.3
±1.5
−40°C to
+85°C
−40°C to
+125°C
85
100
4
4
±2
±5
±5
±10
±20
±25
µA typ
±25
µA typ
±10
nA typ
±50
±500
±70
Power Supplies Floating
±700
±50
±700
±50
Digital Input Capacitance, CIN
Output Voltage
High, VOH
Low, VOL
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
±0.7
±1.1
5.0
±90
nA max
µA typ
2.0
0.8
V min
V max
µA typ
µA max
pF typ
±1.2
2.0
0.8
195
255
190
245
105
135
110
Overvoltage Recovery Time, tRECOVERY
60
80
1400
1900
nA max
nA typ
±700
±50
Test Conditions/Comments
VS = 0 V to 30 V, IS = −1 mA
VS = 4.5 V to 28 V, IS = −1 mA
See Figure 30
VDD = 39.6 V, VSS = 0 V
VS = 1 V/30 V, VD = 30 V/1 V, see Figure 36
VS = 1 V/30 V, VD = 30 V/1 V, see Figure 36
VS = VD = 1 V/30 V, see Figure 37
VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS = +55 V,
−40 V, see Figure 35
VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, Ax = 0 V or floating, VS = ±55 V, see Figure 34
VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS = +55 V,
−40 V, see Figure 35
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, Ax =
0 V, see Figure 34
VDD = floating, VSS = floating, GND = 0 V, VS = ±55 V,
Ax = 0 V, see Figure 34
VIN = VGND or VDD
V min
V max
275
285
270
280
145
145
60
Overvoltage Response Time, tRESPONSE
nA typ
nA max
nA typ
nA max
nA typ
nA max
±58
Power Supplies Grounded
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IINL or IINH
Unit
Ω typ
Ω max
Ω typ
Ω max
V typ
85
85
2100
2200
Rev. A | Page 10 of 34
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 50
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 49
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 49
RL = 1 kΩ, CL = 35 pF
VS = 18 V, see Figure 48
RL = 1 kΩ, CL = 5 pF, see Figure 43
RL = 1 kΩ, CL = 5 pF, see Figure 44
Data Sheet
Parameter
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Adjacent Channels
Nonadjacent Channels
Total Harmonic Distortion Plus Noise,
THD + N
−3 dB Bandwidth
ADG5248F
ADG5249F
Insertion Loss
CS (Off )
CD (Off )
ADG5248F
ADG5249F
CD (On), CS (On)
ADG5248F
ADG5249F
POWER REQUIREMENTS
Normal Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
Fault Mode
IDD
IPOSFV
IDD + IPOSFV
IGND
ISS
INEGFV
ISS + INEGFV
ADG5248F/ADG5249F
+25°C
85
65
1600
−1.2
−75
−40°C to
+125°C
Unit
ns typ
µs typ
ns typ
pC typ
dB typ
−75
−88
0.007
dB typ
dB typ
% typ
200
320
10.5
4
MHz typ
MHz typ
dB typ
pF typ
13
7
pF typ
pF typ
18
12
pF typ
pF typ
Test Conditions/Comments
CL = 12 pF, see Figure 45
CL = 12 pF, see Figure 46
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 47
VS = 18 V, RS = 0 Ω, CL = 1 nF, see Figure 51
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 41,
worst case channel
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
RL = 10 kΩ, VS = 18 V p-p, f = 20 Hz to 20 kHz,
see Figure 39
RL = 50 Ω, CL = 5 pF, see Figure 42
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 42
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V; VSS = 0 V; digital inputs = 0 V, 5 V, or VDD
1.15
0.15
2
0.75
1.4
0.3
0.2
0.65
2
1.4
0.7
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
VS = +55 V, −40 V
1.4
0.2
2.2
0.9
1.6
0.45
0.2
1.0
VDD
1
−40°C to
+85°C
2.3
1.7
1.1
8
44
Guaranteed by design; not subject to production test.
Rev. A | Page 11 of 34
mA typ
mA typ
mA max
mA typ
mA max
mA typ
mA typ
mA max
V min
V max
GND = 0 V
GND = 0 V
ADG5248F/ADG5249F
Data Sheet
CONTINUOUS CURRENT PER CHANNEL, Sx, 1 D, OR Dx
Table 5.
Parameter
ADG5248F
20-Lead TSSOP, θJA = 112.6°C/W
20-Lead LFCSP, θJA = 30.4°C/W
ADG5249F
20-Lead TSSOP, θJA = 112.6°C/W
20-Lead LFCSP, θJA = 30.4°C/W
1
25°C
85°C
125°C
Unit
Test Conditions/Comments
27
16
48
27
16
11
25
17
8
7
11
9
mA max
mA max
mA max
mA max
VS = VSS to VDD − 4.5 V
VS = VSS to VDD
VS = VSS to VDD − 4.5 V
VS = VSS to VDD
20
12
36
21
13
8
20
13
8
6
10
8
mA max
mA max
mA max
mA max
VS = VSS to VDD − 4.5 V
VS = VSS to VDD
VS = VSS to VDD − 4.5 V
VS = VSS to VDD
Sx is the S1 to S8 pins on the ADG5248F, and the S1A to S4A and S1B to S4B pins on the ADG5249F.
Rev. A | Page 12 of 34
Data Sheet
ADG5248F/ADG5249F
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
POSFV to GND
NEGFV to GND
Sx Pins
Sx to VDD or VSS
VS to VD
D or Dx Pins1
Digital Inputs
Peak Current, Sx, D, or Dx Pins
Continuous Current, Sx, D, or Dx
Pins
Digital Outputs
D or Dx Pins, Overvoltage State,
Load Current
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Thermal Impedance, θJA (4-Layer
Board)
20-Lead TSSOP
20-Lead LFCSP
Reflow Soldering Peak
Temperature, Pb-Free
Rating
48 V
−0.3 V to +48 V
−48 V to +0.3 V
−0.3 V to VDD + 0.3 V
VSS − 0.3 V to + 0.3 V
−55 V to +55 V
80 V
80 V
NEGFV − 0.7 V to POSFV +
0.7 V or 30 mA, whichever
occurs first
GND − 0.7 V to 48 V or
30 mA, whichever occurs first
72.5 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data2 + 15%
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
1 mA
−40°C to +125°C
−65°C to +150°C
150°C
112.6°C/W
30.4°C/W
As per JEDEC J-STD-020
Overvoltages at the D or Dx pins are clamped by internal diodes. Limit the
current to the maximum ratings given.
2
See Table 5.
1
Rev. A | Page 13 of 34
ADG5248F/ADG5249F
Data Sheet
A1/F1
19
A2
18
GND
S2 5
17 VDD
TOP VIEW
(Not to Scale) 16 S5
S3 6
15
S6
S4 7
14
S7
D 87
13
S8
NEGFV 9
12
POSFV
SF 10
11
FF
VSS
S1
S2
S3
S4
1
2
3
4
5
ADG5248F
TOP VIEW
(Not to Scale)
15
14
13
12
11
VDD
S5
S6
S7
S8
D 6
NEGFV 7
SF 8
FF 9
POSFV 10
S1 4
ADG5248F
13072-003
VSS 3
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
Figure 3. ADG5248F Pin Configuration (TSSOP)
13072-004
20
20
19
18
17
16
A0/F0 1
EN/F2 2
EN/F2
A0/F0
A1/F1
A2
GND
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADG5248F Pin Configuration (LFCSP)
Table 7. ADG5248F Pin Function Descriptions
TSSOP
1
Pin No.
LFCSP
19
Mnemonic
A0/F0
2
20
EN/F2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
VSS
S1
S2
S3
S4
D
NEGFV
10
8
SF
11
9
FF
12
10
POSFV
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
S8
S7
S6
S5
VDD
GND
A2
A1/F1
Not
Applicable
Exposed
Pad
EP
Description
Logic Control Input (A0). See Table 8.
Decoder Pin (F0). This pin is used together with the specific fault pin (SF) to indicate which input is
in a fault condition. See Table 9.
Active High Digital Input (EN). When this pin is low, the device is disabled and all switches are off.
When this pin is high, the Ax logic inputs determine the on switches.
Decoder Pin (F2). This pin is used together with the specific fault pin (SF) to indicate which input is
in a fault condition. See Table 9.
Most Negative Power Supply Potential.
Overvoltage Protected Source Terminal 1. This pin can be an input or an output.
Overvoltage Protected Source Terminal 2. This pin can be an input or an output.
Overvoltage Protected Source Terminal 3. This pin can be an input or an output.
Overvoltage Protected Source Terminal 4. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Negative Fault Voltage. This pin is the negative supply voltage that determines the overvoltage
protection level. If a secondary supply is not used, connect this pin to VSS.
Specific Fault Digital Output. This pin has a high output (weak internal pull-up resistor, nominally 3
V output) when the device is in normal operation, or a low output when a fault condition is
detected on a specific pin, depending on the state of F0, F1, and F2 as shown in Table 9.
Fault Flag Digital Output. This pin has a high output when the device is in normal operation, or a
low output when a fault condition occurs on any of the Sx inputs. The FF pin has a weak internal
pull-up resistor that allows multiple signals to be combined into a single interrupt for larger
modules that contain multiple devices.
Positive Fault Voltage. This pin is the positive supply voltage that determines the overvoltage
protection level. If a secondary supply is not used, connect this pin to VDD.
Overvoltage Protected Source Terminal 8. This pin can be an input or an output.
Overvoltage Protected Source Terminal 7. This pin can be an input or an output.
Overvoltage Protected Source Terminal 6. This pin can be an input or an output.
Overvoltage Protected Source Terminal 5. This pin can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input (A1). See Table 8.
Decoder Pin (F1). This pin is used together with the specific fault pin (SF) to indicate which input is
in a fault condition. See Table 9.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints
and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Rev. A | Page 14 of 34
Data Sheet
ADG5248F/ADG5249F
Table 8. ADG5248F Switch Selection Truth Table
A2
X1
0
0
0
0
1
1
1
1
1
A1
X1
0
0
1
1
0
0
1
1
A0
X1
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
On Switch
None
S1
S2
S3
S4
S5
S6
S7
S8
X is don’t care.
Table 9. ADG5248F Fault Diagnostic Output Truth Table
Switch in Fault1
None
S1
S2
S3
S4
S5
S6
S7
S8
1
0, 0, 0
1
0
1
1
1
1
1
1
1
State of Specific Flag (SF) with Control Inputs (F2, F1, F0)
0, 0, 1
0, 1, 0
0, 1, 1
1, 0, 0
1, 0, 1
1, 1, 0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
More than one switch can be in fault. See the Applications Information section for more information.
Rev. A | Page 15 of 34
1, 1, 1
1
1
1
1
1
1
1
1
0
State of the Fault Flag (FF)
1
0
0
0
0
0
0
0
0
Data Sheet
A1/F1
GND
18
VDD
17 S1B
TOP VIEW
(Not to Scale) 16 S2B
S3A 6
15
S3B
S4A 7
14
S4B
DA 87
13
DB
NEGFV 9
12
POSFV
SF 10
11
FF
VSS
S1A
S2A
S3A
S4A
1
2
3
4
5
ADG5249F
TOP VIEW
(Not to Scale)
15
14
13
12
11
S1B
S2B
S3B
S4B
DB
DA 6
NEGFV 7
SF 8
FF 9
POSFV 10
S2A 5
ADG5249F
13072-005
VSS 3
S1A 4
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
13072-006
20
19
20
19
18
17
16
A0/F0 1
EN/F2 2
EN/F2
A0/F0
A1/F1
GND
VDD
ADG5248F/ADG5249F
Figure 6. ADG5249F Pin Configuration (LFCSP)
Figure 5. ADG5249F Pin Configuration (TSSOP)
Table 10. ADG5249F Pin Function Descriptions
TSSOP
1
Pin No.
LFCSP
19
Mnemonic
A0/F0
2
20
EN/F2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
VSS
S1A
S2A
S3A
S4A
DA
NEGFV
10
8
SF
11
9
FF
12
10
POSFV
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
DB
S4B
S3B
S2B
S1B
VDD
GND
A1/F1
Not
Applicable
Exposed
Pad
EP
Description
Logic Control Input (A0). See Table 11.
Decoder Pin (F0). This pin is used together with the specific fault pin (SF) to indicate which input is
in a fault condition. See Table 12.
Active High Digital Input (EN). When this pin is low, the device is disabled and all switches are off.
When this pin is high, the Ax logic inputs determine the on switches.
Decoder Pin (F2). This pin is used together with the specific fault pin (SF) to indicate which input is
in a fault condition. See Table 12.
Most Negative Power Supply Potential.
Overvoltage Protected Source Terminal 1A. This pin can be an input or an output.
Overvoltage Protected Source Terminal 2A. This pin can be an input or an output.
Overvoltage Protected Source Terminal 3A. This pin can be an input or an output.
Overvoltage Protected Source Terminal 4A. This pin can be an input or an output.
Drain Terminal A. This pin can be an input or an output.
Negative Fault Voltage. This pin is the negative supply voltage that determines the overvoltage
protection level. If a secondary supply is not used, connect this pin to VSS.
Specific Fault Digital Output. This pin has a high output (weak internal pull-up resistor, nominally
3 V output) when the device is in normal operation, or a low output when a fault condition is
detected on a specific pin, depending on the state of F0, F1, and, F2 as shown in Table 12.
Fault Flag Digital Output. This pin has a high output when the device is in normal operation, or a
low output when a fault condition occurs on any of the Sx inputs. The FF pin has a weak internal
pull-up resistor that allows multiple signals to be combined into a single interrupt for larger
modules that contain multiple devices.
Positive Fault Voltage. This pin is the positive supply voltage that determines the overvoltage
protection level. If a secondary supply is not used, connect this pin to VDD.
Drain Terminal B. This pin can be an input or an output.
Overvoltage Protected Source Terminal 4B. This pin can be an input or an output.
Overvoltage Protected Source Terminal 3B. This pin can be an input or an output.
Overvoltage Protected Source Terminal 2B. This pin can be an input or an output.
Overvoltage Protected Source Terminal 1B. This pin can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input (A1). See Table 11.
Decoder Pin (F1). This pin is used together with the specific fault pin (SF) to indicate which input is
in a fault condition. See Table 12.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints
and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Rev. A | Page 16 of 34
Data Sheet
ADG5248F/ADG5249F
Table 11. ADG5249F Switch Selection Truth Table
A1
X1
0
0
1
1
1
A0
X1
0
1
0
1
EN
0
1
1
1
1
On Switch Pair
None
S1x
S2x
S3x
S4x
X is don’t care.
Table 12. ADG5249F Fault Diagnostic Output Truth Table
Switch in Fault1
None
S1A
S2A
S3A
S4A
S1B
S2B
S3B
S4B
1
0, 0, 0
1
0
1
1
1
1
1
1
1
State of Specific Flag (SF) with Control Inputs (F2, F1, F0)
0, 0, 1
0, 1, 0
0, 1, 1
1, 0, 0
1, 0, 1
1, 1, 0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
More than one switch can be in fault. See the Applications Information section for more information.
Rev. A | Page 17 of 34
1, 1, 1
1
1
1
1
1
1
1
1
0
State of the Fault Flag (FF)
1
0
0
0
0
0
0
0
0
ADG5248F/ADG5249F
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1400
TA = 25°C
±22V
±20V
1000
±18V
±16.5V
±15.0V
±13.5V
800
600
400
200
800
600
400
0
5
10
15
20
25
0
–15
–9
–6
–3
0
3
6
9
12
15
VS, VD (V)
Figure 7. RON as a Function of VS, VD, Dual Supply
Figure 10. RON as a Function of VS, VD for Different Temperatures,
±15 V Dual Supply
1200
1400
TA = 25°C
13.2V
12.0V
10.8V
VDD = +20V
VSS = –20V
+125°C
+85°C
+25°C
–40°C
1200
ON RESISTANCE (Ω)
1000
–12
13072-108
–5
13072-105
–10
–15
–20
VS, VD (V)
800
600
400
200
1000
800
600
400
2
0
4
6
8
10
12
14
VS, VD (V)
0
–20
13072-106
0
–15
–10
–5
0
5
10
15
20
VS, VD (V)
Figure 8. RON as a Function of VS, VD, 12 V Single Supply
13072-109
200
Figure 11. RON as a Function of VS, VD for Different Temperatures,
±20 V Dual Supply
1200
1400
TA = 25°C
39.6V
36.0V
32.4V
1200
ON RESISTANCE (Ω)
1000
VDD = 12V
VSS = 0V
+125°C
+85°C
+25°C
–40°C
800
600
400
200
1000
800
600
400
0
0
5
10
15
20
25
30
35
VS, VD (V)
40
13072-107
200
Figure 9. RON as a Function of VS, VD, 36 V Single Supply
0
0
2
4
6
8
10
12
VS, VD (V)
Figure 12. RON as a Function of VS, VD for Different Temperatures,
12 V Single Supply
Rev. A | Page 18 of 34
13072-110
ON RESISTANCE (Ω)
1000
200
0
–25
ON RESISTANCE (Ω)
VDD = +15V
VSS = –15V
+125°C
+85°C
+25°C
–40°C
1200
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
1200
Data Sheet
ADG5248F/ADG5249F
1.5
1400
1000
1.0
LEAKAGE CURRENT (nA)
1200
ON RESISTANCE (Ω)
VDD = 12V
VSS = 0V
VBIAS = 1V, 10V
VDD = 36V
VSS = 0V
+125°C
+85°C
+25°C
–40°C
800
600
400
0.5
0
–0.5
4
8
12
16
20
24
28
32
36
VS, VD (V)
–1.0
0
20
40
60
80
100
120
TEMPERATURE (°C)
13072-114
0
13072-111
0
Figure 16. Leakage Current vs. Temperature, 12 V Single Supply
Figure 13. RON as a Function of VS, VD for Different Temperatures,
36 V Single Supply
3
2.5
VDD = 36V
VSS = 0V
2 VBIAS = 1V, 30V
VDD = +15V
2.0 VSS = –15V
VBIAS = ±10V
1.5
LEAKAGE CURRENT (nA)
LEAKAGE CURRENT (nA)
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
200
1.0
0.5
0
–0.5
1
0
–1
–2
–1.0
20
40
60
80
100
120
TEMPERATURE (°C)
–4
0
40
60
80
100
120
TEMPERATURE (°C)
Figure 17. Leakage Current vs. Temperature, 36 V Single Supply
Figure 14. Leakage Current vs. Temperature, ±15 V Dual Supply
6
3
VDD = +15V
VSS = –15V
VDD = +20V
VSS = –20V
VBIAS = ±15V
5
1
0
–1
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
–3
0
20
40
60
3
2
VS = –30V
VS = +30V
VS = –55V
VS = +55V
1
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
80
100
120
TEMPERATURE (°C)
Figure 15. Leakage Current vs. Temperature, ±20 V Dual Supply
0
13072-113
–2
4
0
20
40
60
80
TEMPERATURE (°C)
100
120
13072-116
LEAKAGE CURRENT (nA)
2
LEAKAGE CURRENT (nA)
20
13072-115
0
13072-112
–2.0
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
–3
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
–1.5
Figure 18. Overvoltage Leakage Current vs. Temperature, ±15 V Dual Supply
Rev. A | Page 19 of 34
ADG5248F/ADG5249F
Data Sheet
0
6
VDD = +20V
VSS = –20V
OFF ISOLATION (dB)
5
4
3
2
VS = –30V
VS = +30V
VS = –55V
VS = +55V
20
–60
–80
–100
–120
0
0
–40
40
60
80
100
120
TEMPERATURE (°C)
–140
1k
0
–20
5
100M
1G
VDD = +15V
VSS = –15V
TA = 25°C
–40
CROSSTALK (dB)
–60
–80
–100
VS = –30V
VS = +30V
VS = –55V
VS = +55V
–120
0
0
20
40
60
80
100
120
TEMPERATURE (°C)
–140
10k
100k
10M
1M
100M
1G
FREQUENCY (Hz)
Figure 20. Overvoltage Leakage Current vs. Temperature, 12 V Single Supply
13072-121
1
13072-118
LEAKAGE CURRENT (nA)
10M
ADJACENT CHANNELS
NONADJACENT CHANNELS, COMMON DRAIN
NONADJACENT CHANNELS, SEPARATE DRAIN
VDD = 12V
VSS = 0V
2
1M
Figure 22. Off Isolation vs. Frequency, ±15 V Dual Supply
6
3
100k
FREQUENCY (Hz)
Figure 19. Overvoltage Leakage Current vs. Temperature, ±20 V Dual Supply
4
10k
13072-120
1
13072-117
LEAKAGE CURRENT (nA)
VDD = +15V
VSS = –15V
TA = 25°C
–20
Figure 23. Crosstalk vs. Frequency, ±15 V Dual Supply
6
6
VDD = 36V
VSS = 0V
4
CHARGE INJECTION (pC)
4
3
2
VS = –30V
VS = +40V
VS = –40V
VS = +55V
20
0
–2
–4
–6
TA = 25°C
–8
0
0
2
40
60
80
TEMPERATURE (°C)
100
120
Figure 21. Overvoltage Leakage Current vs. Temperature, 36 V Single Supply
Rev. A | Page 20 of 34
VDD = 36V, VSS = 0V
VDD = 12V, VSS = 0V
–10
0
5
10
15
20
25
30
35
40
VS (V)
Figure 24. Charge Injection vs. Source Voltage (VS), Single Supply
13072-122
1
13072-119
LEAKAGE CURRENT (nA)
5
ADG5248F/ADG5249F
8
–9
6
–10
ADG5249F
ADG5248F
–11
4
–12
2
BANDWIDTH (dB)
CHARGE INJECTION (pC)
Data Sheet
0
–2
–4
–13
–14
–15
–16
–17
–6
–8
–18
VDD = +20V, VSS = –20V
–15
–10
–5
0
5
10
15
20
VS (V)
VDD = +15V
VSS = –15V
TA = 25°C
–20
10k
13072-123
–10
–20
–19
VDD = +15V, VSS = –15V
100k
1M
10M
100M
1G
FREQUENCY (Hz)
13072-126
TA = 25°C
Figure 28. Bandwidth vs. Frequency
Figure 25. Charge Injection vs. Source Voltage (VS), Dual Supply
280
0
VDD = +15V
VSS = –15V
TA = 25°C
–20
260
VDD
VDD
VDD
VDD
= +12V,
= +36V,
= +15V,
= +20V,
VSS
VSS
VSS
VSS
= 0V
= 0V
= –15V
= –20V
240
tTRANSITION (ns)
ACPSRR (dB)
–40
–60
–80
220
190
180
–100
100k
1M
10M
100M
1G
FREQUENCY (Hz)
140
–40
13072-124
–120
10k
–20
20
40
60
80
100
120
100
120
TEMPERATURE (°C)
Figure 26. ACPSRR vs. Frequency, ±15 V Dual Supply
0.06
0
13072-127
160
Figure 29. tTRANSITION vs. Temperature
0.9
LOAD = 10kΩ
TA = 25°C
0.8
THRESHOLD VOLTAGE, VT (V)
0.05
0.03
VDD
VDD
VDD
VDD
0.02
= +12V,
= +36V,
= +15V,
= +20V,
VSS
VSS
VSS
VSS
= 0V, VS = +6V p-p
= 0V, VS = +18V p-p
= –15V, VS = +15V p-p
= –20V, VS = +20V p-p
0.6
0.5
0.4
0.3
0.2
0.01
0
0
5
10
15
FREQUENCY (kHz)
20
Figure 27. THD + N vs. Frequency
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 30. Threshold Voltage (VT) vs. Temperature
Rev. A | Page 21 of 34
13072-128
0.1
13072-125
THD + N (%)
0.04
0.7
ADG5248F/ADG5249F
Data Sheet
TA = 25°C
VDD = +10V
VSS = –10V
T
20
SIGNAL VOLTAGE (V p-p)
VS
POSFV
DRAIN
2
NEGFV
16
12
8
DISTORTIONLESS
OPERATING REGION
CH2 10V
CH4 10V
1µs
T
2.5GS/s A CH1
–10.0ns 100k POINTS
15.2V
0
13072-129
CH1 10V
CH3 10V
1
Figure 33. Large Signal Voltage Tracking vs. Frequency
Figure 31. Drain Output Response to Positive Overvoltage
T
POSF
DRAIN
2
NEGFV
CH2 10V
CH4 10V
1µs
T
2.5GS/s A CH1
–10.0ns 100k POINTS
–15.6V
13072-130
VS
CH1 10V
CH3 10V
10
FREQUENCY (MHz)
Figure 32. Drain Output Response to Negative Overvoltage
Rev. A | Page 22 of 34
100
13072-131
4
Data Sheet
ADG5248F/ADG5249F
TEST CIRCUITS
VDD = VSS = GND = 0V
ID
IS
Sx
A
D/Dx
A
13072-040
RL
10kΩ
VS
ADG5248F*
S1
NC
Figure 34. Switch Unpowered Leakage
ID
D/Dx
S8
A
A
VD
VS
|VS| > |VDD| OR |VSS|
NC = NO CONNECT
13072-039
RL
10kΩ
*SIMILAR CONNECTION FOR ADG5249F.
Figure 37. On Leakage
Figure 35. Switch Overvoltage Leakage
IS (OFF)
ADG5248F*
S1
V
ID (OFF)
D
A
Sx
S8
IDS
VS
VS
RON = V/IDS
13072-035
VD
*SIMILAR CONNECTION FOR ADG5249F.
D/Dx
Figure 36. Off Leakage
Figure 38. On Resistance
VSS
VDD
0.1µF
0.1µF
VDD
AUDIO
PRECISION
VSS
RS
Sx
VS
V p-p
Ax
D/Dx
VIN
RL
10kΩ
13072-042
GND
VOUT
Figure 39. THD + N
VDD
VSS
0.1µF
0.1µF
VDD
VSS
NETWORK
ANALYZER
S1/S1x
RL
50Ω
RL
50Ω
VOUT
D/Dx
S2/S2x
VS
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT
VS
Figure 40. Channel-to-Channel Crosstalk
Rev. A | Page 23 of 34
13072-038
A
13072-036
Sx
A
A
A
S2
13072-034
IS
ID (ON)
D
ADG5248F/ADG5249F
Data Sheet
VDD
VSS
0.1µF
VDD
NETWORK
ANALYZER
VSS
Sx
Ax
50Ω
50Ω
VS
D/Dx
VIN
RL
50Ω
GND
VOUT
VOUT
OFF ISOLATION = 20 log
VS
13072-037
0.1µF
Figure 41. Off Isolation
VSS
VDD
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
50Ω
Sx
Ax
VS
VIN
RL
50Ω
GND
INSERTION LOSS = 20 log
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
13072-041
D/Dx
Figure 42. Bandwidth
VDD VSS
0.1µF
0.1µF
POSFV
POSFV + 0.5V
SOURCE
VOLTAGE
(VS)
Sx
0V
tRESPONSE
OUTPUT
(VD)
VS
POSFV
OUTPUT × 0.5
NEGFV
0.1µF
VDD VSS
NEGFV
POSFV
0.1µF
VD
D/Dx
ADG5248F/
ADG5249F
CL
5pF
RL
1kΩ
OTHER SOURCE/
DRAIN PINS
GND
NOTES
1. THE OUTPUT PULLS TO VDD WITHOUT A 1kΩ RESISTOR (INTERNAL
40kΩ PULL-UP RESISTOR TO THE SUPPLY RAIL DURING A FAULT).
Figure 43. Overvoltage Response Time, tRESPONSE
Rev. A | Page 24 of 34
13072-043
0V
Data Sheet
ADG5248F/ADG5249F
VDD VSS
0.1µF
0.1µF
POSFV
POSFV + 0.5V
SOURCE
VOLTAGE
(VS)
VDD VSS
Sx
NEGFV
NEGFV
0.1µF
POSFV
0.1µF
VD
D/Dx
CL
5pF
VS
0V
ADG5248F/
ADG5249F
tRECOVERY
OUTPUT
(VD)
RL
1kΩ
OTHER SOURCE/
DRAIN PINS
POSFV × 0.5
GND
13072-044
0V
NOTES
1. THE OUTPUT STARTS FROM THE POSFV CLAMP LEVEL WITHOUT A 1kΩ RESISTOR
(INTERNAL 40kΩ PULL-UP RESISTOR TO THE POSFV SUPPLY RAIL DURING A FAULT).
Figure 44. Overvoltage Recovery Time, tRECOVERY
VDD VSS
0.1µF
0.1µF
NEGFV
0.1µF
POSFV + 0.5V
SOURCE
VOLTAGE
(VS)
VDD VSS
D/Dx
Sx
VS
0V
NEGFV
POSFV
POSFV
0.1µF
OTHER SOURCE/
DRAIN PINS
ADG5248F/
ADG5249F
tDIGRESP
xF
OUTPUT
(VxF)
CL*
12pF
0V
*INCLUDES TRACK CAPACITANCE
13072-058
GND
0.1VOUT
Figure 45. Interrupt Flag Response Time, tDIGRESP
VDD VSS
0.1µF
0.1µF
POSFV + 0.5V
SOURCE
VOLTAGE
(VS)
NEGFV
0.1µF
VDD VSS
Sx
VS
NEGFV
POSFV
POSFV
0.1µF
D/Dx
OTHER
SOURCE PINS
0V
ADG5248F/
ADG5249F
xF
tDIGREC
0.9VOUT
OUTPUT
(VxF)
GND
*INCLUDES TRACK CAPACITANCE
Figure 46. Interrupt Flag Recovery Time, tDIGREC
Rev. A | Page 25 of 34
13072-056
0V
CL*
12pF
ADG5248F/ADG5249F
Data Sheet
VDD VSS
0.1µF
0.1µF
POSFV + 0.5V
SOURCE
VOLTAGE
(VS)
NEGFV
0.1µF
VDD VSS
Sx
VS
0V
NEGFV
POSFV
POSFV
0.1µF
D/Dx
OTHER SOURCE/
DRAIN PINS
5V
RPULLUP
1kΩ
ADG5248F/
ADG5249F
tDIGREC
OUTPUT
xF
5V
CL*
12pF
3V
OUTPUT
(VxF)
13072-057
GND
0V
*INCLUDES TRACK CAPACITANCE
Figure 47. Interrupt Flag Recovery Time, tDIGREC, with a 1 kΩ Pull-Up Resistor
VSS
VDD
0.1µF
0.1µF
3V
VDD
ADDRESS
DRIVE (VIN)
VSS
A0
S1
VS
A1
VIN
0V
S2 TO S7
A2
S8
80%
ADG5248F*
80%
OUTPUT
2.0V
OUTPUT
D
EN
GND
1kΩ
35pF
13072-045
tD
*SIMILAR CONNECTION FOR ADG5249F.
Figure 48. Break-Before-Make Time Delay, tD
VDD
VSS
0.1µF
0.1µF
3V
VDD
ENABLE
DRIVE (VIN)
50%
VSS
A0
50%
S1
VS
A1
S2 TO S8
0V
A2
ADG5248F*
tOFF (EN)
OUTPUT
0.9VOUT
D
EN
OUTPUT
VIN
GND
1kΩ
35pF
0.1VOUT
*SIMILAR CONNECTION FOR ADG5249F.
Figure 49. Enable Delay, tON (EN), tOFF (EN)
Rev. A | Page 26 of 34
13072-046
tON (EN)
Data Sheet
ADG5248F/ADG5249F
VSS
VDD
0.1µF
3V
ADDRESS
DRIVE (VIN)
0.1µF
tr < 20ns
tf < 20ns
50%
VSS
VDD
50%
A0
S1
0V
VS1
A1
VIN
S2 TO S7
A2
tTRANSITION
tTRANSITION
VS8
S8
90%
ADG5248F*
2.0V
OUTPUT
OUTPUT
D
EN
GND
1kΩ
35pF
13072-047
90%
*SIMILAR CONNECTION FOR ADG5249F.
Figure 50. Address to Output Switching Time, tTRANSITION
VSS
VDD
0.1µF
0.1µF
VDD
3V
VSS
A0
A1
VIN
A2
ADG5248F*
QINJ = CL × ΔVOUT
ΔVOUT
S1
D
EN
GND
VS
VOUT
CL
1nF
VIN
*SIMILAR CONNECTION FOR ADG5249F.
Figure 51. Charge Injection, QINJ
Rev. A | Page 27 of 34
13072-048
VOUT
RS
ADG5248F/ADG5249F
Data Sheet
TERMINOLOGY
IDD
IDD represents the positive supply current.
tON (EN)
tON (EN) represents the delay between applying the digital
control input and the output switching on (see Figure 49).
ISS
ISS represents the negative supply current.
tOFF (EN)
tOFF (EN) represents the delay between applying the digital
control input and the output switching off (see Figure 49).
IPOSFV
IPOSFV represents the positive secondary supply current.
INEGFV
INEGFV represents the negative secondary supply current.
VD, VS
VD and VS represent the analog voltage on the D or Dx pins and
the Sx pins, respectively.
RON
RON represents the ohmic resistance between the D or Dx pins
and the Sx pins.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT(ON)
RFLAT(ON) is the flatness that is defined as the difference between
the maximum and minimum value of on resistance measured
over the specified analog signal range.
IS (Off)
IS (off) is the source leakage current with the switch off.
tD
tD represents the off time measured between the 90% points of
both switches when switching from one address state to
another.
tDIGRESP
tDIGRESP is the time required for the FF pin to go low (0.3 V),
measured with respect to the voltage on the source pin
exceeding the supply voltage by 0.5 V.
tDIGREC
tDIGREC is the time required for the FF pin to return high,
measured with respect to voltage on the Sx pin falling below the
supply voltage plus 0.5 V.
tRESPONSE
tRESPONSE represents the delay between the source voltage
exceeding the supply voltage by 0.5 V and the drain voltage
falling to 50% of its peak voltage.
ID (Off)
ID (off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (on) and IS (on) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
tRESPONSE (EN)
tRESPONSE (EN) represents the delay between the enable pin being
asserted and the drain reaching 90% of POSFV or NEGFV for a
switch that is in fault.
tRECOVERY
tRECOVERY represents the delay between an overvoltage on the Sx
pin falling below the supply voltage plus 0.5 V and the drain
voltage rising from 0 V to 50% of its voltage.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (on) and CS (on) represent the on switch capacitances, which
are measured with reference to ground.
CIN
CIN is the digital input capacitance.
tTRANSITION
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Channel-to-Channel Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
Rev. A | Page 28 of 34
Data Sheet
ADG5248F/ADG5249F
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. ACPSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pin to the output of the switch.
The dc voltage on the device is modulated by a sine wave of
0.62 V p-p.
VT
VT is the voltage threshold at which the overvoltage protection
circuitry engages (see Figure 30).
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
On Response
On response is the frequency response of the on switch.
Rev. A | Page 29 of 34
ADG5248F/ADG5249F
Data Sheet
THEORY OF OPERATION
SWITCH ARCHITECTURE
Each channel of the ADG5248F/ADG5249F consists of a parallel
pair of N-channel DMOS (NDMOS) and P-channel DMOS
(PDMOS) transistors. This construction provides excellent
performance across the signal range. The ADG5248F/ADG5249F
channels operate as standard switches when input signals with a
voltage between POSFV and NEGFV are applied. For example,
the on resistance is 250 Ω typically and opening or closing the
switch is controlled using the appropriate address pins.
Additional internal circuitry enables the switch to detect
overvoltage inputs by comparing the voltage on a source pin
(Sx) with POSFV and NEGFV. A signal is considered
overvoltage if it exceeds these secondary supply voltages by the
voltage threshold, VT. The threshold voltage is typically 0.7 V, but
can range from 0.8 V at −40°C down to 0.6 V at +125°C. See
Figure 30 to see the change in VT with operating temperature.
The maximum voltage that can be applied to any source input is
+55 V or −55 V. When the device is powered using a single supply
of 25 V or greater, the maximum negative signal level is reduced. It
reduces from −55 V at VDD = +25 V to −40 V at VDD = +40 V to
remain within the 80 V maximum rating. Construction of the
process allows the channel to withstand 80 V across the switch
when it is opened. These overvoltage limits apply whether the
power supplies are present or not.
POSFV
ESD
PROTECTION
ESD
Sx
D/Dx
ESD
Ax
SWITCH
DRIVER
LOGIC
BLOCK
NEGFV
When an overvoltage event occurs, the channels undisturbed by
the overvoltage input continue to operate normally without
additional crosstalk.
ESD Performance
The drain pins have ESD protection diodes to the secondary
supply rails and the voltage at these pins must not exceed the
secondary supply voltages, POSFV and NEGFV. The source
pins have specialized ESD protection that allows the signal voltage
to reach ±55 V regardless of supply voltage level. Exceeding
±55 V on any source input may damage the ESD protection
circuitry on the device. See Figure 52 for an overview of the
switch channel.
Trench Isolation
In the ADG5248F and ADG5249F, an insulating oxide layer
(trench) is placed between the NDMOS and the PDMOS
transistors of each switch. Parasitic junctions, which occur
between the transistors in junction isolated switches, are
eliminated, and the result is a switch that is latch-up immune
under all circumstances.
13072-049
FAULT
DETECTOR
During overvoltage conditions, the leakage current into and out
of the source pins is limited to tens of microamperes. If the
source pin is unselected, only nanoamperes of leakage appear
on the drain pin. However, if the source is selected, the pin is
pulled to the supply rail. The device that pulls the drain pin to
the rail has an impedance of approximately 40 kΩ; thus, the D
or Dx pin current is limited to approximately 1 mA during a
shorted load condition. This internal impedance also determines
the minimum external load resistance required to ensure that
the drain pin is pulled to the desired voltage level during a fault.
NDMOS
PDMOS
P-WELL
N-WELL
Figure 52. Switch Channel and Control Function
Rev. A | Page 30 of 34
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 53. Trench Isolation
13072-050
When an overvoltage condition is detected on a source pin (Sx),
the switch automatically opens regardless of the digital logic
state. The source pin becomes high impedance and ensures that
no current flows through the switch. If a source pin is selected
that is in fault, the drain pin is pulled to the supply that was
exceeded. For example, if the source voltage exceeds POSFV, the
drain output pulls to POSFV. If the source voltage exceeds NEGFV,
the drain output pulls to NEGFV. In Figure 31, the voltage on the
drain pin can be seen to follow the voltage on the source pin
until the switch turns off completely. The drain pin then pulls to
GND due to the 1 kΩ load resistor; otherwise, it pulls to the
POSFV supply. The maximum voltage on the drain is limited by
the internal ESD diodes, and the rate at which the output
voltage discharges is dependent on the load at the pin.
ADG5248F/ADG5249F
Power-On Protection
The following conditions must be satisfied for the switch to be
in the on condition:
•
•
•
•
The primary supply must be VDD to VSS ≥ 8 V
For POSFV, the secondary supply must be between 4.5 V
and VDD, and for NEGFV, the secondary supply must be
between VSS and 0 V
The input signal must be between NEGFV − VT and
POSFV + VT
The digital logic control input has selected the switch
When the switch is turned on, signal levels up to the secondary
supply rails are passed.
The switch responds to an analog input that exceeds POSFV or
NEGFV by a threshold voltage, VT, by turning off. The absolute
input voltage limits are −55 V and +55 V, while maintaining an
80 V limit between the source pin and the supply rails. The
switch remains off until the voltage at the source pin returns to
between POSFV and NEGFV.
The fault response time (tRESPONSE) when powered by a ±15 V dual
supply is typically 90 ns and the fault recovery time (tRECOVERY) is
745 ns. These vary with supply voltages and output load conditions.
The maximum stress across the switch channel is 80 V; therefore,
the user must pay close attention to this limit under a fault
condition.
For example, consider the case where the device is set up in a
multiplexer configuration as shown in Figure 54.
•
•
•
•
VDD/VSS and POSFV/NEGFV= ±22 V, S1 = +22 V, S1 is
selected
S2 has a −55 V fault and S3 has a +55 V fault
The voltage between S2 and D = +22 V − (−55 V) = +77 V
The voltage between S3 and D = 55 V− 22 V = 33 V
These calculations are all within device specifications: a 55 V
maximum fault on the source inputs and a maximum of 80 V
across the off switch channel.
+22V
‒55V
+55V
S1
0V
–22V
VDD GND VSS
ADG5248F
S2
S3
D
S8
1-OF-8
DECODER
A0
A1
0V
+5V
A2
EN
13072-051
POSFV and NEGFV are required secondary power supplies that
set the level at which the overvoltage protection is engaged. POSFV
can be supplied from 4.5 V to VDD, and NEGFV can be supplied
from VSS to 0 V. If a secondary supply is not available, the POSFV
and NEGFV pins must be connected to VDD (POSFV) and VSS
(NEGFV). The overvoltage protection then engages at the primary
supply voltages. When the voltages at the source inputs exceed
POSFV or NEGFV by VT, the switch turns off or, if the device is
unpowered, the switch remains off. The switch input remains high
impedance regardless of the digital input state and if it is selected,
the drain pulls to either POSFV or NEGFV. Signal levels up to
+55 V and −55 V are blocked in both the powered and unpowered
condition as long as the 80 V limitation between the source and
supply pins is met.
POSFV
+22V
USER DEFINED FAULT PROTECTION
NEGFV
Data Sheet
Figure 54. ADG5248F in an Overvoltage Condition
Power-Off Protection
When no power supplies are present, the switch remains in the
off condition, and the switch inputs are high impedance. This
state ensures that no current flows and prevents damage to the
switch or downstream circuitry. The switch output is a virtual
open circuit.
The switch remains off regardless of whether the VDD and VSS
supplies are 0 V or floating. A GND reference must always be
present to ensure proper operation. Signal levels of up to ±55 V
are blocked in the unpowered condition.
Digital Input Protection
The ADG5248F and the ADG5249F can tolerate digital input
signals being present on the device without power. When the
device is unpowered, the switch is guaranteed to be in the off
state, regardless of the state of the digital logic signals.
The digital inputs are protected against positive faults of up to
44 V. The digital inputs do not offer protection against negative
overvoltages. ESD protection diodes connected to GND are
present on the digital inputs.
Overvoltage Interrupt Flag
The voltages on the source inputs of the ADG5248F and
ADG5249F are continuously monitored, and the state of the
switches is indicated by an active low digital output pin, FF.
The voltage on the FF pin indicates if any of the source input
pins are experiencing a fault condition. The output of the FF pin
is a nominal 3 V when all source pins are within normal
operating range. If any source pin voltage exceeds the secondary
supply voltage by VT, the FF output reduces to below 0.8 V.
Use the specific fault digital output pin, SF, to decode which
inputs are experiencing a fault condition. The SF pin reduces to
below 0.8 V when a fault condition is detected on a specific pin,
depending on the state of the F0, F1, and F2 pins (see Table 9
and Table 12).
Rev. A | Page 31 of 34
ADG5248F/ADG5249F
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY RAILS
To guarantee correct operation of the device, 0.1 µF decoupling
capacitors are required on the primary and secondary supplies.
If they are driven from the same supply, one set of 0.1 µF
decoupling capacitors is sufficient.
POWER SUPPLY RECOMMENDATIONS
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
An example of a bipolar power solution is shown in Figure 55.
The ADP7118 and ADP7182 can be used to generate clean positive
and negative rails from the ADP5070 (dual switching regulator)
output. These rails can power the ADG5248F, the ADG5249F, an
amplifier, and/or a precision converter in a typical signal chain.
+16V
The secondary supplies (POSFV and NEGFV) provide the
current required to operate the fault protection and, thus, must
be low impedance supplies. Therefore, they can be derived from
the primary supplies by using a resistor divider and buffer.
ADP7118
LDO
12V
INPUT
+15V
ADP5070
–16V
ADP7182
LDO
–15V
Figure 55. Bipolar Power Solution
The secondary supply rails (POSFV and NEGFV) must not
exceed the primary supply rails (VDD and VSS) because this may
lead to a signal passing through the switch unintentionally.
Table 13. Recommended Power Management Devices
The ADG5248F and the ADG5249F can operate with bipolar
supplies between ±5 V and ±22 V. The supplies on VDD and VSS
need not be symmetrical but the VDD to VSS range must not exceed
44 V. The ADG5248F and the ADG5249F can also operate with
single supplies between 8 V and 44 V with VSS connected to GND.
ADP7118
ADP7142
ADP7182
The ADG5248F and ADG5249F devices are fully specified at
±15 V, ±20 V, +12 V, and +36 V supply ranges.
POWER SUPPLY SEQUENCING PROTECTION
The switch channel remains open when the devices are unpowered
and signals from −55 V to +55 V can be applied without damaging
the devices. The switch channel closes only when the supplies are
connected, a suitable digital control signal is placed on the address
pins, and the signal is within normal operating range. Placing
the ADG5248F/ADG5249F between external connectors and
sensitive components offers protection in systems where a signal is
presented to the source pins before the supply voltages are available.
13072-052
The overvoltage protected family of switches and multiplexers
provides robust solutions for instrumentation, industrial,
automotive, aerospace, and other harsh environments where
overvoltage signals can be present and the system must remain
operational both during and after the overvoltage has occurred.
Product
ADP5070
Description
1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
20 V, 200 mA, low noise, CMOS LDO
40 V, 200 mA, low noise, CMOS LDO
−28 V, −200 mA, low noise, linear regulator
HIGH VOLTAGE SURGE SUPPRESSION
The ADG5248F/ADG5249F are not intended for use in very
high voltage applications. The maximum operating voltage of
the transistor is 80 V. In applications where the inputs are likely
to be subject to overvoltages exceeding the breakdown voltage,
use transient voltage suppressors (TVSs) or similar.
SIGNAL RANGE
The primary supplies define the on-resistance profile of the
channel, whereas the secondary supplies define the signal range.
Using voltages on POSFV and NEGFV that are lower than VDD
and VSS, the required signal can benefit from the flat on resistance
in the center of the full signal capabilities of the device.
Rev. A | Page 32 of 34
Data Sheet
ADG5248F/ADG5249F
INTELLIGENT FAULT DETECTION
The ADG5248F and ADG5249F digital output pin, FF, can
interface with a microprocessor or control system and can be
used as an interrupt flag. This feature provides real-time
diagnostic information on the state of the device and the system
to which it connects.
The control system can use the digital interrupt, FF, to start a
variety of actions, as follows:
•
•
•
Initiating an investigation into the source of an overvoltage
fault.
Shutting down critical systems in response to the overvoltage
condition.
Using data recorders to mark data during these events as
unreliable or out of specification.
For systems sensitive during a start-up sequence, the active
low operation of the flag allows the system to ensure that the
ADG5248F or ADG5249F is powered on and that all input
voltages are within the normal operating range before initiating
operation.
The FF pin has a weak internal pull-up resistor, which allows
the signals to combine into a single interrupt for larger modules
that contain multiple devices.
The recovery time, tDIGREC, can be decreased from a typical 65 µs
to 900 ns by using a 1 kΩ pull-up resistor.
The specific fault digital output, SF, decodes which inputs are
experiencing a fault condition. The SF pin reduces to below
0.8 V when a fault condition is detected on a specific pin,
depending on the state of the F0, F1, and F2 pins (see Table 9
and Table 12). The specific fault feature also works with the
switches disabled (EN pin low), which allows the user to cycle
through and check the fault conditions without connecting the
fault to the drain output.
LARGE VOLTAGE, HIGH FREQUENCY SIGNALS
Figure 33 illustrates the voltage range and frequencies that the
ADG5248F/ADG5249F can reliably convey. For signals that
extend across the full signal range from VSS to VDD, keep the
frequency below 1 MHz. If the required frequency is greater
than 1 MHz, decrease the signal range appropriately to ensure
signal integrity.
Rev. A | Page 33 of 34
ADG5248F/ADG5249F
Data Sheet
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 56. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
0.30
0.25
0.18
0.50
BSC
PIN 1
INDICATOR
20
16
15
1
EXPOSED
PAD
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
11
10
5
6
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
2.75
2.60 SQ
2.35
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
020509-B
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 57. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG5248FBCPZ-RL7
ADG5248FBRUZ
ADG5248FBRUZ-RL7
ADG5249FBCPZ-RL7
ADG5249FBRUZ
ADG5249FBRUZ-RL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
20-Lead Lead Frame Chip Scale Package [LFCSP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Lead Frame Chip Scale Package [LFCSP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
Z = RoHS Compliant Part.
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13072-0-7/16(A)
Rev. A | Page 34 of 34
Package Option
CP-20-8
RU-20
RU-20
CP-20-8
RU-20
RU-20
工商网监
湘ICP备2023018690号
