ADN2905ACPZ

CPRI and 10G Ethernet Data Recovery IC with Amp/EQ from 614.4 Mbps to 10.3125 Gbps ADN2905 Data Sheet FEATURES GENERAL DESCRIPTION Serial CPRI data rates 614.4 Mbps, 1.2288 Gbps, 2.4576 Gbps, 3.072 Gbps, 4.9152 Gbps, 6.144 Gbps, and 9.8304 Gbps Ethernet data rates: 1.25 Gbps and 10.3125 Gbps No reference clock required Jitter performance superior to the SFF-8431 jitter specifications Optional equalizer or 0 dB EQ input mode Quantizer sensitivity: 200 mV p-p typical (equalizer mode) Sample phase adjust (5.65 Gbps or greater) Output polarity invert I2C to access optional features Loss of lock (LOL) indicator PRBS generator/detector Application aware power 349.5 mW at 9.8304 Gbps, 0 dB EQ input mode 287.7 mW at 6.144 Gbps, 0 dB EQ input mode 249.3 mW at 3.072 Gbps, 0 dB EQ input mode Power supply: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V 4 mm × 4 mm, 24-lead LFCSP The ADN2905 provides the receiver functions of quantization and multirate data recovery at 614.4 Mbps, 1.2288 Gbps, 1.25 Gbps, 2.4576 Gbps, 3.072 Gbps, 4.9152 Gbps, 6.144 Gbps, 9.8304 Gbps, and 10.3125 Gbps, used in Common Public Radio Interface (CPRI) and gigabit Ethernet applications. The ADN2905 automatically locks to all the specified CPRI and Ethernet data rates without the need for an external reference clock or programming. The ADN2905 jitter performance exceeds the jitter requirement specified by SFF-8431. The ADN2905 provides manual sample phase adjustment. Additionally, the user can select an equalizer or a 0 dB EQ as the input. The equalizer is either adaptive or can be manually set. The ADN2905 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. The ADN2905 is available in a compact 4 mm × 4 mm, 24-lead chip scale package (LFCSP). All ADN2905 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted. APPLICATIONS SFF-8431-compatible Ethernet: 10GE, 1GE, and CPRI: OS/L.6 up to OS/L.96 FUNCTIONAL BLOCK DIAGRAM SCK SDA LOL REFCLKP/ REFCLKN (OPTIONAL) DATOUTP/ DATOUTN ADN2905 I2C REGISTERS I2C_ADDR FREQUENCY ACQUISITION AND LOCK DETECTOR DATA RATE CML CLK TXD DDR FIFO SAMPLE PHASE ADJUST PIN 2 DATA INPUT SAMPLER 0dB EQ NIN 50Ω 50Ω I2C VCM ÷N DOWNSAMPLER AND LOOP FILTER ÷2 DCO RXD RXCK EQ I2C PHASE SHIFTER 12624-001 VCC CLOCK FLOAT Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADN2905 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 15 Applications ....................................................................................... 1 Functional Description .................................................................. 17 General Description ......................................................................... 1 Frequency Acquisition ............................................................... 17 Functional Block Diagram .............................................................. 1 Edge Select................................................................................... 17 Revision History ............................................................................... 2 Passive Equalizer ........................................................................ 18 Specifications..................................................................................... 3 0 dB EQ ........................................................................................ 18 Jitter Specifications ....................................................................... 4 Lock Detector Operation .......................................................... 18 Output and Timing Specifications ............................................. 5 Harmonic Detector .................................................................... 19 Timing Diagrams.......................................................................... 6 Output Disable and Squelch ..................................................... 19 Absolute Maximum Ratings ............................................................ 7 I2C Interface ................................................................................ 20 Thermal Characteristics .............................................................. 7 Reference Clock (Optional) ...................................................... 20 ESD Caution .................................................................................. 7 Additional Features Available via the I2C Interface ............... 22 Pin Configuration and Function Descriptions ............................. 8 Input Configurations ................................................................. 24 Typical Performance Characteristics ............................................. 9 DC-Coupled Application .......................................................... 26 2 I C Interface Timing and Internal Register Descriptions ......... 10 Outline Dimensions ....................................................................... 27 Register Map ............................................................................... 11 Ordering Guide .......................................................................... 27 REVISION HISTORY 1/16—Rev 0. to Rev. A Changes to Figure 5 .......................................................................... 8 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27 12/14—Revision 0: Initial Version Rev. A | Page 2 of 27 Data Sheet ADN2905 SPECIFICATIONS TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data pattern = PRBS 223 − 1, ac-coupled (to 100 Ω differential termination load), I2C register default settings, unless otherwise noted. Table 1. Parameter MULTIRATE SUPPORT RANGE INPUT—DC CHARACTERISTICS Peak-to-Peak Differential Input Input Resistance 0 dB EQ INPUT—CML COMPLIANT Input Voltage Range Input Common-Mode Level Differential Input Sensitivity CPRI × 16, 9.8304 Gbps EQUALIZER INPUT PATH Differential Input Sensitivity CPRI × 16, 9.8304 Gbps INPUT—AC CHARACTERISTICS S11 LOSS OF LOCK (LOL) DETECT Digital Control Oscillator (DCO) Frequency Error for LOL Assert DCO Frequency Error for LOL Deassert LOL Assert Response Time ACQUISITION TIME Lock to Data (LTD) Mode Optional LTR Mode 1 DATA RATE READBACK ACCURACY Coarse Readback Fine Readback POWER SUPPLY VOLTAGE VCC VDD VCC1 POWER SUPPLY CURRENT VCC VDD Test Conditions/Comments PIN – NIN, see Figure 29 Differential At PIN or NIN, dc-coupled, RX_TERM_FLOAT = 1 (floated) DC-coupled (see Figure 28), 600 mV p-p differential, RX_TERM_FLOAT = 1 (floated) Min 0.6144 Typ Max 10.3125 Unit Gbps 95 100 1.0 105 V Ω 0.5 VCC V 0.65 VCC − 0.15 V 250 mV p-p 15 inch FR-4, 100 Ω differential transmission line, adaptive EQ on BER = 1 × 10−12 200 mV p-p At 7.5 GHz, differential return loss, see Figure 8 −12 dB With respect to nominal, data collected in lock to reference (LTR) mode With respect to nominal, data collected in LTR mode 2.4576 Gbps 9.8304 Gbps 1000 ppm 250 51 18 ppm µs µs 2.4576 Gbps 9.8304 Gbps 0.5 0.5 6.0 ms ms ms ±5 ±100 % ppm AC-coupled, RX_TERM_FLOAT = 0 (VCM = 1.2 V), bit error rate (BER) = 1 × 10−12 In addition to reference clock accuracy 1.14 2.97 1.62 0 dB EQ input mode, clock output disabled 2.4576 Gbps 3.072 Gbps 4.9152 Gbps 6.144 Gbps 9.8304 Gbps 2.4576 Gbps 3.072 Gbps 4.9152 Gbps 6.144 Gbps 9.8304 Gbps Rev. A | Page 3 of 27 1.2 3.3 1.8 182.0 159.1 180.8 190.5 217.3 8.6 9.0 8.8 8.9 9.1 1.26 3.63 3.63 V V V mA mA mA mA mA mA mA mA mA mA ADN2905 Data Sheet Parameter VCC1 Test Conditions/Comments 2.4576 Gbps 3.072 Gbps 4.9152 Gbps 6.144 Gbps 9.8304 Gbps 0 dB EQ input mode, clock output disabled 2.4576 Gbps 3.072 Gbps 4.9152 Gbps 6.144 Gbps 9.8304 Gbps TOTAL POWER DISSIPATION OPERATING TEMPERATURE RANGE 1 Min Typ 31.7 16.2 31.8 16.1 32.8 Max Unit mA mA mA mA mA 305.7 249.3 304.5 287.7 349.5 −40 mW mW mW mW mW °C +85 This typical acquisition specification applies to all selectable reference clock frequencies in the range of 11.05 MHz to 176.8 MHz. JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data pattern = PRBS 223 − 1, ac-coupled to 100 Ω differential termination load, I2C register default settings, unless otherwise noted. Table 2. Parameter TRANSMITTER JITTERS Deterministic Jitter Random Jitter Duty Cycle Distortion Total Jitter Data Dependent Jitter Data Dependent Pulse Width Shrinkage Uncorrelated Jitter RECEIVER JITTERS Total Jitter Tolerance 99% Jitter Data Dependent Pulse Width Shrinkage Symbol Test Conditions/Comments T_DJ T_RJ T_DCD TJ DDJ DDPWS CPRI = 9.8304 Gbps, K28.5 + D5.6 and K28.5 + D16.2 CPRI = 9.8304 Gbps, K28.5 + D5.6 and K28.5 + D16.2 CPRI = 9.8304 Gbps, K28.5 + D5.6 and K28.5 + D16.2 SFF-8431, 64B/66B, 10.3125 Gbps SFF-8431, PRBS 29 − 1, 10.3125 Gbps SFF-8431, PRBS 29 − 1, 10.3125 Gbps 6.98 0.36 0.57 13.6 7.37 4.58 ps ps ps ps ps ps UJ SFF-8431, 64B/66B, 10.3125 Gbps 0.14 ps TJT J2 DDPWS SFF-8431, 10.3125 Gbps SFF-8431, 10.3125 Gbps SFF-8431, 10.3125 Gbps 82.4 55.5 33.7 ps ps ps Rev. A | Page 4 of 27 Min Typ Max Unit Data Sheet ADN2905 OUTPUT AND TIMING SPECIFICATIONS TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data pattern = PRBS 223 − 1, ac-coupled to 100 Ω differential termination load, I2C register default settings, unless otherwise noted. Table 3. Parameter CML OUTPUT CHARACTERISTICS Data Differential Output Swing Output Voltage High Low Symbol Test Conditions/Comments Min Typ Max Unit 9.8304 Gbps, DATA_SWING[3:0] = 0xC (default) 9.8304 Gbps, DATA_SWING[3:0] = 0xF (maximum) 9.8304 Gbps, DATA_SWING[3:0] = 0x4 (minimum) 535 668 189 600 724 219 672 771 252 mV p-p mV p-p mV p-p VOH DC-coupled V DC-coupled VCC − 0.025 VCC − 0.325 VCC VOL VCC − 0.05 VCC − 0.36 VCC − 0.29 V 17.4 22.2 17.5 23.9 32.6 28.3 33 29.2 0.5 0.5 0.5 0.5 46.5 33.1 49.1 33.7 ps ps ps ps UI UI UI UI CML OUTPUT TIMING CHARACTERISTICS Rise Time Fall Time Setup Time, Full Rate Clock Hold Time, Full Rate Clock Setup Time, DDR Mode Hold Time, DDR Mode I2C INTERFACE DC CHARACTERISTICS Input Voltage High Low Input Current Output Low Voltage I2C INTERFACE TIMING SCK Clock Frequency SCK Pulse Width High SCK Pulse Width Low Start Condition Hold Time Start Condition Setup Time Data Setup Time Data Hold Time SCK/SDA Rise/Fall Time 1 Stop Condition Setup Time Bus Free Time Between Stop and Start Conditions LVTTL DC INPUT CHARACTERISITICS (I2C_ADDR) Input Voltage High Low Input Current High Low LVTTL DC OUTPUT CHARACTERISITICS (LOS/LOL) Output Voltage High Low tS tH tS tH 20% to 80%, at 9.8304 Gbps, DATOUTN/DATOUTP 20% to 80%, at 9.8304 Gbps, CLKOUTN/CLKOUTP 80% to 20%, at 9.8304 Gbps, DATOUTN/DATOUTP 80% to 20%, at 9.8304 Gbps, CLKOUTN/CLKOUTP See Figure 2 See Figure 2 See Figure 3 See Figure 3 LVTTL VIH VIL VOL 2.0 VIN = 0.1 × VDD or VIN = 0.9 × VDD IOL = 3.0 mA See Figure 14 −10.0 0.8 +10.0 0.4 400 tHIGH tLOW tHD;STA tSU;STA tSU;DAT tHD;DAT tR/tF 600 1300 600 600 100 300 20 + 0.1Cb 600 1300 tSU;STO tBUF VIH VIL 300 0.8 VIN = 2.4 V VIN = 0.4 V VOH VOL IOH = 2.0 mA IOL = −2.0 mA 5 −5 Rev. A | Page 5 of 27 kHz ns ns ns ns ns ns ns ns ns 2.0 IIH IIL V V µA V 2.4 0.4 V V µA µA V V ADN2905 Data Sheet Parameter REFERENCE CLOCK CHARACTERISTICS Input Compliance Voltage (SingleEnded) Minimum Differential Input Drive Reference Frequency Required Accuracy 2 Symbol VCM Test Conditions/Comments Optional LTR mode No input offset, no input current, see Figure 21, ac-coupled input See Figure 21, ac-coupled, differential input Min Typ 0.55 Unit 1.0 V 176.8 mV p-p MHz ppm 100 11.05 AC-coupled, differential input Max 100 1 Cb is the total capacitance of one bus line in picofarads (pF). If mixed with high speed (HS) mode devices, faster rise/fall times are allowed (refer to the Philips I2C Bus Specification, Version 2.1). 2 Required accuracy in dc-coupled mode is guaranteed by design as long as the clock common-mode voltage output matches the reference clock commonmode voltage range. TIMING DIAGRAMS INT_CLKP tH 12624-002 tS DATOUTP/ DATOUTN Figure 2. Data to Clock Timing (Full Rate Clock Mode) INT_CLKP tH 12624-003 tS DATOUTP/ DATOUTN Figure 3. Data to Clock Timing (Half-Rate Clock/DDR Mode) DATOUTP VSE DATOUTN VDIFF 12624-004 VSE 0V DATOUTP – DATOUTN Figure 4. Single-Ended vs. Differential Output Amplitude Relationship Rev. A | Page 6 of 27 Data Sheet ADN2905 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 4. Parameter Supply Voltage (VCC = 1.2 V) Supply Voltage (VDD and VCC1 = 3.3 V) Maximum Input Voltage (REFCLKP/REFCLKN, NIN/PIN) Minimum Input Voltage (REFCLKP/REFCLKN, NIN/PIN) Maximum Input Voltage (SDA, SCK, I2C_ADDR) Minimum Input Voltage (SDA, SCK, I2C_ADDR) Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance Rating 1.26 V 3.63 V 1.26 V Thermal resistance is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages, for a 4-layer board with the exposed paddle soldered to VEE. VEE− 0.4 V Table 5. Thermal Resistance 3.63 V VEE − 0.4 V 125°C −65°C to +150°C 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Package Type 24-Lead LFCSP 1 2 3 θJA1 45 Junction to ambient. Junction to base. Junction to case. ESD CAUTION Rev. A | Page 7 of 27 θJB2 5 θJC3 11 Unit °C/W ADN2905 Data Sheet 20 SDA 19 SCK 22 I2C_ADDR 21 VCC 24 REFCLKP VCC 1 18 VCC PIN 2 17 VDD NIN 3 ADN2905 16 NC VEE 4 TOP VIEW (Not to Scale) 15 DATOUTP LOS 5 14 DATOUTN LOL 6 NC 11 VEE 12 NC 10 VDD 9 VEE 7 VCC1 8 13 VCC NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. EXPOSED PAD ON BOTTOM OF THE PACKAGE MUST BE CONNECTED TO VEE ELECTRICALLY. 12624-005 PIN 1 INDICATOR 23 REFCLKN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Mnemonic VCC PIN NIN VEE LOS LOL VEE VCC1 VDD NC NC VEE VCC DATOUTN DATOUTP NC VDD VCC SCK SDA VCC I2C_ADDR Type 1 P AI AI P DO DO P P P N/A N/A P P DO DO DI P P DI DIO P DI 23 24 N/A REFCLKN REFCLKP EPAD DI DI P 1 Description 1.2 V Supply for Limiting Amplifier. Positive Differential Data Input (CML). Negative Differential Data Input (CML). Ground for Limiting Amplifier. Loss of Signal Output (Active High). Loss of Lock Output (Active High). Digital Control Oscillator (DCO) Ground. 1.8 V to 3.3 V DCO Supply. 3.3 V High Supply. No Connect. Do not connect to this pin. Leave this pin floating No Connect. Do not connect to this pin. Leave this pin floating Ground for CML Output Drivers. 1.2 V Supply for CML Output Drivers. Negative Differential Retimed Data Output (CML). Positive Differential Retimed Data Output (CML). No Connect. Tie this pin to VEE (ground). 3.3 V High Supply. 1.2 V Core Digital Supply. Clock for I2C. Bidirectional Data for I2C. 1.2 V Core Supply. I2C Address Setting. Sets the device I2C address to 0x80 when I2C_ADDR = 0. Sets the device I2C address to 0x82 when I2C_ADDR = 1. Negative Reference Clock Input (Optional). Positive Reference Clock Input (Optional). Exposed Pad (VEE). The exposed pad on the bottom of the device package must be connected to VEE electrically. The exposed pad works as a heat sink. P is power, AI is analog input, DI is digital input, DO is digital output, DIO is digital input/output, and N/A is not applicable. Rev. A | Page 8 of 27 Data Sheet ADN2905 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VCC = 1.2 V, VCC1 = 1.8 V, VDD = 3.3 V, VEE = 0 V, input data pattern = PRBS 215 − 1, ac-coupled inputs and outputs, unless otherwise noted. 0 –5 LOG MAGNITUDE (dB) –10 –15 –20 –25 12624-006 –30 –40 1M 10M 100M 1G 10G 100G FREQUENCY (Hz) Figure 6. Output Eye Diagram at CPRI × 16 = 9.8304 Gbps, Time = 16.95 ps/div, Amplitude = 116 mV/div 12624-008 –35 Figure 8. Typical S11 Spectrum Performance 0.6 0.5 BER 0.4 0.3 0.2 TYPICAL ADAPTIVE EQ SETTING 0 0 2 4 6 8 EQ SETTING Figure 7. Output Eye Diagram at CPRI × 12 = 6.144 Gbps, Time = 27.13 ps/div, Amplitude = 118 mV/div 10 12 14 16 12624-009 12624-007 0.1 Figure 9. BER in Equalizer Mode vs. EQ Compensation at CPRI × 16 = 9.8304 Gbps (with a Signal of 400 mV p-p Differential, on 15 inch FR4 Traces, with Variant EQ Compensation, Including Adaptive EQ) Rev. A | Page 9 of 27 ADN2905 Data Sheet I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTIONS R/W CTRL SLAVE ADDRESS[6:0] 0 0 0 0 x x 12624-010 0 1 MSB = 1 SET BY 0 = W PIN 22 1 = R Figure 10. Slave Address Configuration SLAVE ADDR, LSB = 0 (W) A(S) SUBADDR A(S) S SLAVE ADDR, LSB = 1 (R) A(S) DATA A(M) DATA A(M) P = STOP BIT A(M) = NO ACKNOWLEDGE BY MASTER A(M) = ACKNOWLEDGE BY MASTER P 12624-012 S S = START BIT A(S) = ACKNOWLEDGE BY SLAVE S SLAVE ADDR, LSB = 0 (W) A(S) SUBADDR A(S) DATA A(S) DATA A(S) P 12624-011 Figure 11. I2C Read Data Transfer Figure 12. I2C Write Data Transfer SDA SLAVE ADDRESS A6 SUBADDRESS A5 A7 STOP BIT DATA A0 D7 D0 SCK S WR ACK ACK SLAVE ADDR[4:0] ACK SUBADDR[6:1] DATA[6:1] Figure 13. I2C Data Transfer Timing tF tSU;DAT tHD;STA tBUF SDA tR tR tSU;STO tF tLOW tHIGH tHD;STA S tSU;STA S tHD;DAT Figure 14. I2C Interface Timing Diagram Rev. A | Page 10 of 27 P S 12624-014 SCK P 12624-013 START BIT Data Sheet ADN2905 REGISTER MAP Writing to register bits other than those clearly labeled is not recommended and may cause unintended results. Table 7. Internal Register Map 1, 2 Addr. (Hex) Default (Hex) 0x0 0x1 0x2 0x4 0x5 0x6 N/A N/A N/A N/A N/A N/A X X General Control CTRLA R/W 0x8 0x10 0 CTRLB R/W 0x9 0x08 SOFTWARE_ RESET INIT_FREQ _ACQ CDR bypass LOL config 1 CTRLC R/W 0xA 0x05 0 0 0 0 0 R/W 0xF 0x00 0 LOL data R/W R/W 0x10 0x13 0x1C 0x02 0 0 0 0 R/W R/W 0x14 0x16 0x00 0x08 0 RX_TERM_ FLOAT 0 0 INPUT_SEL[1:0] 0 ADAPTIVE_ EQ_EN Output Control OUTPUTA R/W 0x1E 0x00 0 0 Data squelch DATA_SWING[3:0] DATOUT_ DISABLE Reg. Name R/W Readback/Status FREQMEAS0 R FREQMEAS1 R FREQMEAS2 R FREQ_RB1 R FREQ_RB2 R STATUSA R FLL Control LTR_MODE DPLL Control DPLLA DPLLD Phase LA_EQ D7 D6 D5 D4 D3 FULLRATE X FREQ0[7:0] (RATE_FREQ[7:0]) FREQ1[7:0] (RATE_FREQ[15:8]) FREQ2[7:0] (RATE_FREQ[23:16]) VCOSEL[7:0] DIVRATE[3:0] Reserved LOL status Reserved Static LOL CDR_MODE[2:0] 0 FREF_RANGE[1:0] 0 0 OUTPUTB PRBS Control PRBS Gen 1 R/W 0x1F 0xCC R/W 0x39 0x00 0 0 DATA_ CID_BIT PRBS Gen 2 PRBS Gen 3 PRBS Gen 4 PRBS Gen 5 PRBS Gen 6 PRBS Rec 1 R/W R/W R/W R/W R/W R/W 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x00 0x00 0x00 0x00 0x00 0x00 0 0 0 PRBS Rec 2 PRBS Rec 3 PRBS Rec 4 PRBS Rec 5 PRBS Rec 6 PRBS Rec 7 R R R R R R 0x40 0x41 0x42 0x43 0x44 0x45 0x00 0x00 N/A N/A N/A N/A 0 D2 D1 X D0 VCOSEL[9:8] RATE_MEAS_ COMP Reset static LOL Reserved RATE_ MEAS_EN 0 RATE_MEAS_ RESET 0 REFCLK_ PDN 0 1 DATA_TO_REF_RATIO[3:0] EDGE_SEL[1:0] 0 1 DATA_ 0 CID_EN DATA_CID_LENGTH[7:0] PROG_DATA[7:0] PROG_DATA[15:8] PROG_DATA[23:16] PROG_DATA[31:24] DATA_ 0 RECEIVER_ CLEAR PRBS_ERROR_COUNT[7:0] TRANBW[2:0] Reserved DLL_SLEW[1:0] to 0 SAMPLE_PHASE[3:0] EQ_BOOST[3:0] DDR_ DISABLE DATA_ POLARITY Reserved DATA_ GEN_EN DATA_ RECEIVER_ ENABLE Reserved DATA_GEN_MODE[1:0] DATA_RECEIVER_ MODE[1:0] PRBS_ERROR DATA_LOADED[7:0] DATA_LOADED[15:8] DATA_LOADED[23:16] DATA_LOADED[31:24] Rev. A | Page 11 of 27 ADN2905 Reg. Name ID/Revision REV ID HI_CODE LO_CODE 1 2 Data Sheet R/W Addr. (Hex) Default (Hex) R R R R 0x48 0x49 0x20 0x21 0x54 0x15 0xAD 0x63 D7 D6 D5 D4 D3 D2 D1 D0 Rev[7:0] ID[7:0] Reserved Reserved X means don’t care. N/A means not applicable. Table 8. Status Register, STATUSA (Address 0x6) Bit(s) D5 D4 Bit Name Reserved LOL status D3 D2 Reserved Static LOL D0 RATE_MEAS_COMP Bit Description X 0 = locked 1 = frequency acquisition mode X 0 = no LOL event since last reset 1 = LOL event since last reset; clear using the reset static LOL bit Rate measurement complete 0 = frequency measurement incomplete 1 = frequency measurement complete; clear using the RATE_MEAS_RESET bit Table 9. Control Register, CTRLA (Address 0x8) Bit(s) D7 [D6:D4] Bit Name Reserved CDR_MODE[2:0] D3 D2 Reserved Reset static LOL D1 D0 RATE_MEAS_EN RATE_MEAS_RESET Bit Description Reserved to 0. CDR modes. 000 = lock to data (LTD). 010 = lock to reference (LTR). 001, 011 = reserved. Reserved to 0. In factory default mode, this bit is set to 0. In the static LOL mode, write 1 and then write 0 to clear static LOL bit (D2 of the status register). Fine data rate measurement enable. Set to 1 to initiate a rate measurement. Rate measurement reset. Set to 1 to clear a rate measurement. Table 10. Control Register, CTRLB (Address 0x9) Bit(s) D7 D6 Bit Name SOFTWARE_RESET INIT_FREQ_ACQ D5 CDR bypass D4 LOL config D3 D2 [D1:D0] Reserved Reserved Reserved Bit Description Software reset. Write a 1 followed by a 0 to reset the device. Initiate frequency acquisition. Write a 1 followed by a 0 to initiate a frequency acquisition (optional). CDR bypass. 0 = CDR enabled. 1 = CDR bypassed. LOL configuration. 0 = normal LOL. 1 = static LOL. Reserved to 1. Reserved to 0. Reserved to 0. Rev. A | Page 12 of 27 Data Sheet ADN2905 Table 11. Control Register, CTRLC (Address 0xA) Bit(s) [D7:D3] D2 D1 D0 Bit Name Reserved REFCLK_PDN Reserved Reserved Bit Description Reserved to 0. Reference clock power-down. Write a 0 to enable the reference clock. Reserved to 0. Reserved to 1. Table 12. Lock to Reference Clock Mode Programming Register, LTR_MODE 1 (Address 0xF) Bit(s) D7 D6 Bit Name Reserved LOL data [D5:D4] FREF_RANGE[1:0] [D3:D0] DATA_TO_REF_RATIO[3:0] 1 Bit Description Reserved to 0 LOL data 0 = CLK vs. reference clock during tracking 1 = CLK vs. data during tracking fREF range 00 = 11.05 MHz to 22.1 MHz 01 = 22.1 MHz to 44.2 MHz 10 = 44.2 MHz to 88.4 MHz 11 = 88.4 MHz to 176.8 MHz Data to reference ratio 0000 = ½ 0001 = 1 0010 = 2 N = 2(n − 1) 1010 = 512 Where DIV_fREF is the divided down reference referred to the 11.05 MHz to 22.1 MHz band (see the Reference Clock (Optional) section). Data Rate/2(LTR_MODE[3:0] − 1) = REFCLK/2LTR_MODE[5:4] Table 13. DPLL Control Register, DPLLA (Address 0x10) Bit(s) [D7:D5] [D4:D3[ Bit Name Reserved EDGE_SEL[1:0] [D2:D0] TRANBW[2:0] Bit Description Reserved to 0. Edge for phase detection. See the Edge Select section for further details. 00 = rising and falling edge data. 01 = rising edge data. 10 = falling edge data. 11 = rising and falling edge data. Transfer bandwidth. Scales transfer bandwidth. Default value is 4, resulting in the CPRI × 16: 9.8304 Gbps default BW shown in Table 2. See the Transfer Bandwidth section for further details. Transfer BW = Default Transfer BW × (TRANBW[2:0]/4) Table 14. DPLL Control Register, DPLLD (Address 0x13) Bit(s) [D7:D2] [D1:D0] Bit Name Reserved DLL_SLEW[1:0] Bit Description Reserved to 0. DLL slew. Sets the BW of the DLL. See the DLL Slew section for further details. Table 15. Phase Control Register, Phase (Address 0x14) Bit(s) [D7:D4] [D3:D0] Bit Name Reserved SAMPLE_PHASE[3:0] Bit Description Reserved to 0. Adjusta the phase of the sampling instant for data rates above 5.65 Gbps in steps of 1/32 UI. This register is in twos complement notation. See the Sample Phase Adjust section for further details. Rev. A | Page 13 of 27 ADN2905 Data Sheet Table 16. Input Stage Programming Register, LA_EQ (Address 0x16) Bit(s) D7 Bit Name RX_TERM_FLOAT [D6:D5] INPUT_SEL[1:0] D4 ADAPTIVE_EQ_EN [D3:D0] EQ_BOOST[3:0] Bit Description Receiver (Rx) termination float. 0 = termination common-mode driven. 1 = termination common-mode floated. Input stage select. 01 = equalizer. 10 = 0 dB EQ mode. 00, 11 = undefined. Enable adaptive EQ. 0 = manual EQ control. 1 = adaptive EQ enabled. Equalizer gain. These bits set the EQ gain. See the Passive Equalizer section for further details. Table 17. Output Control Register, OUTPUTA (Address 0x1E) Bit(s) [D7:D6] D5 Bit Name Reserved Data squelch D4 DATOUT_DISABLE D3 D2 Reserved DDR_DISABLE D1 DATA_POLARITY D0 Reserved Bit Description Reserved to 0 Squelch 0 = normal data 1 = squelch data Data output disable 0 = data output enabled 1 = data output disabled Reserved to 1 Double data rate 0 = DDR clock enabled 1 = DDR clock disabled Data polarity 0 = normal data polarity 1 = flip data polarity Reserved to 0 Table 18. Output Swing Register, OUTPUTB (Address 0x1F) Bit(s) [D7:D4] Bit Name DATA_SWING[3:0] [D3:D0] Reserved Bit Description Adjust data output amplitude. Step size is approximately 50 mV differential. Default register value is 0xCH. Typical differential data output amplitudes are 0x1 to 0x3 = invalid. 0x4 = 200 mV. 0x5 = 250 mV. 0x6 = 300 mV. 0x7 = 345 mV. 0x8 = 390 mV. 0x9 = 440 mV. 0xA = 485 mV. 0xB = 530 mV. 0xC = 575 mV. 0xD = 610 mV. 0xE = 640 mV. 0xF = 655 mV. Default = 0xCH. Rev. A | Page 14 of 27 Data Sheet ADN2905 THEORY OF OPERATION The ADN2905 implements a data recovery for CPRI data rates from 614.4 Mbps to 9.8304 Gbps. The front end is configurable to either equalize or 0 dB EQ the nonreturn-to-zero (NRZ) input waveform to full-scale digital logic levels, or to pass a full digital logic signal. The user can choose from two input stages to process the data: a high-pass passive equalizer with up to 10 dB of boost at 5 GHz, or 0 dB EQ mode with approximately 250 mV p-p sensitivity at CPRI rate 9.8304 Gbps. When the input signal is corrupted due to FR-4 or other impairments in the printed circuit board (PCB) traces, a passive equalizer can be one of the signal integrity options. The equalizer high frequency boost is configurable through the I2C registers, in place of the factory default settings. A user enabled adaptation is included that automatically adjusts the equalizer to achieve the widest eye opening. The equalizer can be manually set for any data rate, but adaptation is available only at data rates greater than 5.5 Gbps. When a signal is presented to the data recovery, the ADN2905 acts as a delay-locked and phase-locked loop (PLL) circuit for clock recovery and data retiming from an NRZ encoded data stream. Input data is sampled by a high speed clock. A digital downsampler accommodates data rates spanning three orders of magnitude. Downsampled data is applied to a binary phase detector. The phase of the input data signal is tracked by two separate feedback loops. A high speed, delay-locked loop (DLL) path cascades a digital integrator with a digitally controlled phase shifter on the digital control oscillator (DCO) clock to track the high frequency components of jitter. A separate phase control loop, composed of a digital integrator and DCO, tracks the low frequency components of jitter. The initial frequency of the DCO is set by a third loop that compares the DCO frequency with the input data frequency. This third loop also sets the decimation ratio of the digital downsampler. The delay-locked and phase-locked loops together track the phase of the input data. For example, when the clock lags the input data, the phase detector drives the DCO to a higher frequency and decreases the delay of the clock through the phase shifter; both of these actions reduce the phase error between the clock and data. Because the loop filter is an integrator, the static phase error is driven to zero. Another view of the circuit is that the phase shifter implements the zero required for frequency compensation of a second-order phase-locked loop, and this zero is placed in the feedback path and, therefore, does not appear in the closed-loop transfer function. Because this circuit has no zero in the closed-loop transfer, jitter peaking is eliminated. The delay-locked and phase-locked loops simultaneously provide wideband jitter accommodation and narrow-band jitter filtering. The simplified block diagram in Figure 15 shows that Z(s)/X(s) is a second-order, low-pass jitter transfer function that provides excellent filtering. The low frequency pole is formed by dividing the gain of the PLL by the gain of the DLL, where the upsampling and zero-order hold in the DLL has a gain approaching N at the transfer bandwidth of the loop. Note that the jitter transfer has no zero, unlike an ordinary, second-order phaselocked loop, which means that the main PLL has no jitter peaking. This no jitter peaking feature makes the circuit ideal for signal regenerator applications where jitter peaking in a cascade of regenerators can contribute to hazardous jitter accumulation. The error transfer, e(s)/X(s), has the same high-pass form as an ordinary phase-locked loop up to the slew rate limit of the DLL with a binary phase detector. This transfer function is free to be optimized to give excellent wideband jitter accommodation because the jitter transfer function, Z(s)/X(s), provides the narrow-band jitter filtering. PHASE-LOCKED LOOP (PLL) X(s) N BINARY PHASE DETECTOR KPLL × TRANBW Z(s) KDCO s I – z–1 ÷N RECOVERED CLOCK DELAY-LOCKED LOOP (DLL) N I – z–N KDLL I – z–1 I – z–1 PSH ZERO-ORDER HOLD SAMPLE CLOCK Z(s) X(s) = KPLL × TRANBW – KDCO s × N × PSH × KDLL + KPLL × TRANBW × KDCO Figure 15. CDR Jitter Block Diagram Rev. A | Page 15 of 27 12624-015 INPUT DATA ADN2905 Data Sheet The delay-locked and phase-locked loops contribute to overall jitter accommodation. At low frequencies of input jitter on the data signal, the integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error. In this case, the oscillator is frequency modulated, and jitter is tracked as in an ordinary phase-locked loop. The amount of low frequency jitter that can be tracked is a function of the DCO tuning range. A wider tuning range provides more accommodation of low frequency jitter. The internal loop control word remains small for small jitter frequency, so that the phase shifter remains close to the center of its range and, therefore, contributes little to the low frequency jitter accommodation. At medium jitter frequencies, the gain and tuning range of the DCO are not large enough to track input jitter. In this case, the DCO control word becomes large and saturates. As a result, the DCO frequency remains at an extreme of its tuning range. The size of the DCO tuning range, therefore, has only a small effect on the jitter accommodation.The delay-locked loop control range is larger; therefore, the phase shifter tracks the input jitter. An infinite range phase shifter is used on the clock. Consequently, the minimum range of timing mismatch between the clock at the data sampler and the retiming clock at the output is limited by the depth of the FIFO to 32 UI. There are two ways to acquire the data rate. The default mode is for the frequency to lock to the input data, where a finite state machine extracts frequency measurements from the data to program the DCO and loop division ratio so that the sampling frequency matches the data rate to within 250 ppm. The PLL is enabled, driving this frequency difference to 0 ppm. The second mode is to lock to reference (LTR), in which case the user provides a reference clock between 11.05 MHz and 176.8 MHz. Division ratios must be written to a serial port register. Rev. A | Page 16 of 27 Data Sheet ADN2905 FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION DLL Slew The ADN2905 acquires its frequency from the data over a range of data frequencies from 614.4 Mbps to 9.8304 Gbps. The lock detector circuit compares the frequency of the DCO and the frequency of the incoming data. When these frequencies differ by more than 1000 ppm, the LOL pin is asserted, and a new frequency acquisition cycle is initiated. The DCO frequency is reset to the lowest point of its range, and the internal division rate is set to its lowest value of N = 1, which is the highest octave of data rates. The frequency detector then compares this sampling rate frequency to the data rate frequency and either increases N by a factor of 2 if the sampling rate frequency is greater than the data rate frequency, or increases the DCO frequency if the data rate frequency is greater than the data sampling rate frequency. Initially, the DCO frequency is incremented in large steps to aid fast acquisition. As the DCO frequency approaches the data frequency, the step size is reduced until the DCO frequency is within 250 ppm of the data frequency, at which point LOL is deasserted. Jitter tolerance beyond the transfer bandwidth of the CDR is determined by the slew rate of the delay-locked loop implementing a delta modulator on phase. Setting DLL_SLEW[1:0] = 2, (the default value) in the Register 0x13 configures the DLL to track 0.75 UI p-p jitter at the highest frequency breakpoint at 4 MHz for CPRI = 9.8304 Gbps. DPLLD[1:0] can be set to 0, giving lower jitter generation on the recovered clock and better high frequency jitter tolerance. When LOL is deasserted, the frequency-locked loop is turned off. The PLL or DLL pulls in the DCO frequency until the DCO frequency equals the data frequency. EDGE SELECT A binary, or Alexander, phase detector drives both the DLL and PLL at all division rates. Duty cycle distortion on the received data leads to a dead band in the phase detector transfer function if phase errors are measured on both rising and falling data transitions. This dead band leads to jitter generation of unknown spectral composition with potentially large peak-to-peak amplitudee. The recommended usage of the device when the dc offset loop is disabled is to compute phase errors exclusively on either the rising data edges with EDGE_SEL[1:0] (Bits[D4:D3] in Register 0x10) = 1 (decimal) or on the falling data edges with EDGE_SEL[1:0] = 2. The alignment of the clock to the rising data edges with EDGE_ SEL[1:0] = 1 is represented by the top two curves in Figure 16. Duty cycle distortion with narrow 1s moves the significant sampling instance where data is sampled to the right of center. The alignment of the clock to the falling data edges with EDGE_ SEL[1:0] = 2 is represented by the first and third curves in Figure 16. The significant sampling instance moves to the left of center. Sample phase adjustment for rates above 5.65 Gbps can be used to move the significant sampling instance to the center of the narrow 1 (or narrow 0) for best jitter tolerance. DATA EDGE_SEL[1:0] 12624-016 CLK1 EDGE_SEL = 2 CLK2 Figure 16. Phase Detector Timing Sample Phase Adjustment The phase of the sampling instant can be adjusted using the I2C interface when the device operates at data rates of 5.65 Gbps or higher by writing to SAMPLE_PHASE[3:0] (Bits[D3:D0] in Register 0x14). This feature allows the user to adjust the sampling instant to improve the BER and jitter tolerance. Although the default sampling instant chosen by the CDR is sufficient in most applications, when dealing with some degraded input signals, the BER and jitter tolerance performance can be improved by manually adjusting the phase. A total adjustment range of 0.5 UI is available, with 0.25 UI in each direction, in increments of 1/32 UI. SAMPLE_PHASE[3:0] is a twos complement number. The relationship between data and the sampling clock is shown in Figure 17. Transfer Bandwidth The transfer bandwidth can be adjusted using the I2C interface by writing to the TRANBW[2:0] bitsin Register 0x10. The default value is 4. When set to values below 4, the transfer bandwidth is reduced. When set to values above 4, the transfer bandwidth is increased. The resulting transfer bandwidth (BW) is based on the following formula:  TRANBW[2:0]  Transfer BW = Default Transfer BW ×   4   For example, at CPRI × 16 (9.8304 Gbps), the default transfer bandwidth is approximately 2 MHz. The resulting transfer bandwidth when TRANBW[2:0] is changed is • • • • • • • TRANBW[2:0] = 1: transfer BW = 500 kHz TRANBW[2:0] = 2: transfer BW = 1.0 MHz TRANBW[2:0] = 3: transfer BW = 1.5 MHz TRANBW[2:0] = 4: transfer BW = 2.0 MHz (default) TRANBW[2:0] = 5: transfer BW = 2.5 MHz TRANBW[2:0] = 6: transfer BW = 3.0 MHz TRANBW[2:0] = 7: transfer BW = 3.5 MHz Reducing the transfer bandwidth is commonly used in optical transport network (OTN) applications. Never set TRANBW[2:0] to 0, because this makes the CDR open loop. Also note that setting TRANBW[2:0] above 4 can cause a slight increase in jitter generation and potential jitter peaking. Rev. A | Page 17 of 27 ADN2905 Data Sheet CLOCK PHASE = 4 PHASE = 7 PHASE = –4 PHASE = –8 PHASE = 0 (DEFAULT) 12624-017 DATA Figure 17. Data vs. Sampling Clock PASSIVE EQUALIZER 0 dB EQ A passive equalizer is available at the input to equalize large signals that have undergone distortion due to PCB traces, vias, or connectors. The adaptive EQ functions only at data rates greater than 5.5 Gbps. Therefore, at rates less than 5.5 Gbps, the EQ must be manually set. The 0 dB EQ path connects the input signal directly to the digital logic inside the ADN2905. The 0 dB EQ is useful at lower data rates where the signal is large (therefore, the limiting amplifier is not needed, and power can be saved by deselecting the limiting amplifier) and unimpaired (therefore, the equalizer is not needed). The signal swing of the internal digital circuit is 600 mV p-p differential, the minimum signal amplitude that must be provided in 0 dB EQ mode. The equalizer can be manually set using the LA_EQ register (Register 0x16). An adaptive loop is also available to optimize the EQ setting based on characteristics of the received eye at the phase detector. If the channel is known in advance, set the EQ manually to obtain the best performance; however, the adaptive EQ finds the best setting in most cases. Table 19 lists the typical EQ settings for several trace lengths. The values in Table 19 are based on measurements taken on a test board with simple FR-4 traces. Table 20 lists the typical maximum reach in inches of FR-4 of the EQ at several data rates. If a real channel includes lossy connectors or vias, the FR-4 reach length is lower. For any real-world system, it is highly recommended to test several EQ settings with the real channel to ensure the best signal integrity. Table 19. EQ Settings vs. Trace Length on FR-4 Trace Length (Inches) 6 10 15 20 to 30 Typical EQ Setting 10 12 14 15 Table 20. Typical EQ Reach on FR-4 vs. Maximum Data Rates Supported Maximum Data Rate (Gbps) 4 8 10 11 Typical EQ Reach on FR-4 (Inches) 30 20 15 10 In 0 dB EQ mode, the internal 50 Ω termination resistors can be configured in one of two ways, either floated or tied to VCC = 1.2 V (see Figure 22 and Table 23). By setting the RX_TERM_FLOAT bit (Bit D7 in Register 0x16) to 1, these 50 Ω termination resistors are floated internal to the ADN2905 (see Figure 25). By setting the RX_TERM_FLOAT bit to 0, these 50 Ω termination resistors are connected to VCC = 1.2 V (see Figure 26). In both termination cases, the user must ensure a valid common-mode voltage on the input. When the termination is floated, the two 50 Ω resistors are a purely differential termination. The input must conform to the range of signals shown in Figure 28. When the termination is connected to a 1.2 V VCC power supply (see Figure 26 and Figure 27), the common-mode voltage is created by the driver circuit and the 50 Ω resistors on the ADN2905. For example, the driver can be an open-drain switched current (see Figure 26), and the 50 Ω resistors return this current to VCC. In Figure 26, the common-mode voltage is created by both the current and the resistors. In this case, ensure that the current is a minimum of 6 mA, which gives a single-ended swing of 300 mV or a differential swing of 600 mV p-p differential, with VCM = 1.05 V (see Figure 28). The maximum current is 10 mA, which gives a single-ended 500 mV swing and a differential 1.0 V p-p swing with VCM = 0.95 V (see Figure 29). Another possibility is to back terminate the switched current driver, as shown in Figure 27, with the two VCC supplies having the same potential. In this example, the current is returned to VCC by the two 50 Ω resistors in parallel, or 25 Ω, so that the minimum current is 12 mA and the maximum current is 20 mA. LOCK DETECTOR OPERATION The lock detector on the ADN2905 has three modes of operation: normal mode, LTR mode, and static LOL mode. Rev. A | Page 18 of 27 Data Sheet ADN2905 Normal Mode In normal mode, the ADN2905 is a multiple rate data recovery device that locks onto the CPRI data rate from 614.4 Mbps to 9.8304 Gbps without the use of a reference clock as an acquisition aid. In this mode, the lock detector monitors the frequency difference between the DCO and the input data frequency, and deasserts the loss of lock signal, which appears on LOL (Pin 6) when the DCO is within 250 ppm of the data frequency. This enables the digital PLL (DPLL), which pulls the DCO frequency in the remaining amount and acquires phase lock. When locked, if the input frequency error exceeds 1000 ppm (0.1%), the loss of lock signal is reasserted and control returns to the frequency loop, which begins a new frequency acquisition. The LOL pin remains asserted until the DCO locks onto a valid input data stream to within 250 ppm frequency error. This hysteresis is shown in Figure 18. 0 250 1000 fDCO ERROR (ppm) 12624-018 –250 Writing a 1 to the LOL configuration bit (Bit D4 in Register 0x9) causes the LOL pin (Pin 6) to become a static LOL indicator. In this mode, the LOL pin mirrors the contents of the static LOL bit (Bit D2 in Register 0x6) and has the functionality described previously. The LOL configuration bit defaults to 0. In this mode, the LOL pin operates in the normal operating mode; that is, it is asserted only when the ADN2905 is in acquisition mode and deasserts when the ADN2905 has reacquired lock. HARMONIC DETECTOR LOL 1 –1000 asserted, even if the ADN2905 regains lock, until the static LOL bit (Bit D2 in Register 0x6) is manually reset. If a loss of lock condition occurs, this bit is internally asserted to logic high. The static LOL bit remains high even after the ADN2905 reacquires lock to a new data rate. This bit can be reset by writing a 1, followed by 0, to the reset static LOL bit (Bit D2 in Register 0x8). When reset, the static LOL bit remains deasserted until another loss of lock condition occurs. Figure 18. Transfer Function of LOL LOL Detector Operation Using a Reference Clock (LTR Mode) In lock to reference (LTR) mode, a reference clock is used as an acquisition aid to lock the ADN2905 DCO. LTR mode is enabled by setting the CDR_MODE[2:0] bits to 2 (Bits[D6:D4] in Register 0x8). The user must also write to the FREF_RANGE[1:0] bits and the DATA_TO_ REF_RATIO[3:0] bits (Bits[D5:D4] and Bits[D3:D0] in Register 0xF) to set the reference frequency range and the divide ratio of the data rate with respect to the reference frequency. Finally, the reference clock power down to the reference clock buffer must be deasserted by writing a 0 to the REFCLK_PDN bit (Bit D2 in Register 0xA). To maintain fastest acquisition, keep Bit D0 in Register 0xA set to 1. For more details, see the Reference Clock (Optional) section. In LTR mode, the lock detector monitors the difference in frequency between the divided down DCO and the divided down reference clock. The loss of lock signal, which appears on LOL (Pin 6), is deasserted when the DCO is within 250 ppm of the desired frequency. This enables the DPLL, which pulls in the DCO frequency by the remaining amount with respect to the input data and acquires phase lock. When locked, if the frequency error exceeds 1000 ppm (0.1%), the loss of lock signal is reasserted and control returns to the frequency loop, which reacquires lock with respect to the reference clock. The LOL pin remains asserted until the DCO frequency is within 250 ppm of the desired frequency. This hysteresis is shown in Figure 18. Static LOL Mode The ADN2905 implements a static LOL feature that indicates whether a loss of lock condition has ever occurred and remains The ADN2905 provides a harmonic detector that detects whether the input data has changed to a lower harmonic of the data rate than the one that the sampling clock is currently locked onto. For example, if the input data instantaneously changes from a CPRI × 16 (9.8304 Gbps) to a CPRI × 4 (2.4576 Gbps) bit stream, this can be perceived as a valid CPRI × 16 bit stream because the CPRI × 4 data pattern is exactly 4× slower than the CPRI × 16 pattern. Therefore, if the change in data rate is instantaneous, a 101 pattern at CPRI × 4 (2.4576 Gbps) is perceived by the ADN2905 as a 111100001111 pattern at CPRI × 16 (9.8304 Gbps). If the change to a lower harmonic is instantaneous, a typical inferior CDR may remain locked at the higher data rate. The ADN2905 implements a harmonic detector that automatically identifies whether the input data has switched to a lower harmonic of the data rate than the one that the DCO is currently locked onto. When a harmonic is identified, the LOL pin is asserted, and a new frequency acquisition is initiated. The ADN2905 automatically locks onto the new data rate, and the LOL pin is deasserted. The time to detect a lock to harmonic is 216 × (TD/ρ) where: 1/TD is the new data rate. For example, if the data rate is switched from CPRI × 16 (9.8304 Gbps) to CPRI × 4 (2.4576 Gbps), TD = 1/2.4576 GHz. ρ is the data transition density. Most coding schemes seek to ensure that ρ = 0.5, for example, PRBS and 8B/10B. When the ADN2905 is placed in lock to reference mode, the harmonic detector is disabled. OUTPUT DISABLE AND SQUELCH The ADN2905 offers output disable/squelch. The DATOUTP/ DATOUTN outputs can be disabled by setting the DATOUT_ DISABLE bit (Bit D4 in Register 0x1E) high. When an output is Rev. A | Page 19 of 27 ADN2905 Data Sheet I2C INTERFACE The ADN2905 supports a 2-wire, I2C-compatible, serial bus driving multiple peripherals. Two inputs, serial data (SDA) and serial clock (SCK), carry information between any devices connected to the bus. Each slave device is recognized by a unique address. The slave address consists of the seven MSBs of an 8-bit word. The upper six bits (Bits[6:1]) of the 7-bit slave address are factory programmed to 100000. The LSB of the slave address (Bit 0) is set by Pin 22, I2C_ADDR. The LSB of the word specifies either a read or write operation (see Figure 10). Logic 1 corresponds to a read operation, whereas Logic 0 corresponds to a write operation. To control the device on the bus, the following protocol must be used: 1. 2. 3. 4. The master initiates a data transfer by establishing a start condition, defined as a high to low transition on SDA while SCK remains high. This indicates that an address/data stream follows. All peripherals respond to the start condition and shift the next eight bits (the 7-bit address and the R/W bit). The bits are transferred from MSB to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. In the idle condition, the device monitors the SDA and SCK lines waiting for the start condition and the correct transmitted address. REFERENCE CLOCK (OPTIONAL) A reference clock is not required to perform data recovery with the ADN2905. However, support for an optional reference clock is provided. The reference clock can be driven differentially or single-ended. If the reference clock is not used, float both the REFCLKP and REFCLKN pins. Two 50 Ω series resistors present a differential load between REFCLKP and REFCLKN. Common mode is internally set to 0.56 × VCC by a resistor divider between VCC and VEE. See Figure 19, Figure 20, and Figure 21 for sample configurations. The reference clock input buffer accepts any differential signal with a peak-to-peak differential amplitude of greater than 100 mV. The phase noise and duty cycle of the reference clock are not critical, and a 100 ppm accuracy is sufficient. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADN2905 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. The ADN2905 has subaddresses to enable the user-accessible internal registers (see Table 7). The ADN2905, therefore, interprets the first byte as the device address and the second byte as the starting subaddress. Autoincrement mode is supported, allowing data to be read from or written to the starting subaddress and each subsequent address without manually addressing the subsequent subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all registers. Rev. A | Page 20 of 27 ADN2905 REFCLKP 24 BUFFER CLOCK REFCLKN 23 50Ω 50Ω VCC/2 12624-019 To set the data output while leaving the clock on, the output data can be squelched by setting the data squelch bit (Bit D5 in Register 0x1E) high. In this mode, the data driver remains powered, but the data itself is forced to be a value of 0 or 1, depending on the setting of the DATA_POLARITY bit (Bit D1 in Register 0x1E). Stop and start conditions can be detected at any stage of the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCK high period, issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If the user issues an invalid subaddress, the ADN2905 does not issue an acknowledge and returns to the idle condition. If the user exceeds the highest subaddress while reading back in auto-increment mode, the highest subaddress register contents continue to be output until the master device issues a no acknowledge. This indicates the end of a read. In a no acknowledge condition, the SDA line is not pulled low on the ninth pulse. See Figure 11 and Figure 12 for sample read and write data transfers, respectively, and Figure 13 for a more detailed timing diagram. Figure 19. DC-Coupled, Differential REFCLKx Configuration ADN2905 VCC CLK OSC OUT REFCLKP 24 BUFFER REFCLKN 23 50Ω 50Ω VCC/2 12624-020 disabled, it is fully powered down, saving approximately 30 mW total power. Figure 20. AC-Coupled, Single-Ended REFCLKx Configuration Data Sheet ADN2905 The user can specify a fixed integer multiple of the reference clock to lock onto using the DATA_TO_REF_RATIO[3:0] bits (Bits[D3:D0] in Register 0xF), as follows: ADN2905 REFCLKP 24 BUFFER REFCLK DATA_TO_REF_RATIO[3:0] = Data Rate ÷ DIV_fREF 23 50Ω 50Ω VCC/2 where DIV_fREF represents the divided-down reference referred to the 11.05 MHz to 22.1 MHz band. 12624-021 REFCLKN Figure 21. AC-Coupled, Differential REFCLKx Configuration The reference clock can be used either as an acquisition aid for the ADN2905 to lock onto data, or to measure the frequency of the incoming data to within 0.01%. The modes are mutually exclusive because, in the first use, the user can force the device to lock onto only a known data rate; in the second use, the user can measure an unknown data rate. Lock to reference mode is enabled by writing a 2 to the CDR_ MODE[2:0] bits (Bits[D6:D4] in Register 0x8). An on-chip clock buffer must be powered on by writing a 0 to the REFCLK_ PDN bit (Bit D2 in Register 0xA). Fine data rate readback mode is enabled by writing a 1 to the RATE_MEAS_EN bit (Bit D1 in Register 0x8). Enabling lock to reference and data rate readback at the same time causes an indeterminate state and is not supported. Using the Reference Clock to Lock onto Data In LTR mode, the ADN2905 locks onto a frequency derived from the reference clock according to the following equation: Data Rate/2(LTR_MODE[3:0] − 1) = REFCLK/2LTR_MODE[5:4] The user must know exactly what the data rate is and provide a reference clock that is a function of this rate. The ADN2905 can still be used as a continuous rate device in this configuration if the user can provide a reference clock that has a variable frequency (see the AN-632 Application Note). The reference clock can have a frequency from 11.05 MHz to 176.8 MHz. By default, the ADN2905 expects a reference clock of between 11.05 MHz and 22.1 MHz. If the reference clock is between 22.1 MHz and 44.2 MHz, 44.2 MHz and 88.4 MHz, or 88.4 MHz and 176.8 MHz, the user must configure the ADN2905 to use the correct reference frequency range by setting the two bits of FREF_RANGE[1:0] (Bits[D5:D4] in Register 0xF). Table 21. LTR_MODE Register Settings FREF_ RANGE[1:0] 00 01 10 11 Range (MHz) 11.05 to 22.1 22.1 to 44.2 44.2 to 88.4 88.4 to 176.8 DATA_TO_ REF_RATIO[3:0] 0000 0001 n 1010 Ratio 2−1 20 2n − 1 29 For example, if the reference clock frequency is 38.88 MHz and the input data rate is 622.08 Mbps, the FREF_RANGE[1:0] bits are set to 01 to give a divided-down reference clock of 19.44 MHz. DATA_TO_REF_RATIO[3:0] is set to 0110, that is, 6, because 622.08 Mbps/19.44 MHz = 2(6 − 1) If the ADN2905 is operating in lock to reference mode, and the user changes the reference frequency, the fREF range or the fREF ratio (Bits[D5:D4] or Bits[D3:D0], respectively, in Register 0xF), this change must be followed by writing a low to high to low transition to the INIT_FREQ_ACQ bit (Bit D6 in Register 0x9) to initiate a new lock to reference command. By default in lock to reference clock mode, when lock has been achieved and the ADN2905 is in tracking mode, the frequency of the DCO is compared to the frequency of the reference clock. If this frequency error exceeds 1000 ppm, lock is lost, LOL is asserted, and the device relocks to the reference clock while continuing to output a stable clock. An alternative configuration is enabled by setting LOL data (Bit D6 in Register 0xF) to 1. In this configuration, when the device is in tracking mode, the frequency of the DCO is compared to the frequency of the input data rather than the frequency of the reference clock. If this frequency error exceeds 1000 ppm, lock is lost, LOL is asserted, and the device relocks to the reference clock while continuing to output a stable clock. Using the Reference Clock to Measure Data Frequency The user can also provide a reference clock to measure the recovered data frequency. In this case, the user provides a reference clock, and the ADN2905 compares the frequency of the incoming data to the incoming reference clock and returns a ratio of the two frequencies to 0.01% (100 ppm). The accuracy error of the reference clock is added to the accuracy error of the ADN2905 data rate measurement. For example, if a 100 ppm accuracy reference clock is used, the total accuracy of the measurement is 200 ppm. The reference clock can range from 11.05 MHz and 176.8 MHz. Prior to reading back the data rate using the reference clock, the FREF_RANGE[1:0] bits (Bits[D5:D4] in Register 0xF) must be set to the appropriate frequency range with respect to the reference clock being used according to Table 21. Rev. A | Page 21 of 27 ADN2905 Data Sheet A fine data rate readback is then executed as follows: 1. 2. 3. 4. 5. 6. Apply the reference clock. Write a 0 to the REFCLK_PDN bit (Bit D2 in Register 0xA) to enable the reference clock circuit. Write to the FREF_RANGE[1:0] bits(Bits[D5:D4] in Register 0xF) to select the appropriate reference clock frequency circuit. Write a 1 to the RATE_MEAS_EN bit (Bit D1 in Register 0x8) to enable the fine data rate measurement capability of the ADN2905. This bit is level sensitive and does not need to be reset to perform subsequent frequency measurements. Write a low to high to low transition to the RATE_MEAS_ RESET bit (Bit D0 in Register 0x8) to initiate a new data rate measurement. Read back the RATE_MEAS_COMP bit (Bit D0 in Register 0x6). If the bit is 0, the measurement is not complete. If it is 1, the measurement is complete and the data rate can be read back on the RATE_FREQ[23:0] and FREQ_RB2[6:2] bits (see Table 7). The approximate time for a data rate measurement is given in Equation 2. Use the following equation to determine the data rate: f DATARATE = (RATE_FREQ[23:0] × f REFCLK ) 2LTR[5:4] × 27 × 2FULLRATE × 2DIVRATE Consider the example of a 1.25 Gbps (GE) input signal and a reference clock source of 32 MHz at the PIN/NIN and REFCLKP/ REFCLKN ports, respectively. In this case, the FREF_ RANGE[1:0] bits(Bits[D5:D4] in Register 0xF) are 01, and the reference frequency falls into the range of 22.1 MHz to 44.2 MHz. After following Step 1 through Step 6, the readback value of the RATE_FREQ[23:0] bits is 0x13880, which is equal to 8 × 104. The readback value of the FULLRATE bit (Bit D6 in Register 0x5) is 1, and the readback value of the DIVRATE[3:0] bits (Bits[D5:D2] in Register 0x5) is 2. Inserting these values into Equation 1 yields 4 6 1 7 1 Measurement Time = 211 × 2LTR[5:4] f REFCLK (2) ADDITIONAL FEATURES AVAILABLE VIA THE I2C INTERFACE Coarse Data Rate Readback The data rate can be read back over the I2C interface to approximately ±5% without using an external reference clock according to the following formula: Data Rate = 2 f DCO FULLRATE DIVRATE (3) ×2 where fDCO is the frequency of the DCO, derived as shown in Table 22. FULLRATE = FREQ_RB2[6] (Bit D6 in Register 0x5). DIVRATE = FREQ_RB2[5:2] (Bits[D5:D2] in Register 0x5). Four oscillator cores, defined by the VCOSEL[9:8] bits (Bits[D1:D0] in Register 0x5), span the highest octave of data rates according to Table 22. Table 22. DCO Center Frequency vs. VCOSEL[9:8] LSB D7 to D0 FREQ0[7:0] D15 to D8 FREQ1[7:0] Initiating a frequency measurement by writing a low to high to low transition to the RATE_MEAS_RESET bit (Bit D0 in Register 0x8) also resets the RATE_MEAS_COMP bit (Bit D10 in Register 0x6). The approximate time to complete a frequency measurement from the RATE_MEAS_RESET bit being written with a low to high to low transition to when the RATE_MEAS_COMP bit returns high is given by (1) where: fDATARATE is the data rate in Mbps. RATE_FREQ[23:0] is from FREQ2[7:0] (most significant byte), FREQ1[7:0], and FREQ0[7:0] (least significant byte). See Table 7. fREFCLK is the reference clock frequency in MHz. LTR[5:4] = LTR_MODE[5:4]. FULLRATE = FREQ_RB2[6] (Bit D6 in Register 0x5). DIVRATE = FREQ_RB2[5:2] (Bits[D5:D2] in Register 0x5). MSB D23 to D16 FREQ2[7:0] a 1 followed by a 0 to the RATE_MEAS_RESET bit (Bit D0 in Register 0x8). This initiates a new data rate measurement. Follow Step 2 through Step 6 to read back the new data rate. Note that a data rate readback is valid only if the LOL pin is low. If LOL is high, the data rate readback is invalid. Core = (VCOSEL[9:8]) 0 1 2 3 Minimum Frequency (MHz) = MIN_F (Core) 5570 7000 8610 10,265 Maximum Frequency (MHz) = MAX_F (Core) 7105 8685 10,330 11,625 Determine fDCO from the VCOSEL[9:0] bits (Bits[D7:D0] in Register 0x4, and Bits[D1:D0] in Register 0x5), using the following formula: f DCO = MIN _ F (core) + 2 ((8 × 10 ) × (32 × 10 ))/(2 × 2 × 2 × 2 ) = 1.25 Gbps If subsequent frequency measurements are required, keep the RATE_MEAS_EN bit (Bit D1 in Register 0x8) set to 1. It does not need to be reset. The measurement process is reset by writing Rev. A | Page 22 of 27 VCOSEL[9:0] MAX _ F (core) − MIN _ F (core) × 256 (4) Data Sheet ADN2905 2. Worked Example Read back the contents of the FREQ_RB1 and FREQ_RB2 registers. For example, with a CPRI × 16 (9.8304 Gbps) signal presented to the PIN/NIN ports FREQ_RB1 = 0xBA FREQ_RB2 = 0x02 FULLRATE (FREQ_RB2[6]) = 0 DIVRATE (FREQ_RB2[5:2]) = 0 Core (FREQ_RB2[1:0]) = 2 Table 23. PRBS Settings PRBS Pattern PRBS7 PRBS15 PRBS31 PROG_DATA[31:0] Then fDCO = 8610 Mbps + 10,300 Mbps − 8610 Mbps ×186 = 9837.89 Mbps 256 and f data = 9837.89 Mbps = 9.83789 Gbps 20 × 20 Initiate Frequency Acquisition A frequency acquisition can be initiated by writing a 1 followed by a 0 to the INIT_FREQ_ACQ bit (Bit D6 in Register 0x9). This initiates a new frequency acquisition while keeping the ADN2905 in the operating mode that was previously programmed in the CTRLA, CTRLB, and CTRLC registers. PRBS Generator/Receiver The ADN2905 has an integrated PRBS generator and detector for system testing purposes. The devices are configurable as either a PRBS detector or a PRBS generator. The following steps configure the PRBS detector: 1. 2. 3. Set the DATA_RECEIVER_ENABLE bit (Bit D2 in Register 0x3F) to 1 while also setting the DATA_RECEIVER_ MODE[1:0] bits (Bits[D1:D0] in Register 0x3F]) according to the desired PRBS pattern (0 = PRBS7; 1 = PRBS15; 2 = PRBS31). Setting the DATA_RECEIVER_MODE[1:0] bits to 3 leads to a one shot sampling of recovered data into the DATA_LOADED[15:0] bits. Set the DATA_RECEIVER_CLEAR bit (Bit D3 in Register 0x3F) to 1 followed by 0 to clear the PRBS_ERROR and PRBS_ERROR_COUNT bits. The states of the PRBS_ERROR bit (Bit D0 in Register 0x41) and the PRBS_ERROR_COUNT[7:0] bits (Bits[D7:D0] in Register 0x40) can be frozen by setting the DATA_ RECEIVER_ENABLE bits (Bit D2 in Register 0x3F) to 0. The following steps configure the PRBS generator: 1. Strings of consecutive identical digits (CIDs) sensed from the DATA_CID_BIT bit (Bit D5 in Register 0x39) can be introduced in the generator by setting the DATA_CID_EN bit (Bit D4 in Register 0x39) to 1. The length of CIDs is 8 × DATA_CID_LENGTH, which is set via Bits[D7:D0] in Register 0x3A. Set the DATA_GEN_EN bit(Bit D2 in Register 0x39) to 1 to enable the PRBS generator and set the DATA_GEN_ MODE[1:0] bits (Bits[D1:D0] in Register 0x39) for the desired PRBS output pattern (0 = PRBS7; 1 = PRBS15; 2 = PRBS31). An arbitrary 32-bit pattern stored as PROG_ DATA[31:0] is activated by setting the DATA_GEN_ MODE[1:0] bits to 3. DATA_GEN_MODE[1:0] 0x00 0x01 0x10 0x11 PRBS Polynomial 1 + x6 + x 7 1 + x14 + x15 1 + x28 + x31 N/A Double Data Rate Mode The default output clock mode is a double data rate (DDR) clock, where the output clock frequency is ½ the data rate. DDR mode allows direct interfacing to FPGAs that support clocking on both rising and falling edges. Setting the DDR_DISABLE bit (Bit D2 in Register 0x1E) to 1 enables full data rate mode. Full data rate mode is not supported for data rates in the highest octave between 5.6 Gbps and 9.8304 Gbps. CDR Bypass Mode The CDR in the ADN2905 can be bypassed by setting the CDR bypass bit (Bit D5 in Register 0x9) to 1. In this mode, the ADN2905 feeds the input directly through the input amplifiers to the output buffer, bypassing the CDR. The CDR bypass path is intended for use in testing or debugging a system. Use the CDR bypass path at data rates at or below 3.0 Gbps only. Transmission Lines Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, DATOUTP, and DATOUTN (also REFCLKP and REFCLKN, if using a high frequency reference clock, such as 155 MHz). It is also necessary for the PIN and NIN input traces to be matched in length, and the DATOUTP and DATOUTN output traces to be matched in length to avoid skew between the differential traces. The high speed inputs (PIN and NIN) are each internally terminated with 50 Ω to an internal reference voltage (see Figure 26). As with any high speed, mixed-signal circuit, take care to keep all high speed digital traces away from sensitive analog nodes. The high speed outputs (DATOUTP, DATOUTN) are internally terminated with 50 Ω to VCC. Soldering Guidelines for Lead Frame Chip Scale Package The lands on the 24-lead LFCSP are rectangular. The printed circuit board pad for these is 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width. Center the land on the pad to ensure that the solder joint size is maximized. The bottom of the lead frame chip scale package has a central exposed pad. The pad on the printed circuit board must be at least as large as this exposed pad. Connect the exposed pad to VEE using plugged vias to prevent solder from leaking Rev. A | Page 23 of 27 ADN2905 Data Sheet It is highly recommended to include as many vias as possible when connecting the exposed pad to VEE. This minimizes the thermal resistance between the die and VEE, and minimizes the die temperature. It is recommended that the vias be connected to a VEE plane, or planes, rather than a signal trace to improve heat dissipation, as shown in Figure 23. can be configured to use any required input configuration through the I2C bus. Figure 22 shows a block diagram of the input stage circuit. PIN 2 0dB EQ NIN 2.9kΩ Placing an external VEE plane on the backside of the board opposite the ADN2905 provides an additional benefit because this allows easier heat dissipation into the ambient environment. 2.9kΩ 50Ω 50Ω EQ INPUT_SEL[1:0] RX_TERM_FLOAT 12624-022 through the vias during reflow. This ensures a solid connection from the exposed pad to VEE. VCC VREF FLOAT Figure 22. Input Stage Block Diagram INPUT CONFIGURATIONS The ADN2905 input stage can work with the signal source in an ac-coupled or dc-coupled configuration. To best fit in a required applications environment, the ADN2905 supports one of following input modes: equalizer, or bypass. The ADN2905 The input signal path is configurable with the INPUT_SEL[1:0] bits (Bits[D6:D5] in Register 0x16). Table 24 shows the INPUT_ SEL[1:0] bits and the input signal configuration. Table 24. Input Signal Configuration INPUT_SEL[1:0] 00 01 10 11 RX_TERM_FLOAT = 0 VREF VREF VCC Not defined RX_TERM_FLOAT = 1 Not defined Not defined Float Not defined ADN2905 Availability Not defined Yes Yes Not defined 12624-023 Selected Input Limiting Amplifier Equalizer 0 dB EQ Not Defined Figure 23. Connecting Vias to VEE Rev. A | Page 24 of 27 Data Sheet ADN2905 Therefore, Choosing AC Coupling Capacitors τ = 12t AC coupling capacitors at the inputs (PIN, NIN) and outputs (DATOUTP, DATOUTN) of the ADN2905 must be chosen such that the device works properly over the full range of data rates used in the application. When choosing the capacitors, the time constant formed with the two 50 Ω resistors in the signal path must be considered. When a large number of consecutive identical digits (CIDs) are applied, the capacitor voltage can droop due to baseline wander (see Figure 24), causing pattern dependent jitter (PDJ). where: τ is the RC time constant (C is the ac coupling capacitor, R = 100 Ω seen by C). t is the total discharge time. t = nΤ where: n is the number of CIDs. T is the bit period. The user must determine how much droop is tolerable and choose an ac coupling capacitor based on that amount of droop. The amount of PDJ can then be approximated based on the capacitor selection. The actual capacitor value selection may require some trade-offs between droop and PDJ. Calculate the capacitor value by combining the equations for τ and t. C = 12nT/R When the capacitor value is selected, the PDJ can be approximated as For example, assuming that 2% droop is tolerable, the maximum differential droop is 4%. PDJps p-p = 0.5tR(1 − e(−nT/RC)/0.6 Normalizing to V p-p, where: PDJps p-p is the amount of pattern dependent jitter allowed,