Data Sheet
ADP7142
40 V, 200 mA, Low Noise, CMOS LDO Linear Regulator
FEATURES
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TYPICAL APPLICATION CIRCUITS
Low noise: 11 µV rms independent of fixed output voltage
PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz,
VOUT ≤ 5 V, VIN = 7 V
Input voltage range: 2.7 V to 40 V
Maximum output current: 200 mA
Initial accuracy: ±0.8%
Accuracy over line, load, and temperature
► −1.2% to +1.5%, TJ = −40°C to +85°C
► ±1.8%, TJ = −40°C to +125°C
Low dropout voltage: 200 mV (typical) at a 200 mA load, VOUT =
5V
User programmable soft start (LFCSP and SOIC only)
Low quiescent current, IGND = 50 μA (typical) with no load
Low shutdown current: 1.8 μA at VIN = 6 V, 3.0 μA at VIN = 40 V
Stable with a small 2.2 µF ceramic output capacitor
Fixed output voltage options: 1.8 V, 2.5 V, 3.3 V, 3.8 V, and 5.0 V
► 15 standard voltages between 1.2 V and 5.0 V are available
Adjustable output from 1.2 V to VIN – VDO, output can be
adjusted above initial set point
Precision enable
2 mm × 2 mm, 6-lead LFCSP, 8-Lead SOIC, 5-Lead TSOT
AEC-Q100 qualified for automotive applications
APPLICATIONS
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Regulation to noise sensitive applications
ADC, DAC circuits, precision amplifiers, power for VCO VTUNE
control
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
Automotive
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Figure 1. ADP7142 with Fixed Output Voltage, 5 V
Figure 2. ADP7142 with 5 V Output Adjusted to 6 V
GENERAL DESCRIPTION
The ADP7142 is a CMOS, low dropout (LDO) linear regulator that
operates from 2.7 V to 40 V and provides up to 200 mA of output
current. This high input voltage LDO is ideal for the regulation
of high performance analog and mixed signal circuits operating
from 39 V down to 1.2 V rails. Using an advanced proprietary
architecture, the device provides high power supply rejection, low
noise, and achieves excellent line and load transient response with
a small 2.2 µF ceramic output capacitor. The ADP7142 regulator
output noise is 11 μV rms independent of the output voltage for the
fixed options of 5 V or less.
The ADP7142 is available in 15 fixed output voltage options. The
following voltages are available from stock: 1.2 V (adjustable), 1.8
V, 2.5 V, 3.3 V, 3.8 V, and 5.0 V. Additional voltages available by
special order are 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.75 V, 2.8 V, 2.85 V,
3.0 V, 4.2 V, and 4.6 V.
Each fixed output voltage can be adjusted above the initial set
point with an external feedback divider. This allows the ADP7142 to
provide an output voltage from 1.2 V to VIN − VDO with high PSRR
and low noise.
User programmable soft start with an external capacitor is available
in the LFCSP and SOIC packages.
The ADP7142 is available in a 6-lead, 2 mm × 2 mm LFCSP making it not only a very compact solution, but it also provides excellent
thermal performance for applications requiring up to 200 mA of
output current in a small, low profile footprint. The ADP7142 is also
available in a 5-lead TSOT and an 8-lead SOIC.
Rev. I
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
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change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Data Sheet
ADP7142
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Typical Application Circuits....................................1
General Description...............................................1
Specifications........................................................ 3
Input and Output Capacitance,
Recommended Specifications..........................4
Absolute Maximum Ratings...................................5
Thermal Data......................................................5
Thermal Resistance........................................... 5
ESD Caution.......................................................5
Pin Configurations and Function Descriptions.......6
Typical Performance Characteristics..................... 7
Theory of Operation.............................................13
Applications Information...................................... 14
Design Tools.....................................................14
Capacitor Selection.......................................... 14
Programmable Precision Enable......................14
Soft Start.......................................................... 15
Noise Reduction of the ADP7142 in
Adjustable Mode.............................................15
Effect of Noise Reduction on Start-Up Time.....16
Current-Limit and Thermal Overload
Protection....................................................... 16
Thermal Considerations................................... 17
Printed Circuit Board Layout Considerations.......20
Outline Dimensions............................................. 22
Ordering Guide.................................................23
Output Voltage Options ................................... 24
Evaluation Boards............................................ 24
Automotive Products........................................ 24
REVISION HISTORY
3/2022—Rev. H to Rev. I
Changes to Features Section.......................................................................................................................... 1
Change to Applications Section....................................................................................................................... 1
Change to General Description Section...........................................................................................................1
Change to Specifications Section.................................................................................................................... 3
Changes to Table 3.......................................................................................................................................... 5
Changes to Figure 6 Caption, Figure 9 Caption, Figure 10 Caption, and Figure 11 Caption.......................... 7
Changes to Figure 12 Caption, Figure 13 Caption, Figure 15 Caption, and Figure 16 Caption...................... 8
Changes to Figure 19 Caption to Figure 22 Caption....................................................................................... 9
Changes to Figure 24 Caption and Figure 25 Caption.................................................................................. 10
Changed ADISIMPower Design Tool Section to Design Tools Section......................................................... 14
Changes to Design Tools Section.................................................................................................................. 14
Changes to Input and Output Capacitor Properties Section ......................................................................... 14
Changes to Soft Start Section........................................................................................................................15
Changes to Figure 48.................................................................................................................................... 15
Change to Effect of Noise Reduction on Start-Up Time Section....................................................................16
Changes to Thermal Considerations Section................................................................................................ 17
Changes to Ordering Guide........................................................................................................................... 23
Added Voltage Output Options Section......................................................................................................... 24
Added Automotive Products Section............................................................................................................. 24
analog.com
Rev. I | 2 of 24
Data Sheet
ADP7142
SPECIFICATIONS
VIN = VOUT +1 V or 2.7 V, whichever is greater, VOUT = 5 V, VEN = VIN, IOUT = 10 mA, CIN = COUT = 2.2 µF, CSS = 0 pF, TA = 25°C for typical
specifications, TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 1.
Parameter
Symbol
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
VIN
IGND
SHUTDOWN CURRENT
IGND-SD
OUTPUT VOLTAGE ACCURACY
Output Voltage Accuracy
VOUT
LINE REGULATION
LOAD REGULATION1
SENSE INPUT BIAS CURRENT
DROPOUT VOLTAGE2
∆VOUT/∆VIN
∆VOUT/∆IOUT
SENSEI-BIAS
VDROPOUT
START-UP TIME3
SOFT START SOURCE CURRENT
CURRENT-LIMIT THRESHOLD4
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
UNDERVOLTAGE THRESHOLDS
Input Voltage Rising
Input Voltage Falling
Hysteresis
PRECISION EN INPUT
Logic High
Logic Low
Logic Hysteresis
Leakage Current
Delay Time
OUTPUT NOISE
POWER SUPPLY REJECTION RATIO
tSTART-UP
SSI-SOURCE
ILIMIT
TSSD
TSSD-HYS
Test Conditions/Comments
Min
Typ
Max
Unit
40
140
190
320
10
V
µA
µA
µA
µA
µA
–0.8
–1.2
+0.8
+1.5
%
%
–1.8
–0.01
+1.8
+0.01
0.004
1000
60
420
%
%/V
%/mA
nA
mV
mV
µs
µA
mA
2.7
IOUT = 0 µA
IOUT = 10 mA
IOUT = 200 mA
EN = GND
EN = GND, VIN = 40 V
IOUT = 10 mA, TJ = 25°C
100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 40 V, TJ = −40°C
to +85°C
100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 40 V
VIN = (VOUT + 1 V) to 40 V
IOUT = 100 μA to 200 mA
100 μA < IOUT < 200 mA VIN = (VOUT + 1 V) to 40 V
IOUT = 10 mA
IOUT = 200 mA
VOUT = 5 V
SS = GND
50
80
180
1.8
3.0
250
TJ rising
UVLORISE
UVLOFALL
UVLOHYS
0.002
10
30
200
380
1.15
360
460
150
15
°C
°C
2.69
V
V
mV
1.30
1.18
V
V
mV
µA
μs
µV rms
dB
dB
dB
2.2
230
2.7 V ≤ VIN ≤ 40 V
ENHIGH
ENLOW
ENHYS
IEN-LKG
tEN-DLY
OUTNOISE
PSRR
1.15
1.06
EN = VIN or GND
From EN rising from 0 V to VIN to 0.1 × VOUT
10 Hz to 100 kHz, all output voltage options
1 MHz, VIN = 7 V, VOUT = 5 V
100 kHz, VIN = 7 V, VOUT = 5 V
10 kHz, VIN = 7 V, VOUT = 5 V
1.22
1.12
100
0.04
80
11
50
68
88
1
1
Based on an endpoint calculation using 100 μA and 200 mA loads. See Figure 7 for typical load regulation performance for loads less than 1 mA.
2
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output voltages
above 2.7 V.
3
Start-up time is defined as the time between the rising edge of EN to OUT being at 90% of its nominal value.
4
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V output
voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V or 4.5 V.
analog.com
Rev. I | 3 of 24
Data Sheet
ADP7142
SPECIFICATIONS
INPUT AND OUTPUT CAPACITANCE, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
INPUT AND OUTPUT CAPACITANCE
Minimum Capacitance1
Capacitor Effective Series Resistance (ESR)
CMIN
RESR
TA = −40°C to +125°C
TA = −40°C to +125°C
1.5
0.001
1
Typ
Max
Unit
0.3
µF
Ω
The minimum input and output capacitance must be greater than 1.5 μF over the full range of operating conditions. The full range of operating conditions in the application
must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, while Y5V and
Z5U capacitors are not recommended for use with any LDO.
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Rev. I | 4 of 24
Data Sheet
ADP7142
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
VIN to GND
VOUT to GND
EN to GND
SENSE/ADJ to GND
SS to GND
–0.3 V to +44 V
–0.3 V to VIN
–0.3 V to +44 V
–0.3 V to +6 V
–0.3 V to VIN or +6 V
(whichever is less)
–65°C to +150°C
150°C
–40°C to +125°C
Storage Temperature Range
Junction Temperature (TJ)
Operating Ambient Temperature (TA)
Range
Soldering Conditions
ESD
6-Lead LFCSP, 8-Lead SOIC
Human Body Model (HBM)
Field Induced Charged Device Model
(FICDM)
5-Lead TSOT
HBM
FICDM
5-Lead TSOT (W Grade)
HBM1
HBM2
FICDM
JEDEC J-STD-020
±1000 V
±1000 V
±1000 V
±1250 V
±1000 V
±2000 V
±1250 V
1
All pins passing.
2
All pins passing with elevated output noise. No physical damage to circuitry.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in combination. The ADP7142 can be damaged when the junction temperature
limits are exceeded. Monitoring ambient temperature does not
guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the
maximum ambient temperature may have to be derated.
In applications with moderate power dissipation and low printed
circuit board (PCB) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction
temperature is within specification limits. The junction temperature
of the device is dependent on the ambient temperature, the power
dissipation (PD) of the device, and the junction-to-ambient thermal
resistance of the package (θJA).
T J = TA + PD × θ JA
(1)
θJA of the package is based on modeling and calculation using
a 4-layer board. The θJA is highly dependent on the application
and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required.
The value of θJA may vary, depending on PCB material, layout, and
environmental conditions. The specified values of θJA are based on
a 4-layer, 4 inches × 3 inches circuit board. See JESD51-7 and
JESD51-9 for detailed information on the board construction.
ΨJB is the junction-to-board thermal characterization parameter with
units of °C/W. The ΨJB of the package is based on modeling
and calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same as
thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance (θJB). Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package, factors that make ΨJB more useful in real-world
applications. Maximum TJ is calculated from the board temperature
(TB) and PD using the formula
T J = TB + PD × Ψ JB
(2)
See JESD51-8 and JESD51-12 for more detailed information about
ΨJB.
THERMAL RESISTANCE
θJA, θJC, and ΨJB are specified for the worst-case conditions, that
is, a device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
θJC
ΨJB
Unit
6-Lead LFCSP
8-Lead SOIC
5-Lead TSOT
72.1
52.7
170
42.3
41.5
N/A1
47.1
32.7
43
°C/W
°C/W
°C/W
1
N/A means not applicable.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Maximum TJ is calculated from the TA and PD using the formula
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Rev. I | 5 of 24
Data Sheet
ADP7142
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 5. 8-Lead SOIC Pin Configuration
Figure 3. 6-Lead LFCSP Pin Configuration
Figure 4. 5-Lead TSOT Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
6-Lead LFCSP
8-Lead SOIC
5-Lead TSOT
Mnemonic
Description
1
2
1, 2
3
5
4
VOUT
SENSE/ADJ
3
4
4
5
2
3
GND
EN
5
6
Not applicable
SS
6
7, 8
1
VIN
EP
Regulated Output Voltage. Bypass VOUT to GND with a 2.2 µF or greater capacitor.
Sense Input (SENSE). Connect to load. An external resistor divider may also be used to set the output
voltage higher than the fixed output voltage (ADJ).
Ground.
The Enable Pin Controls the Operation of the LDO. Drive EN high to turn on the regulator. Drive EN
low to turn off the regulator. For automatic startup, connect EN to VIN.
Soft Start. An external capacitor connected to this pin determines the soft-start time. Leave this pin
open for a typical 380 μs start-up time. Do not ground this pin.
Regulator Input Supply. Bypass VIN to GND with a 2.2 µF or greater capacitor.
Exposed Pad. The exposed pad on the bottom of the package enhances thermal performance and is
electrically connected to GND inside the package. It is recommended that the exposed pad connect to
the ground plane on the board.
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Rev. I | 6 of 24
Data Sheet
ADP7142
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VOUT + 1 V or 2.7 V, whichever is greater, VOUT = 5 V, IOUT = 10 mA, CIN = COUT = 2.2 µF, TA = 25°C, unless otherwise noted.
Figure 6. Output Voltage (VOUT) vs. Junction Temperature (TJ)
Figure 9. Ground Current (IGND) vs. Junction Temperature (TJ)
Figure 7. Output Voltage (VOUT) vs. Load Current (ILOAD)
Figure 10. Ground Current (IGND) vs. Load Current (ILOAD)
Figure 8. Output Voltage (VOUT) vs. Input Voltage (VIN)
Figure 11. Ground Current (IGND) vs. Input Voltage (VIN)
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Rev. I | 7 of 24
Data Sheet
ADP7142
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 12. Shutdown Current (IGND-SD) vs. Temperature at Various Input
Voltages (VIN)
Figure 15. Ground Current (IGND) vs. Input Voltage (VIN) in Dropout,
VOUT = 5 V
Figure 13. Dropout Voltage (VDROPOUT) vs. Load Current (ILOAD), VOUT = 5 V
Figure 16. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = 3.3 V
Figure 14. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout, VOUT = 5 V
Figure 17. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 3.3 V
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Rev. I | 8 of 24
Data Sheet
ADP7142
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 18. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = 3.3 V
Figure 21. Ground Current (IGND) vs. Input Voltage (VIN), VOUT = 3.3 V
Figure 19. Ground Current (IGND) vs. Junction Temperature (TJ), VOUT = 3.3 V
Figure 22. Dropout Voltage (VDROPOUT) vs. Load Current (ILOAD), VOUT = 3.3 V
Figure 20. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 3.3 V
Figure 23. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout,
VOUT = 3.3 V
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Rev. I | 9 of 24
Data Sheet
ADP7142
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 24. Ground Current (IGND) vs. Input Voltage (VIN) in Dropout,
VOUT = 3.3 V
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
VOUT = 1.8 V, for Different Frequencies
Figure 25. Soft Start (SS) Current vs. Temperature (TJ),
Multiple Input Voltages (VIN), VOUT = 5 V
Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 3.3 V,
for Various Headroom Voltages
Figure 26. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 1.8 V,
for Various Headroom Voltages
Figure 29. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
VOUT = 3.3 V, for Different Frequencies
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Rev. I | 10 of 24
Data Sheet
ADP7142
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 30. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 5 V,
for Various Headroom Voltages
Figure 31. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
VOUT = 5 V, for Different Frequencies
Figure 32. RMS Output Noise vs. Load Current (ILOAD)
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Figure 33. Output Noise Spectral Density vs. Frequency, ILOAD = 10 mA
Figure 34. Output Noise Spectral Density vs. Frequency, for Different Loads
Figure 35. Output Noise Spectral Density vs. Frequency, for Different Output
Voltages (VOUT)
Rev. I | 11 of 24
Data Sheet
ADP7142
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 36. Load Transient Response, ILOAD = 1 mA to 200 mA, VOUT = 5 V,
VIN = 7 V, CH1 Load Current (ILOAD), CH2 VOUT
Figure 39. Line Transient Response, ILOAD = 200 mA,VOUT = 3.3 V, CH1 VIN,
CH2 VOUT
Figure 37. Line Transient Response, ILOAD = 200 mA, VOUT = 5 V, CH1 VIN,
CH2 VOUT
Figure 40. Load Transient Response, ILOAD = 1 mA to 200 mA, VOUT = 1.8 V,
VIN = 3 V, CH1 Load Current (ILOAD), CH2 VOUT
Figure 38. Load Transient Response, ILOAD = 1 mA to 200 mA, VOUT = 3.3 V,
VIN = 5 V, CH1 Load Current (ILOAD), CH2 VOUT
Figure 41. Line Transient Response, ILOAD = 200 mA, VOUT = 1.8 V, CH1 VIN,
CH2 VOUT
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Rev. I | 12 of 24
Data Sheet
ADP7142
THEORY OF OPERATION
The ADP7142 is a low quiescent current, LDO linear regulator
that operates from 2.7 V to 40 V and provides up to 200 mA of
output current. Drawing a low 180 μA of quiescent current (typical)
at full load makes the ADP7142 ideal for portable equipment.
Typical shutdown current consumption is less than 3 μA at room
temperature.
Optimized for use with small 2.2 µF ceramic capacitors, the
ADP7142 provides excellent transient performance.
output voltage to be set to a higher voltage with an external voltage
divider. For example, a fixed 5 V output can be set to a 6 V output
according to the following equation:
VOUT = 5 V 1 + R1/R2
(3)
where R1 and R2 are the resistors in the output voltage divider
shown in Figure 43.
To set the output voltage of the adjustable ADP7142, replace 5 V in
Equation 3 with 1.2 V.
Figure 42. Internal Block Diagram
Internally, the ADP7142 consists of a reference, an error amplifier,
and a PMOS pass transistor. Output current is delivered via the
PMOS pass device, which is controlled by the error amplifier. The
error amplifier compares the reference voltage with the feedback
voltage from the output and amplifies the difference. If the feedback
voltage is lower than the reference voltage, the gate of the PMOS
device is pulled lower, allowing more current to pass and increasing
the output voltage. If the feedback voltage is higher than the
reference voltage, the gate of the PMOS device is pulled higher,
allowing less current to pass and decreasing the output voltage.
The ADP7142 is available in 15 fixed output voltage options, ranging from 1.2 V to 5.0 V. The ADP7142 architecture allows any fixed
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Figure 43. Typical Adjustable Output Voltage Application Schematic
It is recommended that the R2 value be less than 200 kΩ to minimize errors in the output voltage caused by the SENSE/ADJ pin
input current. For example, when R1 and R2 each equal 200 kΩ
and the default output voltage is 1.2 V, the adjusted output voltage
is 2.4 V. The output voltage error introduced by the SENSE/ADJ pin
input current is 1 mV or 0.04%, assuming a typical SENSE/ ADJ pin
input current of 10 nA at 25°C.
The ADP7142 uses the EN pin to enable and disable the VOUT pin
under normal operating conditions. When EN is high, VOUT turns
on, and when EN is low, VOUT turns off. For automatic startup, EN
can be tied to VIN.
Rev. I | 13 of 24
Data Sheet
ADP7142
APPLICATIONS INFORMATION
DESIGN TOOLS
®
The ADP7142 is supported by the ADIsimPower™, LTpowerCAD ,
®
and LTspice design tools to produce complete power designs
and simulations. For more information on design tools, visit the
ADP7142 product page, www.analog.com/adp7142.
CAPACITOR SELECTION
Figure 45 depicts the capacitance vs. voltage bias characteristic of
an 0805, 2.2 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the X5R
dielectric is ~±15% over the −40°C to +85°C temperature range and
is not a function of package or voltage rating.
Output Capacitor
The ADP7142 is designed for operation with small, space-saving
ceramic capacitors, but functions with general-purpose capacitors
as long as care is taken with regard to the effective series resistance (ESR) value. The ESR of the output capacitor affects the
stability of the LDO control loop. A minimum of 2.2 µF capacitance
with an ESR of 0.3 Ω or less is recommended to ensure the stability
of the ADP7142. Transient response to changes in load current
is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP7142
to large changes in load current. Figure 44 shows the transient
responses for an output capacitance value of 2.2 µF.
Figure 45. Capacitance vs. Voltage Characteristic
Use Equation 4 to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance,
and voltage.
CEFF = CBIAS 1 − TEMPCO × 1 − TOL
(4)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
Figure 44. Output Transient Response, VOUT = 5 V, COUT = 2.2 µF, CH1 Load
Current, CH2 VOUT
Input Bypass Capacitor
Connecting a 2.2 µF capacitor from VIN to GND reduces the circuit
sensitivity to the PCB layout, especially when long input traces
or high source impedance is encountered. If greater than 2.2 µF
of output capacitance is required, increase the input capacitor to
match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP7142, as long as they meet the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are manufactured
with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric
adequate to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V to 100 V are recommended. Y5V and
Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics.
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In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
CBIAS is 2.09 μF at 5 V, as shown in Figure 45.
These values in Equation 4 yield
CEFF = 2 . 09 μF× 1 − 0 . 15 × 1 − 0 . 1 =
1 . 59 μF
(5)
Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and
tolerance at the chosen output voltage.
To guarantee the performance of the ADP7142, it is imperative that
the effects of dc bias, temperature, and tolerances on the behavior
of the capacitors be evaluated for each application.
PROGRAMMABLE PRECISION ENABLE
The ADP7142 uses the EN pin to enable and disable the VOUT pin
under normal operating conditions. As shown in Figure 46, when a
rising voltage on EN crosses the upper threshold, nominally 1.2 V,
VOUT turns on. When a falling voltage on EN crosses the lower
threshold, nominally 1.1 V, VOUT turns off. The hysteresis of the
EN threshold is approximately 100 mV.
Rev. I | 14 of 24
Data Sheet
ADP7142
APPLICATIONS INFORMATION
Figure 48. Typical Start-Up Behavior
Figure 46. Typical VOUT Response to EN Pin Operation
The upper and lower thresholds are user programmable and can be
set higher than the nominal 1.2 V threshold by using two resistors.
The resistance values, REN1 and REN2, can be determined from
REN2 = nominally 10 kΩ to 100 kΩ
REN1 = REN2 × VIN − 1 . 2 V /1 . 2 V
(6)
(7)
where VIN is the desired turn-on voltage.
The hysteresis voltage increases by the factor (REN1 + REN2)/ REN2.
For the example shown in Figure 47, the enable threshold is 3.6 V
with a hysteresis of 300 mV.
An external capacitor connected to the SS pin determines the soft
start time. The SS pin can be left open for a typical 380 μs start-up
time. Do not ground this pin. When an external soft start capacitor
(CSS) is used, the soft start time is determined by the following
equation:
SSTIME sec = tSTARTUP
0 pF
+ 0 . 6 × CSS /ISS
(8)
where:
tSTARTUP (at 0 pF) is the start-up time at CSS = 0 pF (typically 380 µs).
CSS is the soft start capacitor (F).
ISS is the soft start current (typically 1.15 µA).
Figure 47. Typical EN Pin Voltage Divider
Figure 46 shows the typical hysteresis of the EN pin. This prevents
on/off oscillations that can occur due to noise on the EN pin as it
passes through the threshold points.
SOFT START
The ADP7142 uses an internal soft start (when the SS pin is left
open) to limit the inrush current when the output is enabled. The
start-up time for the 3.3 V option is approximately 380 μs from the
time the EN active threshold is crossed to when the output reaches
90% of its final value. As shown in Figure 48, the start-up time is
independent of the output voltage setting.
Figure 49. Typical Soft Start Behavior, Different CSS
NOISE REDUCTION OF THE ADP7142 IN
ADJUSTABLE MODE
The ultralow output noise of the ADP7142 is achieved by keeping
the LDO error amplifier in unity gain and setting the reference
voltage equal to the output voltage. This architecture does not work
for an adjustable output voltage LDO in the conventional sense.
However, the ADP7142 architecture allows any fixed output voltage
to be set to a higher voltage with an external voltage divider. For
example, a fixed 5 V output can be set to a 10 V output according
to Equation 3 (see Figure 50):
VOUT = 5 V 1 + R1/R2
The disadvantage in using the ADP7142 in this manner is that the
output voltage noise is proportional to the output voltage. Therefore,
analog.com
Rev. I | 15 of 24
Data Sheet
ADP7142
APPLICATIONS INFORMATION
it is best to choose a fixed output voltage that is close to the target
voltage to minimize the increase in output noise.
The adjustable LDO circuit can be modified to reduce the output
voltage noise to levels close to that of the fixed output ADP7142.
The circuit shown in Figure 50 adds two additional components to
the output voltage setting resistor divider. CNR and RNR are added
in parallel with R1 to reduce the ac gain of the error amplifier. RNR
is chosen to be small with respect to R2. If RNR is 1% to 10%
of the value of R2, the minimum ac gain of the error amplifier is
approximately 0.1 dB to 0.8 dB. The actual gain is determined by
the parallel combination of RNR and R1. This gain ensures that the
error amplifier always operates at slightly greater than unity gain.
CNR is chosen by setting the reactance of CNR equal to R1 − RNR
at a frequency between 1 Hz and 50 Hz. This setting places the
frequency where the ac gain of the error amplifier is 3 dB down
from its dc gain.
is limited by its open loop gain characteristic. Therefore, the noise
contribution from 20 kHz to 100 kHz is less than what it would be
if the error amplifier had infinite bandwidth. This is also the reason
why the noise is less than what might be expected simply based on
the dc gain, that is, 70 µV rms vs. 110 µV rms.
Figure 51. 6 V and 12 V Output Voltage with and Without Noise Reduction
Network
EFFECT OF NOISE REDUCTION ON START-UP
TIME
The start-up time of the ADP7142 is affected by the noise reduction
network and must be considered in applications where power
supply sequencing is critical.
Figure 50. Noise Reduction Modification
The noise of the adjustable LDO is found by using the following
formula, assuming the noise of a fixed output LDO is approximately
11 μV.
Noise = 11 μV × RPAR + R2 /R2
(9)
where RPAR is a parallel combination of R1 and RNR.
Based on the component values shown in Figure 50, the ADP7142
has the following characteristics:
►
►
►
►
►
►
►
DC gain of 10 (20 dB)
3 dB roll-off frequency of 1.75 Hz
High frequency ac gain of 1.099 (0.82 dB)
Theoretical noise reduction factor of 9.1 (19.2 dB)
Measured rms noise of the adjustable LDO without noise reduction is 70 µV rms
Measured rms noise of the adjustable LDO with noise reduction
is 12 µV rms
Measured noise reduction of approximately 15.3 dB
Note that the measured noise reduction is less than the theoretical
noise reduction. Figure 51 shows the noise spectral density of an
adjustable ADP7142 set to 6 V and 12 V with and without the
noise reduction network. The output noise with the noise reduction
network is approximately the same for both voltages, especially
beyond 100 Hz. The noise of the 6 V and 12 V outputs without the
noise reduction network differs by a factor of 2 up to approximately
20 kHz. Above 40 kHz, the closed loop gain of the error amplifier
analog.com
The noise reduction circuit adds a pole in the feedback loop,
slowing down the start-up time. The start-up time for an adjustable
model with a noise reduction network can be approximated using
the following equation:
SSNRTIME sec = 5 . 5 × CNR × RNR + R1
(10)
For a CNR, RNR, and R1 combination of 1 µF, 1 kΩ, and 91 kΩ
as shown in Figure 50, the start-up time is approximately 0.5 sec.
When SSNRTIME is greater than SSTIME, SSNRTIME dictates the
length of the start-up time instead of the soft start capacitor.
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP7142 is protected against damage due to excessive power
dissipation by current and thermal overload protection circuits. The
ADP7142 is designed to current limit when the output load reaches
360 mA (typical). When the output load exceeds 360 mA, the output
voltage is reduced to maintain a constant current limit.
Thermal overload protection is included, which limits the junction
temperature to a maximum of 150°C (typical). Under extreme
conditions (that is, high ambient temperature and/or high power
dissipation) when the junction temperature starts to rise above
150°C, the output is turned off, reducing the output current to zero.
When the junction temperature drops below 135°C, the output is
turned on again, and output current is restored to its operating
value.
Rev. I | 16 of 24
Data Sheet
ADP7142
APPLICATIONS INFORMATION
Consider the case where a hard short from VOUT to ground occurs.
At first, the ADP7142 current limits, so that only 360 mA is conducted into the short. If self heating of the junction is great enough
to cause its temperature to rise above 150°C, thermal shutdown
activates, turning off the output and reducing the output current to
zero. As the junction temperature cools and drops below 135°C,
the output turns on and conducts 360 mA into the short, again
causing the junction temperature to rise above 150°C. This thermal
oscillation between 135°C and 150°C causes a current oscillation
between 360 mA and 0 mA that continues as long as the short
remains at the output.
Table 6. Typical θJA Values
θJA (°C/W)
Copper Size (mm1)
LFCSP
SOIC
TSOT
500
1000
6400
83.9
71.7
57.4
89.3
77.5
63.2
131
N/A1
N/A1
1
N/A means not applicable.
2
Device soldered to minimum size pin traces.
Table 7. Typical ΨJB Values
Current and thermal limit protections protect the device against
accidental overload conditions. For reliable operation, device power
dissipation must be externally limited so that the junction temperature does not exceed 125°C.
Model
ΨJB (°C/W)
6-Lead LFCSP
8-Lead SOIC
5-Lead TSOT
24
38.8
43
THERMAL CONSIDERATIONS
To calculate the junction temperature of the ADP7142, use Equation 1:
In applications with a low input-to-output voltage differential, the
ADP7142 does not dissipate much heat. However, in applications
with high ambient temperature and/or high input voltage, the heat
dissipated in the package may become large enough to cause the
junction temperature of the die to exceed the maximum junction
temperature of 125°C.
When the junction temperature exceeds 150°C, the converter enters thermal shutdown. It recovers only after the junction temperature has decreased below 135°C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is very
important to guarantee reliable performance over all conditions.
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to the power dissipation, as shown in Equation 2.
To guarantee reliable operation, the junction temperature of the
ADP7142 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction and ambient air (θJA). The θJA number is dependent on
the package assembly compounds that are used and the amount of
copper used to solder the package GND pins to the PCB.
T J = TA + PD × θ JA
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD =
VIN − VOUT × ILOAD + VIN × IGND
(11)
where:
VIN and VOUT are input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation due to ground current is quite small and can be
ignored. Therefore, the junction temperature equation simplifies to
the following:
T J = TA +
VIN − VOUT × ILOAD × θ JA
(12)
As shown in Equation 12, for a given ambient temperature, inputto-output voltage differential, and continuous load current, there
exists a minimum copper size requirement for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure
52 to Figure 60 show junction temperature calculations for different
ambient temperatures, power dissipation, and areas of PCB copper.
Table 6 shows typical θJA values of the 8-lead SOIC, 6-lead LFCSP,
and 5-Lead TSOT packages for various PCB copper sizes. Table
7 shows the typical ΨJB values of the 8-lead SOIC, 6-lead LFCSP,
and 5-lead TSOT.
Table 6. Typical θJA Values
θJA (°C/W)
Copper Size (mm1)
252
50
100
analog.com
LFCSP
SOIC
TSOT
182.8
N/A1
142.6
N/A1
N/A1
152
146
181.4
145.4
Figure 52. LFCSP, TA = 25°C
Rev. I | 17 of 24
Data Sheet
ADP7142
APPLICATIONS INFORMATION
Figure 53. LFCSP, TA = 50°C
Figure 57. SOIC, TA = 85°C
Figure 54. LFCSP, TA = 85°C
Figure 58. TSOT, TA = 25°C
Figure 55. SOIC, TA = 25°C
Figure 59. TSOT, TA = 50°C
Figure 56. SOIC, TA = 50°C
Figure 60. TSOT, TA = 85°C
In the case where the board temperature is known, use the thermal
characterization parameter, ΨJB, to estimate the junction temperaanalog.com
Rev. I | 18 of 24
Data Sheet
ADP7142
APPLICATIONS INFORMATION
ture rise (see Figure 61, Figure 62, and Figure 63). Calculate the
maximum junction temperature by using Equation 2.
T J = TB + PD × Ψ JB
The typical value of ΨJB is 24°C/W for the 8-lead LFCSP package,
38.8°C/W for the 8-lead SOIC package, and 43°C/W for the 5-lead
TSOT package.
Figure 61. LFCSP Junction Temperature Rise, Different Board Temperatures
Figure 62. SOIC Junction Temperature Rise, Different Board Temperatures
Figure 63. TSOT Junction Temperature Rise, Different Board Temperatures
analog.com
Rev. I | 19 of 24
Data Sheet
ADP7142
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP7142. However, as listed in Table 6, a point of diminishing returns is eventually
reached, beyond which an increase in the copper size does not
yield significant heat dissipation benefits.
Place the input capacitor as close as possible to the VIN pin and
GND pin. Place the output capacitor as close as possible to the
VOUT and GND pins. Use of 0805 or 1206 size capacitors and
resistors achieves the smallest possible footprint solution on boards
where area is limited.
Figure 64. Example LFCSP PCB Layout
Figure 65. Example SOIC PCB Layout
Figure 66. Example TSOT PCB Layout
analog.com
Rev. I | 20 of 24
Data Sheet
ADP7142
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
Table 8. Recommended LDOs for Very Low Noise Operation
Device
Number
VIN Range
(V)
VOUT
Fixed (V)
VOUT
Adjust (V)
IOUT
(mA)
IQ at
IOUT
(µA)
IGND-SD
Max
(µA)
Soft
Start
PGOOD
Noise
(Fixed)
10 Hz to
100 kHz (µV
rms)
ADP7102
3.3 to 20
1.5 to 9
1.22 to 19
300
750
75
No
Yes
15
60
40 dB
ADP7104
3.3 to 20
1.5 to 9
1.22 to 19
500
900
75
No
Yes
15
60
40 dB
ADP7105
3.3 to 20
1.8, 3.3, 5
1.22 to 19
500
900
75
Yes
Yes
15
60
40 dB
ADP7112
2.7 to 20
1.2 to 5
1.2 to 19
200
180
10
Yes
No
11
68
50 dB
ADP7118
2.7 to 20
1.2 to 5
1.2 to 19
200
180
10
Yes
No
11
68
50 dB
ADP7142
2.7 to 40
1.2 to 5
1.2 to 39
200
180
10
Yes
No
11
68
50 dB
ADP7182
−2.7 to −28 −1.8 to −5
−1.22 to
−27
−200
−650
−8
No
No
18
45
45 dB
PSRR 100 PSRR 1
kHz (dB) MHz
Package
3 mm × 3 mm 8lead LFCSP, 8lead SOIC
3 mm × 3 mm 8lead LFCSP, 8lead SOIC
3 mm × 3 mm 8lead LFCSP, 8lead SOIC
1 mm × 1.2 mm 6ball WLCSP
2 mm × 2 mm 6lead LFCSP, 8lead SOIC, 5-lead
TSOT
2 mm × 2 mm 6lead LFCSP, 8lead SOIC, 5-lead
TSOT
2 mm × 2 mm 6lead LFCSP, 3 mm
× 3 mm 8-lead
LFCSP, 5-lead
TSOT
Table 9. Related Devices
Model
Input Voltage (V)
Output Current (mA)
Package
ADP7118CP
ADP7118RD
ADP7118UJ
ADP7112CB
2.7 to 20
2.7 to 20
2.7 to 20
2.7 to 20
200
200
200
200
6-lead LFCSP
8-lead SOIC
5-lead TSOT
6-ball WLCSP
analog.com
Rev. I | 21 of 24
Data Sheet
ADP7142
OUTLINE DIMENSIONS
Figure 67. 6-Lead Lead Frame Chip Scale Package [LFCSP]
2.00 mm × 2.00 mm Body and 0.55 mm Package Height
(CP-6-3)
Dimensions shown in millimeters
Figure 68. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
Figure 69. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions shown in millimeters
analog.com
Rev. I | 22 of 24
Data Sheet
ADP7142
OUTLINE DIMENSIONS
Updated: October 18, 2021
ORDERING GUIDE
Model1, 2
Temperature Range
Package Description
Packing Quantity
Package
Option
ADP7142ACPZN1.8-R7
ADP7142ACPZN2.5-R7
ADP7142ACPZN3.3-R7
ADP7142ACPZN3.8-R7
ADP7142ACPZN5.0-R7
ADP7142ACPZN-R7
ADP7142ARDZ
ADP7142ARDZ-1.8
ADP7142ARDZ-1.8-R7
ADP7142ARDZ-2.5
ADP7142ARDZ-2.5-R7
ADP7142ARDZ-3.3
ADP7142ARDZ-3.3-R7
ADP7142ARDZ-5.0
ADP7142ARDZ-5.0-R7
ADP7142ARDZ-R7
ADP7142AUJZ-1.8-R7
ADP7142AUJZ-2.5-R7
ADP7142AUJZ-3.3-R7
ADP7142AUJZ-5.0-R7
ADP7142AUJZ-R2
ADP7142AUJZ-R7
ADP7142WAUJZ-1.8-R7
ADP7142WAUJZ-2.5-R7
ADP7142WAUJZ-3.3-R7
ADP7142WAUJZ-5.0-R7
ADP7142WAUJZ-R7
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
6-Lead LFCSP (2mm x 2mm w/ EP)
6-Lead LFCSP (2mm x 2mm w/ EP)
6-Lead LFCSP (2mm x 2mm w/ EP)
6-Lead LFCSP (2mm x 2mm w/ EP)
6-Lead LFCSP (2mm x 2mm w/ EP)
6-Lead LFCSP (2mm x 2mm w/ EP)
8-Lead SOIC w/ EP
8-Lead SOIC w/ EP
8-Lead SOIC w/ EP
8-Lead SOIC w/ EP
8-Lead SOIC w/ EP
8-Lead SOIC w/ EP
8-Lead SOIC w/ EP
8-Lead SOIC w/ EP
8-Lead SOIC w/ EP
8-Lead SOIC w/ EP
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
Reel, 3000
Reel, 3000
Reel, 3000
Reel, 3000
Reel, 3000
Reel, 3000
Tube, 98
Tube, 98
Reel, 1000
Tube, 98
Reel, 1000
Tube, 98
Reel, 1000
Tube, 98
Reel, 1000
Reel, 1000
Reel, 3000
Reel, 3000
Reel, 3000
Reel, 3000
Reel, 250
Reel, 3000
Reel, 3000
Reel, 3000
Reel, 3000
Reel, 3000
Reel, 3000
CP-6-3
CP-6-3
CP-6-3
CP-6-3
CP-6-3
CP-6-3
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.
analog.com
Marking Code
LP5
LP7
LP6
LVK
LP8
LP4
LP5
LP7
LP6
LP8
LP4
LP4
LVQ
LVR
LVT
LVS
LVU
Rev. I | 23 of 24
Data Sheet
ADP7142
OUTLINE DIMENSIONS
OUTPUT VOLTAGE OPTIONS
Model
Output Voltage (V)1
ADP7142ACPZN1.8-R7
ADP7142ACPZN2.5-R7
ADP7142ACPZN3.3-R7
ADP7142ACPZN3.8-R7
ADP7142ACPZN5.0-R7
ADP7142ACPZN-R7
ADP7142ARDZ
ADP7142ARDZ-1.8
ADP7142ARDZ-1.8-R7
ADP7142ARDZ-2.5
ADP7142ARDZ-2.5-R7
ADP7142ARDZ-3.3
ADP7142ARDZ-3.3-R7
ADP7142ARDZ-5.0
ADP7142ARDZ-5.0-R7
ADP7142ARDZ-R7
ADP7142AUJZ-1.8-R7
ADP7142AUJZ-2.5-R7
ADP7142AUJZ-3.3-R7
ADP7142AUJZ-5.0-R7
ADP7142AUJZ-R2
ADP7142AUJZ-R7
ADP7142WAUJZ-1.8-R7
ADP7142WAUJZ-2.5-R7
ADP7142WAUJZ-3.3-R7
ADP7142WAUJZ-5.0-R7
ADP7142WAUJZ-R7
1.8
2.5
3.3
3.8
5
Adjustable (1.2 V)
Adjustable (1.2 V)
1.8
1.8
2.5
2.5
3.3
3.3
5
5
Adjustable (1.2 V)
1.8
2.5
3.3
5
Adjustable (1.2 V)
Adjustable (1.2 V)
1.8
2.5
3.3
5
Adjustable (1.2 V)
1
For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative.
EVALUATION BOARDS
Model1, 2
Package Description
ADP7142UJ-EVALZ
ADP7142CP-EVALZ
ADP7142RD-EVALZ
TSOT Evaluation Board
LFCSP Evaluation Board
SOIC Evaluation Board
1
Z = RoHS Compliant Part.
2
The evaluation boards are preconfigured with an adjustable ADP7142.
AUTOMOTIVE PRODUCTS
The ADP7142W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should
review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive
applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific
Automotive Reliability reports for these models.
©2014-2022 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. I | 24 of 24
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