ADPD103BCBZRL7

Photometric Front End ADPD103 Data Sheet FEATURES GENERAL DESCRIPTION Multifunction photometric front end Fully integrated AFE, ADC, LED drivers, and timing core Usable in a broad range of optical measurement applications, including photoplethysmography Enables best-in-class ambient light rejection capability without the need for photodiode optical filters Three 8 mA to 250 mA LED drivers Separate data registers for each LED/photodiode combination 1 to 8 optical inputs Flexible, multiple, short LED pulses per optical sample 20-bit burst accumulator enabling 20 bits per sample period On-board sample to sample accumulator, enabling up to 27 bits per data read Low power operation I2C interface and 1.8 V analog/digital core Flexible sampling frequency ranging from 0.122 Hz to 3.820 kHz FIFO data operation The ADPD103 is a highly efficient photometric front end with an integrated 14-bit analog-to-digital converter (ADC) and a 20-bit burst accumulator that works in concert with flexible light emitting diode (LED) drivers. It is designed to stimulate an LED and measure the corresponding optical return signal. The data output and functional configuration occur over a 1.8 V I2C interface. The control circuitry includes flexible LED signaling and synchronous detection. The analog front end (AFE) features best-in-class rejection of signal offset and corruption due to modulated interference commonly caused by ambient light. Couple the ADPD103 with a low capacitance photodiode of 0x3FFF ADPD103 Data Sheet LED SLOTx_AFE_OFFSET + 9 SUB ADD SUB 12722-021 SAMPLE Figure 27. Digital Integration Mode in Double-Sample Pair Mode with Continuous Sample Timing LED SAMPLE SUB ADD AFE_FOFFSET SUB AFE_FOFFSET 12722-022 SLOTx_AFE_OFFSET + 9 Figure 28. Digital Integration Mode in Double-Sample Pair Mode with Gapped Sample Timing LED SAMPLE SUB ADD AFE_FOFFSET 12722-023 SLOTx_AFE_OFFSET + 9 Figure 29. Digital Integration Mode in Single-Sample Pair Mode with Gapped Sample Timing LED SLOTx_AFE_OFFSET + 9 SUB ADD Figure 30. Digital Integration Mode in Single-Sample Pair Mode with Continuous Sample Timing Rev. B | Page 32 of 52 12722-024 SAMPLE Data Sheet ADPD103 Table 18. Configuration Registers to Switch Between the Normal Sample Mode, TIA_ADC Mode, and Digital Integration Mode Bit Name SLOTA_AFE_MODE Normal Mode Value 0x1C TIA_ADC Mode Value Not applicable Digital Integration Mode Value 0x1D [15:0] SLOTA_AFE_CFG 0xADA5 0xB065 0xAE65 0x44 [15:8] SLOTB_AFE_MODE 0x1C Not applicable 0x1D 0x45 [15:0] SLOTB_AFE_CFG 0xADA5 0xB065 0xAE65 0x4E [15:0] ADC_TIMING Not applicable 0x0040 0x58 13 SLOTB_DIGITAL_INT_EN Not applicable 0x0 0x0 0x1 12 SLOTA_DIGITAL_INT_EN 0x0 0x0 0x1 [15:0] DIG_INT_CFG Not applicable Not applicable Variable Address 0x42 Data Bits [15:8] 0x43 0x5A Rev. B | Page 33 of 52 Description In normal mode, this setting configures the integrator block for optimal operation. In digital integration mode, this setting configures the integrator block as a buffer. This setting is not important for TIA_ADC mode. Time Slot A AFE connection. 0xAE65 bypasses the band-pass filter. 0xB065 bypasses the band-pass filter and the integrator. In normal mode, this setting configures the integrator block for optimal operation. In digital integration mode, this setting configures the integrator block as a buffer. This setting is not important for TIA_ADC mode. Time Slot B AFE connection. 0xAE65 bypasses the band-pass filter. 0xB065 bypasses the BPF and the integrator. Set ADC Clock to 1 MHz in TIA_ADC mode. Digital integrate mode enable Time Slot B. 0: disable. 1: enable. Digital integrate mode enable Time Slot A. 0: disable. 1: enable. Configuration of digital integration depends on the use case. This register is ignored for other modes. ADPD103 Data Sheet REGISTER LISTING Table 19. Numeric Register Listing 1 Hex Addr Name Bits 0x00 Status [15:8] [7:0] 0x01 0x02 0x06 0x08 0x09 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved SLOTB_ INT SLOTA_INT [15:8] INT_IO_ CTL [15:8] FIFO_ THRESH [15:8] [7:0] Reserved[7:0] DEVID [15:8] REV_NUM[15:8] [7:0] DEV_ID[7:0] I2CS_ID Reserved[15:9] Reserved SLOTB_INT_ SLOTA_INT_ MASK MASK 0x0D 0x0F 0x10 CLK_ RATIO Reserved[7:3] INT_ENA Reserved[15:14] 0x12 FSAMPLE [15:8] [7:0] 0x15 0x18 0x19 0x1A 0x1B 0x1E 0x1F 0x20 0x21 0x0416 R 0x00C8 R/W 0x0000 R 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x1000 R/W 0x0028 R/W 0x0541 R/W 0x0600 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 RW SLAVE_ADDRESS_KEY[15:8] SLAVE_ADDRESS_KEY[7:0] Reserved[15:8] Reserved[7:1] SW_RESET Reserved[15:8] Reserved[7:2] Reserved[15:14] RDOUT_M ODE SLOTB_FIFO_MODE[7:6] SLOTB_EN Mode[1:0] FIFO_OVRN_ PREVENT Reserved[11:9] SLOTA_FIFO_MODE[4:2] SLOTB_FIFO_ MODE Reserved SLOTA_EN FSAMPLE[15:8] FSAMPLE[7:0] PD_LED_ [15:8] SELECT [7:0] Reserved[15:12] SLOTA_PD_SEL[7:4] SLOTB_PD_SEL[11:8] SLOTB_LED_SEL[3:2] NUM_ AVG [15:8] SLOTA_ CH1_ OFFSET [15:8] SLOTA_CH1_OFFSET[15:8] [7:0] SLOTA_CH1_OFFSET[7:0] SLOTA_ CH2_ OFFSET [15:8] SLOTA_CH2_OFFSET[15:8] [7:0] SLOTA_CH2_OFFSET[7:0] SLOTA_ CH3_ OFFSET [15:8] SLOTA_CH3_OFFSET[15:8] [7:0] SLOTA_CH3_OFFSET[7:0] SLOTA_ CH4_ OFFSET [15:8] SLOTA_CH4_OFFSET[15:8] [7:0] SLOTA_CH4_OFFSET[7:0] SLOTB_ CH1_ OFFSET [15:8] SLOTB_CH1_OFFSET[15:8] [7:0] SLOTB_CH1_OFFSET[7:0] SLOTB_ CH2_ OFFSET [15:8] SLOTB_CH2_OFFSET[15:8] [7:0] SLOTB_CH2_OFFSET[7:0] SLOTB_ CH3_ OFFSET [15:8] SLOTB_CH3_OFFSET[15:8] [7:0] SLOTB_CH3_OFFSET[7:0] SLOTB_ CH4_ OFFSET [15:8] SLOTB_CH4_OFFSET[15:8] [7:0] SLOTB_CH4_OFFSET[7:0] [7:0] R/W CLK_RATIO[11:8] [7:0] 0x14 0x0000 CLK_RATIO[7:0] [7:0] SLOT_EN [15:8] R/W Reserved Reserved[15:12] [7:0] 0x11 0x0000 INT_POL ADDRESS_WRITE_KEY[15:8] SLAVE_ [15:8] ADDRESS [7:0] _KEY [15:8] INT_DRV FIFO_THRESH[13:8] [7:0] Mode R/W SLAVE_ADDRESS[7:1] [15:8] [15:8] FIFO_INT_MASK 0x00FF Reserved[4:0] [15:8] SW_ RESET R/W Reserved[15:8] [7:0] [7:0] 0x0A RW 0x0000 Reserved[4:0] INT_ MASK [7:0] Reset FIFO_SAMPLES[15:8] Reserved Reserved SLOTA_LED_SEL[1:0] SLOTB_NUM_AVG SLOTA_NUM_AVG Reserved Rev. B | Page 34 of 52 Data Sheet Hex ADPD103 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Addr Name Bits 0x22 ILED3_ COARSE [15:8] 0x23 ILED1_ COARSE 0x24 ILED2_ COARSE [15:8] 0x25 ILED_ FINE [15:8] SLOTA_ LED_ PULSE [15:8] [7:0] SLOTA_LED_OFFSET[7:0] SLOTA_ NUMPULSES [15:8] SLOTA_LED_NUMBER[15:8] [7:0] SLOTA_LED_PERIOD[7:0] [7:0] [15:8] [7:0] [7:0] 0x30 0x31 [7:0] Reserved[15:14] ILED3_ SCALE Reserved Reserved[12:8] ILED3_SLEW[6:4] Reserved[15:14] Reserved[12:8] ILED1_SLEW[6:4] Reserved[15:14] Reserved[12:8] ILED2_SLEW[6:4] ILED2_FINE[10:8] Reserved Reserved[15:13] SLOTA_LED_WIDTH[12:8] LED_ [15:8] DISABLE 0x35 SLOTB_ LED_ PULSE Reserved[15:10] [15:8] [7:0] SLOTB_LED_OFFSET[7:0] SLOTB_ NUMPULSES [15:8] SLOTB_LED_NUMBER[15:8] [7:0] SLOTB_LED_PERIOD[7:0] [7:0] SLOTA_ [15:8] AFE_ [7:0] WINDOW Reserved EXT_SYNC_ ENA Reserved[13:8] SLOTA_AFE_OFFSET[10:5] SLOTB_ [15:8] AFE_ [7:0] WINDOW SLOTB_AFE_OFFSET[10:5] [7:0] 0x42 SLOTA_ [15:8] TIA_CFG [7:0] 0x44 0x45 0x4B 0x4D 0x4E Reserved[15:14] 0x4F SLOTA_AFE_OFFSET[10:8] SLOTB_AFE_OFFSET[10:8] Reserved AFE_POWERDOWN[7:3] V_ CATHODE AFE_ POWER-DOWN 0x0320 R/W 0x0818 R/W 0x0000 R/W 0x0320 R/W 0x0818 R/W 0x000 R/W 0x22FC R/W 0x22FC R/W 0x3006 R/W 0x1C38 R/W 0xADA5 R/W 0x1C38 R/W 0xADA5 R/W 0x2612 R/W 0x425E R/W 0x0060 R/W 0x2090 R/W Reserved[2:0] SLOTA_AFE_MODE[15:8] Reserved Reserved[5:2] (write 0xD) SLOTA_ TIA_ IND_EN SLOTA_TIA_GAIN[1:0] SLOTA_AFE_CFG[15:8] SLOTA_AFE_CFG[7:0] SLOTB_AFE_MODE[15:8] Reserved Reserved[5:2] (write 0xD) SLOTB_ TIA_ IND_EN SLOTB_TIA_GAIN[1:0] SLOTB_AFE_CFG[15:8] SLOTB_AFE_CFG[7:0] SAMPLE_ [15:8] CLK [7:0] CLK32K_EN Reserved[15:8] Reserved CLK32K_ADJUST[5:0] CLK32M_ [15:8] ADJUST [7:0] RESERVED[15:8] CLK32M_ADJUST[7:0] [15:8] ADC_CLOCK[15:8] [7:0] ADC_CLOCK[7:0] EXT_ [15:8] SYNC_SEL [7:0] R/W SLOTB_AFE_FOFFSET[4:0] Reserved[13:11] SLOTB_ [15:8] AFE_CFG [7:0] ADC_ CLOCK 0x630C SLOTA_AFE_FOFFSET[4:0] SLOTB_AFE_WIDTH[15:11] SLOTA_ [15:8] AFE_CFG [7:0] SLOTB_ [15:8] TIA_CFG [7:0] R/W Reserved[7:0] SLOTA_AFE_WIDTH[15:11] [7:0] 0x43 SLOTA_ LED_DIS SLOTB_LED_WIDTH[12:8] 0x39 AFE_PWR [15:8] _CFG1 0x3000 Reserved[7:0] TIMING_ [15:8] CFG 0x3C SLOTB_LED_ DIS Reserved[15:13] 0x38 0x3B R/W ILED1_FINE[4:0] 0x34 0x36 0x3000 ILED2_COARSE[3:0] ILED3_FINE[15:11] ILED2_FINE[7:6] R/W ILED1_COARSE[3:0] ILED2_ SCALE Reserved RW 0x3000 ILED3_COARSE[3:0] ILED1_ SCALE Reserved Reset Reserved[15:8] Reserved PDSO_ OE PDSO_IE Reserved EXT_SYNC_SEL[3:2] Rev. B | Page 35 of 52 INT_IE Reserved ADPD103 Data Sheet Hex Addr Name 0x50 CLK32M_ [15:8] CAL_EN [7:0] 0x54 Bits AFE_PWR [15:8] _CFG2 [7:0] 0x55 TIA_INDEP_ GAIN [15:8] [7:0] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved SLOTB_SINGLE_CH_ DIG_INT PDSO_ CTRL SLOTA_ SINGLE_ CH_DIG_ INT DIG_INT_ [15:8] CFG [7:0] DIG_INT_ GAPMODE Reserved[15:14] 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x70 0x71 0x72 0x73 0x74 Reserved SLOTA_TIA_GAIN_4[5:4] SLOTB_ DIGITAL_ INT_EN [7:0] 0x64 SLOTA_V_CATHODE[9:8] 0x0020 R/W SLOTB_TIA_GAIN_4 [11:10] SLOTB_TIA_GAIN_3[9:8] 0x0000 R/W SLOTA_TIA_GAIN_3[3:2] SLOTA_TIA_GAIN_2[1:0] 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R Reserved[4:0] SLEEP_V_CATHODE[13:12] DIGINT_POWER[15:13] 0x5A 0x60 R/W SLOTB_V_ CATHODE[11:10] Reserved[6:0] SLOTB_TIA_GAIN_2[7:6] DIGITAL_ [15:8] INT_EN DATA_AC [15:8] CESS_ [7:0] CTL RW 0x0000 CLK32M_ CAL_EN REG54_VCAT_ ENABLE 0x58 0x5F Reset Reserved[15:8] Reserved[11:8] SLOTA_ DIGITAL_INT_ EN Reserved[7:0] Reserved[15:8] SLOTB_ DIG_INT_ SAMPLEMODE Reserved[4:0] SLOTA_ DIG_INT_ SAMPLEMODE Reserved[15:8] Reserved[7:3] SLOTB_ DATA_ HOLD FIFO_ ACCESS [15:8] FIFO_DATA[15:8] [7:0] FIFO_DATA[7:0] SLOTA_ PD1_ 16BIT [15:8] SLOTA_CH1_16BIT[15:8] [7:0] SLOTA_CH1_16BIT[7:0] SLOTA_ PD2_ 16BIT [15:8] SLOTA_CH2_16BIT[15:8] [7:0] SLOTA_CH2_16BIT[7:0] SLOTA_ PD3_ 16BIT [15:8] SLOTA_CH3_16BIT[15:8] [7:0] SLOTA_CH3_16BIT[7:0] SLOTA_ PD4_ 16BIT [15:8] SLOTA_CH4_16BIT[15:8] [7:0] SLOTA_CH4_16BIT[7:0] SLOTB_ PD1_ 16BIT [15:8] SLOTB_CH1_16BIT[15:8] [7:0] SLOTB_CH1_16BIT[7:0] SLOTB_ PD2_ 16BIT [15:8] SLOTB_CH2_16BIT[15:8] [7:0] SLOTB_CH2_16BIT[7:0] SLOTB_ PD3_ 16BIT [15:8] SLOTB_CH3_16BIT[15:8] [7:0] SLOTB_CH3_16BIT[7:0] SLOTB_ PD4_ 16BIT [15:8] SLOTB_CH4_16BIT[15:8] [7:0] SLOTB_CH4_16BIT[7:0] A_PD1_ LOW [15:8] SLOTA_CH1_LOW[15:8] [7:0] SLOTA_CH1_LOW[7:0] A_PD2_ LOW [15:8] SLOTA_CH2_LOW[15:8] [7:0] SLOTA_CH2_LOW[7:0] A_PD3_ LOW [15:8] SLOTA_CH3_LOW[15:8] [7:0] SLOTA_CH3_LOW[7:0] A_PD4_ LOW [15:8] SLOTA_CH4_LOW[15:8] [7:0] SLOTA_CH4_LOW[7:0] A_PD1_ HIGH [15:8] SLOTA_CH1_HIGH[15:8] [7:0] SLOTA_CH1_HIGH[7:0] Rev. B | Page 36 of 52 SLOTA_DAT A_HOLD DIGITAL_ CLOCK_ENA Data Sheet Hex ADPD103 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Addr Name Bits 0x75 A_PD2_ HIGH [15:8] SLOTA_CH2_HIGH[15:8] [7:0] SLOTA_CH2_HIGH[7:0] A_PD3_ HIGH [15:8] SLOTA_CH3_HIGH[15:8] [7:0] SLOTA_CH3_HIGH[7:0] A_PD4_ HIGH [15:8] SLOTA_CH4_HIGH[15:8] [7:0] SLOTA_CH4_HIGH[7:0] B_PD1_ LOW [15:8] SLOTB_CH1_LOW[15:8] [7:0] SLOTB_CH1_LOW[7:0] B_PD2_ LOW [15:8] SLOTB_CH2_LOW[15:8] [7:0] SLOTB_CH2_LOW[7:0] B_PD3_ LOW [15:8] SLOTB_CH3_LOW[15:8] [7:0] SLOTB_CH3_LOW[7:0] B_PD4_ LOW [15:8] SLOTB_CH4_LOW[15:8] [7:0] SLOTB_CH4_LOW[7:0] B_PD1_ HIGH [15:8] SLOTB_CH1_HIGH[15:8] [7:0] SLOTB_CH1_HIGH[7:0] B_PD2_ HIGH [15:8] SLOTB_CH2_HIGH[15:8] [7:0] SLOTB_CH2_HIGH[7:0] B_PD3_ HIGH [15:8] SLOTB_CH3_HIGH[15:8] [7:0] SLOTB_CH3_HIGH[7:0] B_PD4_ HIGH [15:8] SLOTB_CH4_HIGH[15:8] [7:0] SLOTB_CH4_HIGH[7:0] 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 1 Reset RW 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R Recommended values not shown. Only power-on reset values are in Table 19. The recommended values are largely dependent on use case. See Table 20 to Table 26 for the recommended values. Rev. B | Page 37 of 52 ADPD103 Data Sheet LED CONTROL REGISTERS Table 20. LED Control Registers Address 0x14 0x22 Data Bit [15:12] [11:8] Default Value 0x0 0x5 Access R/W R/W Name Reserved SLOTB_PD_SEL [7:4] 0x4 R/W SLOTA_PD_SEL [3:2] 0x0 R/W SLOTB_LED_SEL [1:0] 0x1 R/W SLOTA_LED_SEL [15:14] 13 0x0 0x1 R/W R/W Reserved ILED3_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED3_SLEW [3:0] 0x0 R/W ILED3_COARSE Description Write 0x0 to these bits for proper operation. PDx connection selection for Time Slot B. See Figure 13. 0x1: All photodiode inputs are connected during Time Slot B. 0x4: PD5/PD6/PD7/PD8 are connected during Time Slot B. 0x5: PD1/PD2/PD3/PD4 are connected during Time Slot B. Other: reserved. PDx connection selection for Time Slot A. See Figure 13. 0x1: All photodiode inputs are connected during Time Slot A. 0x4: PD5/PD6/PD7/PD8 are connected during Time Slot A. 0x5: PD1/PD2/PD3/PD4 are connected during Time Slot A. Other: reserved. Time Slot B LED configuration. These bits determine which LED is associated with Time Slot B. 0x0: reserved. 0x1: LEDX1 pulses during Time Slot B. 0x2: LEDX2 pulses during Time Slot B. 0x3: LEDX3 pulses during Time Slot B. Time Slot A LED configuration. These bits determine which LED is associated with Time Slot A. 0x0: reserved. 0x1: LEDX1 pulses during Time Slot A. 0x2: LEDX2 pulses during Time Slot A. 0x3: LEDX3 pulses during Time Slot A. Write 0x0. LEDX3 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX3 driver in low power mode. LEDX3 Current Scale = 0.4 + 0.6 × (Register 0x22, Bit 13). Write 0x1. Write 0x0. LEDX3 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0: the slowest slew rate. … 7: the fastest slew rate. LEDX3 coarse current setting. Coarse current sink target value of LEDX3 in standard operation. 0: 25 mA. 1: 40 mA. 2: 55 mA. … 15: 250 mA. LED3PEAK = LED3COARSE × LED3FINE × LED3SCALE where: LED3PEAK is the LEDX3 peak target value (mA). LED3COARSE = 28 + 15.46 × (Register 0x22, Bits[3:0]). LED3FINE = 0.71 + 0.024 × (Register 0x25, Bits[15:11]). LED3SCALE = 0.4 + 0.6 × (Register 0x22, Bit 13). Rev. B | Page 38 of 52 Data Sheet Address 0x23 0x24 ADPD103 Data Bit [15:14] 13 Default Value 0x0 0x1 Access R/W R/W Name Reserved ILED1_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED1_SLEW [3:0] 0x0 R/W ILED1_COARSE [15:14] 13 0x0 0x1 R/W R/W Reserved ILED2_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED2_SLEW [3:0] 0x0 R/W ILED2_COARSE Description Write 0x0. LEDX1 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX1 driver in low power mode. LEDX1 Current Scale = 0.4 + 0.6 × (Register 0x23, Bit 13). Write 0x1. Write 0x0. LEDX1 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0: the slowest slew rate. … 7: the fastest slew rate. LEDX1 coarse current setting. Coarse current sink target value of LEDX1 in standard operation. 0: 25 mA. 1: 40 mA. 2: 55 mA. … 15: 250 mA. LED1PEAK = LED1COARSE × LED1FINE × LED1SCALE where: LED1PEAK is the LEDX1 peak target value (mA). LED1COARSE = 28 + 15.46 × (Register 0x23, Bits[3:0]). LED1FINE = 0.71 + 0.024 × (Register 0x25, Bits[4:0]). LED1SCALE = 0.4 + 0.6 × (Register 0x23, Bit 13). Write 0x0. LEDX2 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX2 driver in low power mode. LED2 Current Scale = 0.4 + 0.6 × (Register 0x24, Bit 13) Write 0x1. Write 0x0. LEDX2 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0: the slowest slew rate. … 7: the fastest slew rate. LEDX2 coarse current setting. Coarse current sink target value of LED2 in standard operation. See Register 0x23, Bits[3:0] for values. LED2PEAK = LED2COARSE × LED2FINE × LED2SCALE where: LED2PEAK is the LEDX2 peak target value (mA). LED2COARSE = 28 + 15.46 × (Register 0x24, Bits[3:0]). LED2FINE = 0.71 + 0.024 × (Register 0x25, Bits[10:6]). LED2SCALE = 0.4 + 0.6 × (Register 0x24, Bit 13). Rev. B | Page 39 of 52 ADPD103 Address 0x25 0x30 0x31 0x34 0x35 0x36 0x3C Data Sheet Data Bit [15:11] Default Value 0xC Access R/W Name ILED3_FINE [10:6] 0xC R/W ILED2_FINE 5 [4:0] 0x0 0xC R/W R/W Reserved ILED1_FINE [15:13] [12:8] [7:0] [15:8] 0x0 0x3 0x20 0x08 R/W R/W R/W R/W Reserved SLOTA_LED_WIDTH SLOTA_LED_OFFSET SLOTA_LED_NUMBER [7:0] [15:10] 9 0x18 0x00 0x0 R/W R/W R/W SLOTA_LED_PERIOD Reserved SLOTB_LED_DIS 8 0x0 R/W SLOTA_LED_DIS [7:0] [15:13] [12:8] [7:0] [15:8] 0x00 0x0 0x3 0x20 0x08 R/W R/W R/W Reserved Reserved SLOTB_LED_WIDTH SLOTB_LED_OFFSET SLOTB_LED_NUMBER [7:0] [15:14] [13:11] 10 9 0x18 0x0 0x6 0x0 0x0 R/W R/W R/W R/W R/W SLOTB_LED_PERIOD RESERVED RESERVED Reserved V_CATHODE [8:3] 0x0 R/W AFE_POWERDOWN [2:0] 0x6 R/W Reserved Description LEDX3 fine adjust. Current adjust multiplier for LED3. LEDX3 fine adjust = 0.71 + 0.024 × (Register 0x25, Bits[15:11]). See Register 0x22, Bits[3:0], for the full LED3 formula. LEDX2 fine adjust. Current adjust multiplier for LED2. LEDX2 fine adjust = 0.71 + 0.024 × (Register 0x25, Bits[10:6]). See Register 0x24, Bits[3:0], for the full LED2 formula. Write 0x0. LEDX1 fine adjust. Current adjust multiplier for LED1. LEDX1 fine adjust = 0.71 + 0.024 × (Register 0x25, Bits[4:0]). See Register 0x23, Bits[3:0], for the full LED1 formula. Write 0x0. LED pulse width (in 1 μs step) for Time Slot A. LED offset width (in 1 μs step) for Time Slot A. LED Time Slot A pulse count. nA: number of LED pulses in Time Slot A. This is typically LED1. Adjust in the application. A setting of six pulses (0x06) is typical. LED Time Slot A pulse period (in 1 μs step). Write 0x0. Time Slot B LED disable. 1: disables the LED assigned to Time Slot B. Register 0x34 keeps the drivers active and prevents them from pulsing current to the LEDs. Disabling both LEDs via this register is often used to measure the dark level. Use Register 0x11 instead to enable or disable the actual time slot usage and not only the LED. Time Slot A LED disable. 1: disables the LED assigned to Time Slot A. Use Register 0x11 instead to enable or disable the actual time slot usage and not only the LED. Write 0x00. Write 0x0. LED pulse width (in 1 μs step) for Time Slot B. LED offset width (in 1 μs step) for Time Slot B. LED Time Slot B pulse count. nB: number of LED pulses in Time Slot B. This is typically LED2. A setting of six pulses (0x06) is typical. LED Time Slot B pulse period (in 1 μs step). Write 0x0. Write 0x6. Write 0x0. 0x0: 1.3 V (identical to anode voltage); recommended setting. 0x1: 1.8 V (reverse bias photodiode by 550 mV; this setting may add noise). AFE channels power-down select. 0x38: powers down AFE Channel 2, Channel 3, and Channel 4. 0x0: keeps all channels on. Write 0x6. Rev. B | Page 40 of 52 Data Sheet ADPD103 AFE CONFIGURATION REGISTERS Table 21. AFE Global Configuration Registers Address 0x3C 0x54 Data Bit [15:14] [13:11] Default Value 0x0 0x6 Access R/W R/W Name RESERVED RESERVED Description Write 0x0. Write 0x6. 10 0x0 R/W Reserved Write 0x0. 9 0x0 R/W V_CATHODE [8:3] 0x0 R/W AFE_POWERDOWN 0x0: 1.3 V (identical to anode voltage); recommended setting. 0x1: 1.8 V (reverse bias photodiode by 550 mV. This setting may add noise). AFE channels power-down select. 0x38: powers down AFE Channel 2, Channel 3, and Channel 4. 0x0: keeps all channels on. [2:0] 0x6 R/W Reserved Write 0x6. 15 0x0 R/W SLOTB_SINGLE_CH_DIG_INT 14 0x0 R/W SLOTA_SINGLE_CH_DIG_INT [13:12] 0x0 R/W SLEEP_V_CATHODE 0: In Time Slot B, use all four photodiode channels in parallel for digital integration (default setting for highest dynamic range) 1: In Time Slot B, use only Channel 1 for digital integration. This limits connection to PD1 or PD5. 0: In Time Slot A, use all four photodiode channels in parallel for digital integration (default setting for highest dynamic range) 1: In Time Slot A, use only Channel 1 for digital integration. This limits connection to PD1 or PD5. If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in sleep mode. The anode voltage is always set to the cathode voltage in sleep mode. 0x0: VDD (1.8 V). 0x1: 1.3 V. 0x2: 1.55 V. 0x3: 0.0 V. [11:10] 0x0 R/W SLOTB_V_CATHODE If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in Time Slot B operation. The anode voltage is always 1.3 V in Time Slot B mode. 0x0: VDD (1.8 V). 0x1: 1.3 V. 0x2: 1.55 V. 0x3: 0.0 V (this forward biases a diode at the input). [9:8] 0x0 R/W SLOTA_V_CATHODE If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in Time Slot A operation. The anode voltage is always 1.3 V in Time Slot A mode. 0x0: VDD (1.8 V). 0x1: 1.3 V. 0x2: 1.55 V. 0x3: 0.0 V (this forward biases a diode at the input). 7 0x0 R/W REG54_VCAT_ENABLE [6:0] 0x20 R/W Reserved 0: use the cathode voltage settings defined by Register 0x3C, Bit 9. 1: override Register 0x3C, Bit 9 with cathode settings defined by Register 0x54, Bits[13:8]. Write 0x20. Rev. B | Page 41 of 52 ADPD103 Address 0x58 0x5A Data Sheet Data Bit [15:14] 13 Default Value 0x0 0x0 Access R/W R/W Name Reserved SLOTB_DIGITAL_INT_EN 12 0x0 R/W SLOTA_DIGITAL_INT_EN [11:0] [15:8] 7 0x000 0x00 0x0 R/W R/W R/W Reserved Reserved DIG_INT_GAPMODE 6 0x0 R/W SLOTB_DIG_INT_SAMPLE_MODE 5 0x0 R/W SLOTA_DIG_INT_SAMPLE_MODE [4:0] 0x00 R/W Reserved Description Write 0x0. 0x0: Time Slot B operating in normal mode. 0x1: Time Slot B operating in digital integration mode. 0x0: Time Slot A operating in normal mode. 0x1: Time Slot A operating in digital integration mode. Write 0x000. Write 0x00. Digital integrate gapped mode enable. 0: no gap between negative and positive sample regions. 1: use SLOTA_AFE_FOFFSET for Time Slot A or SLOTB_AFE_ FOFFSET for Time Slot B to specify the gap in μs. Digital integrate single sample pair mode for Time Slot B. 0: double sample pair mode. 1: single sampled pair mode. Digital integrate single sample pair mode for Time Slot A. 0: double sample pair mode. 1: single sampled pair mode. Write 0x00. Table 22. AFE Configuration Registers, Time Slot A Address 0x39 0x42 Data Bit [15:11] [10:5] Default Value 0x4 0x17 Access R/W R/W Name SLOTA_AFE_WIDTH SLOTA_AFE_OFFSET [4:0] 0x1C R/W SLOTA_AFE_FOFFSET [15:8] 0x1C R/W SLOTA_AFE_MODE 7 6 0x0 0x0 R/W R/W Reserved SLOTA_TIA_IND_EN [5:2] [1:0] 0xE 0x0 R/W R/W Reserved SLOTA_TIA_GAIN Description AFE integration window width (in 1 μs step) for Time Slot A. AFE integration window coarse offset (in 1 μs step) for Time Slot A. AFE integration window fine offset (in 31.25 ns step) for Time Slot A. 0x1C: Time Slot A AFE setting for normal mode. All four blocks of the signal chain are in use during normal mode (the TIA, the BPF, followed by the integrator (INT), and finally the ADC). 0x1D: Time Slot A AFE setting for digital integrate mode. Write 0x0. Enable Time Slot A TIA gain individual settings. When it is enabled, the Channel 1 TIA gain is set via Register 0x42, Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set via Register 0x55, Bits[5:0]. 0: disable TIA gain individual setting. 1: enable TIA gain individual setting. Reserved. Write 0xD. Transimpedance amplifier gain for Time Slot A. When SLOTA_TIA_IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When SLOTA_TIA_IND_EN is disabled, it is for all four Time Slot A channel TIA gain settings. 0: 200 kΩ. 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. Rev. B | Page 42 of 52 Data Sheet ADPD103 Address 0x43 Data Bit [15:0] Default Value 0xADA5 Access R/W Name SLOTA_AFE_CFG 0x55 [15:13] 0x0 R/W DIGINT_POWER 12 [11:10] 0x0 0x0 R/W R/W Reserved SLOTB_TIA_GAIN_4 [9:8] 0x0 R/W SLOTB_TIA_GAIN_3 [7:6] 0x0 R/W SLOTB_TIA_GAIN_2 [5:4] 0x0 R/W SLOTA_TIA_GAIN_4 [3:2] 0x0 R/W SLOTA_TIA_GAIN_3 [1:0] 0x0 R/W SLOTA_TIA_GAIN_2 Description AFE connection in Time Slot A. 0xADA5: analog full path mode (TIA_BPF_INT_ADC). 0xB065: TIA_ADC mode. 0xAE65: digital integration mode. Others: reserved. Power-down for Channel 2, Channel 3, and Channel 4 in digital integration mode. 0: keep all channels powered up. 7: powers down Channel 2, Channel 3, and Channel 4. Write 0x0. TIA gain for Time Slot B, Channel 4 (PD4). 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. TIA gain for Time Slot B, Channel 3 (PD3). 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. TIA gain for Time Slot B, Channel 2 (PD2). 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. TIA gain for Time Slot A, Channel 4 (PD4). 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. TIA gain for Time Slot A, Channel 3 (PD3). 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. TIA gain for Time Slot A, Channel 2 (PD2). 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. Rev. B | Page 43 of 52 ADPD103 Address 0x5A Data Sheet Data Bit [15:8] 7 Default Value 0x0 0x0 Access R/W R/W Name Reserved DIG_INT_GAPMODE 6 0x0 R/W SLOTB_DIG_INT_SAMPLEMODE 5 0x0 R/W SLOTA_DIG_INT_SAMPLEMODE [4:0] 0x0 R/W Reserved Description Write 0x0. Digital integration gapped mode enable. 0: no gap between negative and positive sample regions. 1: use SLOTA_AFE_FOFFSET for Time Slot A or SLOTB_AFE_ FOFFSET for Time Slot B to specify the gap in μs. Digital integration single-sample pair mode for Time Slot B. 0: double sample pair mode. 1: single-sampled pair mode. Digital integration single-sample pair mode for Time Slot A. 0: double sample pair mode. 1: single-sampled pair mode. Write 0x0. Table 23. AFE Configuration Registers, Time Slot B Address 0x3B 0x44 0x45 Data Bit [15:11] [10:5] Default Value 0x4 0x17 Access R/W R/W Name SLOTB_AFE_WIDTH SLOTB_AFE_OFFSET [4:0] 0x1C R/W SLOTB_AFE_FOFFSET [15:8] 0x1C R/W SLOTB_AFE_MODE 7 6 0x0 0x0 R/W R/W Reserved SLOTB_TIA_IND_EN [5:2] [1:0] 0xE 0x0 R/W R/W Reserved SLOTB_TIA_GAIN [15:0] 0xADA5 R/W SLOTB_AFE_CFG Rev. B | Page 44 of 52 Description AFE integration window width (in 1 μs step) for Time Slot B. AFE integration window coarse offset (in 1 μs step) for Time Slot B. AFE integration window fine offset (in 31.25 ns step) for Time Slot B. 0x1C: Time Slot B AFE setting for normal mode (TIA_BPF_INT_ADC). 0x1D: Time Slot B AFE setting for digital integrate mode. Write 0x0. Enable Time Slot B TIA gain individual settings. When it is enabled, the Channel 1 TIA gain is set via Register 0x44, Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set via Register 0x55, Bits[11:6]. 0: disable TIA gain individual setting. 1: enable TIA gain individual setting. Write 0xD. Transimpedance amplifier gain for Time Slot B. When SLOTB_TIA_IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When SLOTB_TIA_IND_EN is disabled, it is for all four Time Slot B channel TIA gain settings. 0: 200 kΩ. 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. AFE connection in Time Slot B. 0xADA5: analog full path mode (TIA_BPF_INT_ADC). 0xB065: TIA_ADC mode. 0xAE65: digital integration mode. Others: reserved. Data Sheet Address 0x58 ADPD103 Data Bit [15:14] 13 Default Value 0x0 0x0 Access R/W R/W Name Reserved DIG_INT_EN_B 12 0x0 R/W DIG_INT_EN_A [11:0] 0x0000 R/W Reserved Rev. B | Page 45 of 52 Description Write 0x0. Digital integration mode, enable Time Slot B. 0: disable. 1: enable. Digital integration mode, enable Time Slot A. 0: disable. 1: enable. Write 0x0000. ADPD103 Data Sheet SYSTEM REGISTERS Table 24. System Registers Address 0x00 0x01 0x02 0x06 0x08 Data Bit [15:8] Default 0x00 Access R/W Name FIFO_SAMPLES 7 6 0x0 0x0 R/W R/W Reserved SLOTB_INT 5 0x0 R/W SLOTA_INT [4:0] [15:9] 8 0x00 0x00 0x0 R/W R/W R/W Reserved Reserved FIFO_INT_MASK 7 6 0x1 0x1 R/W R/W Reserved SLOTB_INT_MASK 5 0x1 R/W SLOTA_INT_MASK [4:0] [15:3] 2 0x1F 0x0000 0x0 R/W R/W R/W Reserved Reserved INT_ENA 1 0x0 R/W INT_DRV 0 0x0 R/W INT_POL [15:14] [13:8] 0x0 0x00 R/W R/W Reserved FIFO_THRESH [7:0] [15:8] [7:0] 0x00 0x04 0x16 R/W R R Reserved REV_NUM DEV_ID Description FIFO status. Number of available bytes to be read from the FIFO. When comparing this to the FIFO length threshold (Register 0x06, Bits[13:8]), note that the FIFO status value is in bytes and the FIFO length threshold is in words, where one word = two bytes. With the FIFO_ACCESS_ENA bit set, write 1 to Bit 15 of FIFO_SAMPLES to clear the contents of the FIFO. Write 0x1 to clear this bit to 0x0. Time Slot B interrupt. Describes the type of interrupt event. A 1 indicates an interrupt of a particular event type has occurred. Write a 1 to clear the corresponding interrupt. After clearing, the register goes to 0. Writing a 0 to this register has no effect. Time Slot A interrupt. Describes the type of interrupt event. A 1 indicates an interrupt of a particular event type has occurred. Write a 1 to clear the corresponding interrupt. After clearing, the register goes to 0. Writing a 0 to this register has no effect Write 0x1F to clear these bits to 0x00. Write 0x00. Sends an interrupt when the FIFO data length has exceeded the FIFO length threshold in Register 0x06, Bits[13:8]. A 0 enables the interrupt. Write 0x1. Sends an interrupt on the Time Slot B sample. Write a 1 to disable the interrupt. Write a 0 to enable the interrupt. Sends an interrupt on the Time Slot A sample. Write a 1 to disable the interrupt. Write a 0 to enable the interrupt. Write 0x1F. Write 0x0000. INT pin enable. 0: disable the INT pin. The INT pin floats regardless of interrupt status. The status register (Address 0x00) remains active. 1: enable the INT pin. INT drive. 0: the INT pin is always driven. 1: the INT pin is driven when the interrupt is asserted; otherwise, it is left floating and requires a pull-up or pull-down resistor, depending on polarity (operates as open drain). Use this setting if multiple devices need to share the INT pin. INT polarity. 0: the INT pin is active high. 1: the INT pin is active low. Write 0x0. FIFO length threshold. An interrupt is generated when the number of data-words in the FIFO exceeds the value in FIFO_THRESH. The interrupt pin automatically deasserts when the number of data-words available in the FIFO no longer exceeds the value in FIFO_THRESH. Write 0x00. Revision number. Device ID. Rev. B | Page 46 of 52 Data Sheet ADPD103 Data Bit [15:8] [7:1] 0 [15:12] [11:0] Default 0x0 0x64 0x0 0x0 0x000 Access W R/W R R R Name ADDRESS_WRITE_KEY SLAVE_ADDRESS Reserved Reserved CLK_RATIO 0x0D [15:0] 0x0 R/W SLAVE_ADDRESS_KEY 0x0F [15:1] 0 0x0000 0x0 R R/W Reserved SW_RESET 0x10 [15:2] [1:0] 0x000 0x0 R/W R/W Reserved Mode 0x11 [15:14] 13 0x0 0x0 R/W R/W Reserved RDOUT_MODE 12 0x1 R/W FIFO_OVRN_PREVENT [11:9] [8:6] 0x0 0x0 R/W R/W Reserved SLOTB_FIFO_MODE 5 0x0 R/W SLOTB_EN Address 0x09 0x0A Description Write 0xAD when writing to SLAVE_ADDRESS. Otherwise, do not access. I2C slave address. Do not access. Reserved. Read only. When the CLK32M_CAL_EN bit (Register 0x50, Bit 5) is set, the device calculates the number of 32 MHz clock cycles in two cycles of the 32 kHz clock. The result, nominally 2000 (0x07D0), is stored in the CLK_RATIO bits. Enable changing the I2C address using Register 0x09. 0x04AD: enable address change always. 0x44AD: enable address change if INT is high. 0x84AD: enable address change if PDSO is high. 0xC4AD: enable address change if both INT and PDSO are high. Reserved. Read only. Software reset. Write 0x1 to reset the device. This bit clears itself after a reset. This command does not return an acknowledge because the command is instantaneous. Write 0x000. Determines the operating mode of the ADPD103. 0x0: standby. 0x1: program. 0x2: normal operation. Write 0x0. Readback data mode for extended data registers 0x0: Block sum of N samples 0x1: Block average of N samples 0x0: wrap around FIFO, overwriting old data with new. 0x1: new data if FIFO is not full (recommended setting). Write 0x0. Time Slot B FIFO data format. 0: no data to FIFO. 1: 16-bit sample in digital integration mode or 16-bit sum of all 4 channels when not in digital integration mode. 2: 32-bit sample in digital integration mode or 32-bit sum of all 4 channels when not in digital integration mode. 3: 16-bit sample and 16-bit background value in digital integration mode 4: 32-bit sample and 32-bit background value in digital integration mode or 4 channels of 16-bit sample data for Time Slot B when not in digital integration mode. 6: 4 channels of 32-bit extended sample data for Time Slot B when not in digital integration mode. Others: reserved. The selected Time Slot B data is saved in the FIFO. Available only if Time Slot A has the same averaging factor, N (Register 0x15, Bits[10:8] = Bits[6:4]), or if Time Slot A is not saving data to the FIFO (Register 0x11, Bits[4:2] = 0). Time Slot B enable. 1: enables Time Slot B. Rev. B | Page 47 of 52 ADPD103 Data Sheet Data Bit [4:2] Default 0x0 Access R/W Name SLOTA_FIFO_MODE 1 0 15 14 0x0 0x0 0x0 0x0 R/W R/W R/W R/W Reserved SLOTA_EN Reserved EXT_SYNC_ENA [13:0] [15:9] 8 0x0 0x13 0x0 R/W R/W R/W Reserved Reserved CLK32K_BYP 7 0x0 R/W CLK32K_EN 6 [5:0] 0x0 0x12 R/W R/W Reserved CLK32K_ADJUST 0x4D [15:8] [7:0] 0x42 0x5E R/W R/W Reserved CLK32M_ADJUST 0x4E 1 [15:0] 0x0060 R/W ADC_TIMING1 Address 0x38 0x4B Description Time Slot A FIFO data format. 0: no data to FIFO. 1: 16-bit sample in digital integration mode or 16-bit sum of all 4 channels when not in digital integration mode. 2: 32-bit sample in digital integration mode or 32-bit sum of all 4 channels when not in digital integration mode. 3: 16-bit sample and 16-bit background value in digital integration mode 4: 32-bit sample and 32-bit background value in digital integration mode or 4 channels of 16-bit sample data for Time Slot B when not in digital integration mode. 6: 4 channels of 32-bit extended sample data for Time Slot B when not in digital integration mode. Others: reserved. Write 0x0. Time Slot A enable. 1: enables Time Slot A. Write 0x0. Enables external sampling trigger. 0x0: samples triggered internally. 0x1: samples triggered externally. Must be set to 1 if EXT_SYNC_SEL is b01 or b10. Write 0x0. Write 0x13. Bypass internal 32 kHz clock oscillator. 0x0: normal operation. 0x1: use an external clock on the PDSO pin. Sample clock power-up. Enables the data sample clock. 0x0: clock disabled. 0x1: normal operation. Write 0x0. Data sampling (32 kHz) clock frequency adjust. This register is used to calibrate the sample frequency of the device to achieve high precision on the data rate as defined in Register 0x12. Adjusts the sample master 32 kHz clock by 0.6 kHz per LSB. For a 100 Hz sample rate as defined in Register 0x12, 1 LSB of Register 0x4B, Bits[5:0], is 1.9 Hz. Note that a larger value produces a lower frequency. See the Clocks and Timing Calibration section for more information regarding clock adjustment. 00 0000: maximum frequency. 10 0010: typical center frequency. 11 1111: minimum frequency. Write 0x42. Internal timing (32 MHz) clock frequency adjust. This register is used to calibrate the internal clock of the device to achieve precisely timed LED pulses. Adjusts the 32 MHz clock by 109 kHz per LSB. See the Clocks and Timing Calibration section for more information regarding clock adjustment. 0000 0000: minimum frequency. 0101 1110: default frequency. 1111 1111: maximum frequency. 0x0040: ADC clock speed = 1 MHz. 0x0060: ADC clock speed = 500 kHz. Rev. B | Page 48 of 52 Data Sheet Address 0x4F 0x50 0x5F 1 ADPD103 Data Bit [15:7] 6 5 4 [3:2] Default 0x41 0x0 0x0 0x1 0x0 Access R/W R/W R/W R/W R/W Name Reserved PDSO_OE PDSO_IE Reserved EXT_SYNC_SEL 1 0 [15:7] 6 0x0 0x0 0x000 0x0 R/W R/W R/W R/W INT_IE Reserved Reserved PDSO_CTRL 5 0x0 R/W CLK32M_CAL_EN [4:0] [15:3] 2 0x0 0x0000 0x0 R/W R/W R/W Reserved Reserved SLOTB_DATA_HOLD 1 0x0 R/W SLOTA_DATA_HOLD 0 0x0 R/W FIFO_ACCESS_ENA Description Write 0x41. PDSO pin output enable. PDSO pin input enable. Write 0x1. Sample sync select. 00: use the internal 32 kHz clock with FSAMPLE to select sample timings. 01: use the INT pin to trigger sample cycle. 10: use the PDSO pin to trigger sample cycle. 11: reserved. INT pin input enable. Write 0x0. Write 0x000. Controls the PDSO output when the PDSO output is enabled (PDSO_OE = 0x1). 0x0: PDSO output driven low. 0x1: PDSO output driven by the AFE power-down signal. As part of the 32 MHz clock calibration routine, write 1 to begin the clock ratio calculation. Read the result of this calculation from the CLK_RATIO bits in Register 0x0A. Reset this bit to 0 prior to reinitiating the calculation. Write 0x0. Write 0x0000. Setting this bit prevents the update of the data registers corresponding to Time Slot B. Set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: hold data registers for Time Slot B. 0: allow data register update. Setting this bit prevents the update of the data registers corresponding to Time Slot A. Set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: hold data registers for Time Slot A. 0: allow data register update. Set to 1 twice to enable FIFO access. It is necessary to write 1 to the FIFO_ACCESS_ENA bit in two consecutive write operations in order to read data from the FIFO. During clock calibration, set to 1 to force the 32 MHz clock to run. For power savings, reset to 0 when the previously described operations are complete. Clock speed setting is only relevant during digital integrate mode. Rev. B | Page 49 of 52 ADPD103 Data Sheet ADC REGISTERS Table 25. ADC Registers Data Bits [15:0] Default 0x0028 Access R/W Name FSAMPLE [15:11] [10:8] 0x0 0x6 R/W R/W Reserved SLOTB_NUM_AVG 7 [6:4] 0x0 0x0 R/W R/W Reserved SLOTA_NUM_AVG 0x18 [3:0] [15:0] 0x0 0x2000 R/W R/W Reserved SLOTA_CH1_OFFSET 0x19 [15:0] 0x2000 R/W SLOTA_CH2_OFFSET 0x1A [15:0] 0x2000 R/W SLOTA_CH3_OFFSET 0x1B [15:0] 0x2000 R/W SLOTA_CH4_OFFSET 0x1E [15:0] 0x2000 R/W SLOTB_CH1_OFFSET 0x1F [15:0] 0x2000 R/W SLOTB_CH2_OFFSET 0x20 [15:0] 0x2000 R/W SLOTB_CH3_OFFSET 0x21 [15:0] 0x2000 R/W SLOTB_CH4_OFFSET Address 0x12 0x15 Description Sampling frequency: fSAMPLE = 32 kHz/(Register 0x12, Bits[15:0] × 4). For example, 100 Hz = 0x0050; 200 Hz = 0x0028. Write 0x0. Sample sum/average for Time Slot B. Specifies the averaging factor, NB, which is the number of consecutive samples that is summed and averaged after the ADC. Register 0x70 to Register 0x7F hold the data sum. Register 0x64 to Register 0x6B and the data buffer in Register 0x60 hold the data average, which can be used to increase SNR without clipping, in 16-bit registers. The data rate is decimated by the value of the SLOTB_NUMB_AVG bits. 0: 1. 1: 2. 2: 4. 3: 8. 4: 16. 5: 32. 6: 64. 7: 128. Write 0x0. Sample sum/average for Time Slot A. NA: same as Bits[10:8] but for Time Slot A. See description in Register 0x15, Bits[10:8]. Write 0x0. Time Slot A Channel 1 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 2 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 3 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 4 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 1 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 2 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 3 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 4 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Rev. B | Page 50 of 52 Data Sheet ADPD103 DATA REGISTERS Table 26. Data Registers Address 0x60 Data Bits [15:0] Access R Name FIFO_DATA 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] R R R R R R R R R R R R R R R R R R R R R R R R SLOTA_CH1_16BIT SLOTA_CH2_16BIT SLOTA_CH3_16BIT SLOTA_ CH4_16BIT SLOTB_ CH1_16BIT SLOTB_CH2_16BIT SLOTB_CH3_16BIT SLOTB_CH4_16BIT SLOTA_CH1_LOW SLOTA_CH2_LOW SLOTA_CH3_LOW SLOTA_CH4_LOW SLOTA_CH1_HIGH SLOTA_CH2_HIGH SLOTA_CH3_HIGH SLOTA_CH4_HIGH SLOTB_CH1_LOW SLOTB_CH2_LOW SLOTB_CH3_LOW SLOTB_CH4_LOW SLOTB_CH1_HIGH SLOTB_CH2_HIGH SLOTB_CH3_HIGH SLOTB_CH4_HIGH Description Next available word in FIFO. Prior to reading this register, set the FIFO_ACCESS_ENA bit to 0x1 twice with two consecutive write operations to enable FIFO access (Register 0x5F, Bit 0). Reset this bit to 0 when the FIFO access sequence is complete. 16-bit value of Channel1 in Time Slot A. 16-bit value of Channel 2 in Time Slot A. 16-bit value of Channel 3 in Time Slot A. 16-bit value of Channel 4 in Time Slot A. 16-bit value of Channel 1 in Time Slot B. 16-bit value of Channel 2 in Time Slot B. 16-bit value of Channel 3 in Time Slot B. 16-bit value of Channel 4 in Time Slot B. Low data-word for Channel 1 in Time Slot A. Low data-word for Channel 2 in Time Slot A. Low data-word for Channel 3 in Time Slot A. Low data-word for Channel 4 in Time Slot A. High data-word for Channel 1 in Time Slot A. High data-word for Channel 2 in Time Slot A. High data-word for Channel 3 in Time Slot A. High data-word for Channel 4 in Time Slot A. Low data-word for Channel 1 in Time Slot B. Low data-word for Channel 2 in Time Slot B. Low data-word for Channel 3 in Time Slot B. Low data-word for Channel 4 in Time Slot B. High data-word for Channel 1 in Time Slot B. High data-word for Channel 2 in Time Slot B. High data-word for Channel 3 in Time Slot B. High data-word for Channel 4 in Time Slot B. Table 27. Required Start-Up Load Sequence Step Number 1 2 3 4 Address 0x4B, Bit 7 0x10 Other registers 0x10 Comment Write to 0x1 to enable the clock that drives the state machine. Write 0x0001 to enter program mode. Register order is not important while the device is in program mode. Write 0x0002 to start normal sampling operation. Rev. B | Page 51 of 52 ADPD103 Data Sheet OUTLINE DIMENSIONS 0.25 0.20 0.15 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 22 0.40 BSC PIN 1 INDICATOR 28 1 21 2.70 2.60 SQ 2.50 EXPOSED PAD 7 15 0.80 0.75 0.70 14 8 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PKG-003523 SEATING PLANE 0.20 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 06-23-2015-B 0.45 0.40 0.35 TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-220-WGGE. Figure 31. 28-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-28-5) Dimensions shown in millimeters 1.44 1.40 1.36 0.225 3 2 1 A BALL A1 IDENTIFIER B 2.00 REF 2.50 2.46 2.42 C D 0.40 BSC E F TOP VIEW 0.235 0.300 (BALL SIDE DOWN) 0.560 0.500 0.440 0.300 0.260 0.220 1 0.230 0.200 0.170 02-03-2015-B COPLANARITY 0.05 PKG-004659 Model 1 ADPD103BCPZ ADPD103BCPZRL ADPD103BCBZRL7 EVAL-ADPD103Z-GEN (BALL SIDE UP) 0.330 0.300 0.270 END VIEW SEATING PLANE ORDERING GUIDE BOTTOM VIEW Figure 32. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-18) Dimensions shown in millimeters Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 28-Lead LFCSP_WQ 28-Lead LFCSP_WQ 16-Ball WLCSP Generic ADPD103 Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12722-0-2/16(B) Rev. B | Page 52 of 52 Package Option CP-28-5 CP-28-5 CB-16-18