AD6676BCBZRL

Wideband IF Receiver Subsystem AD6676 Data Sheet FEATURES APPLICATIONS High instantaneous dynamic range Noise figure (NF) as low as 13 dB Noise spectral density (NSD) as low as −159 dBFS/Hz IIP3 up to 36.9 dBm with spurious tones 85 dB Rejection) 0.814 0.814 0.571 0.571 BW (>60 dB Rejection) 0.834 0.834 0.617 0.617 Total Pipeline Latency The digital filter path dominates the latency of the AD6676 whereas the JESD204B PHY adds a few samples of delay and the ADC delay is a fraction of an output sample. The latency between the ADC and digital filter output is fixed with the only nondeterministic delay being associated with the JESD204B PHY clock and lane FIFOs before synchronization. See the Synchronization Using SYSREF section for additional information. Table 15 provides the nominal pipeline delay associated with each DEC_MODE. Note that although all DEC_MODE settings provide similar delays relative to the output data rate, fDATA_IQ, applications that require shorter absolute time delays may consider using a lower decimation factor to reduce the absolute delay by 2×. Table 15. Nominal Pipeline Latency vs. DEC_MODE (Sample Delay Relative to 1/fDATA_IQ) DEC_MODE 1 2 3 4 All filter responses provide a linear phase response over its pass band. The usable IF bandwidth depends on the DEC_MODE as well as the minimum acceptable pass band ripple and stop band rejection requirements. Table 14 provides the normalized usable complex bandwidth vs. DEC_MODE for stop band rejections of greater than 85 dB and 60 dB. The last filter stage sets the usable bandwidth and stop band rejection because it has the most aggressive transition band specifications. For this reason, the decimation factors of 12 and 16 have the same normalized usable bandwidths as does decimation factors of 24 and 32. Rev. D | Page 40 of 90 Decimation Factor 32 24 16 12 JESD204B Lanes 1 1 2 2 IQ Data Output Sample Delay 34.2 34.2 32.3 32.3 Data Sheet AD6676 0.5 0 0.4 –20 0.3 MAGNITUDE (dB) MAGNITUDE (dB) 0.2 0.1 0 –0.1 –0.2 –0.3 –40 –60 –80 MINIMUM ALIAS ATTENUATION 85.5dB –100 –120 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY NORMALIZED TO fDATA_IQ 12348-056 –0.5 Figure 105. Pass Band Frequency Response of Decimate by 12 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY NORMALIZED TO fDATA_IQ 12348-059 –0.4 Figure 108. Folded Frequency Response of Decimate by 12 Shows Alias Rejection 0.5 0 0.4 –20 0.3 MAGNITUDE (dB) MAGNITUDE (dB) 0.2 0.1 0 –0.1 –0.2 –0.3 –40 –60 –80 MINIMUM ALIAS ATTENUATION 85.5dB –100 –120 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY NORMALIZED TO fDATA_IQ 12348-057 –0.5 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY NORMALIZED TO fDATA_IQ 12348-060 –0.4 Figure 109. Folded Frequency Response of Decimate by 16 Shows Alias Rejection Figure 106. Pass Band Frequency Response of Decimate by 16 0.5 0 0.4 –20 0.3 MAGNITUDE (dB) 0.1 0 –0.1 –0.2 –0.3 –40 –60 –80 MINIMUM ALIAS ATTENUATION 85.5dB –100 –0.5 –120 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY NORMALIZED TO fDATA_IQ Figure 107. Pass Band Frequency Response of Decimate by 24 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 FREQUENCY NORMALIZED TO fDATA_IQ 0.45 0.50 12348-061 –0.4 12348-058 MAGNITUDE (dB) 0.2 Figure 110. Folded Frequency Response of Decimate by 24 Shows Alias Rejection Rev. D | Page 41 of 90 AD6676 Data Sheet 0.5 Peak Detection and AGC Flags 0.4 Peak detection occurs at the output of the second stage decimation filter, as shown in Figure 103. Detection at this stage represents a compromise between the accuracy of the peak detector, delay time and ability to measure large out-of-band signals. At this stage, the Σ-Δ ADC output signal has been frequency translated to dc and its out-of-band noise sufficiently filtered for reasonable threshold detection accuracy down to −12 dBFS peak signal levels. Note that the peak detector monitors the peak power envelope response of the IF input signal and calculates the peak power (that is, I2 + Q2) expressed in dBFS with 12-bit resolution. 0.3 MAGNITUDE (dB) 0.2 0.1 0 –0.1 –0.2 –0.3 –0.5 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY NORMALIZED TO fDATA_IQ 12348-062 –0.4 Figure 111. Pass Band Frequency Response of Decimate by 32 0 MAGNITUDE (dB) –20 –40 –60 –80 MINIMUM ALIAS ATTENUATION 88dB –100 Because the peak detector is monitoring the peak power at the output of the second stage decimation filter, it provides a wider frequency range than what can be observed in the final IQ data output. The first stage filter is decimate by 3 or by 4; therefore, the output of the second stage filter can be 1/6th or 1/8th of FADC. Figure 113 shows the normalized measurement bandwidth relative to the output rate of the second stage filter centered about its zero IF. Table 16 references the measurement bandwidth to fDATA_IQ for the different decimation factors such that its absolute bandwidth can be easily determined. For example, the −1 dB bandwidth for an fDATA_IQ of 100 MSPS with decimate by 24 or by 32 is 200 MHz and remains at 200 MHz if the decimation factor is reduced to decimate by 12 or by 16. Any droop occurring at the pass band edges, as well as the Σ-Δ ADC STF, must be considered when setting thresholds. 0.10 0.15 0.20 0.25 0.30 0.35 0.40 FREQUENCY NORMALIZED TO fDATA_IQ 0.45 0.50 Figure 112. Folded Frequency Response of Decimate by 32 Shows Alias Rejection AGC FEATURES AND PEAK DETECTION In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be overdriven. The AD6676 Σ-Δ ADC is based on a feedback loop that can be overdriven into a nonlinear region, resulting in oscillation. This oscillation persists until the Σ-Δ ADC is reset and the overload condition is removed. Typically, a receiver lineup employs some form of AGC that attempts to avoid this scenario. The AD6676 pipeline latency along with any additional overhead associated with the host processor (JESD204B Rx PHY) may limit the ability to design a fast reacting digital-based AGC required by some applications. For this reason, the AD6676 includes the AGCx pins that serve as digital input/ outputs to facilitate the implementation of a fast AGC control loop under the control of the host. The AGC4 and AGC3 pins can be allocated to provide flag outputs after a programmable threshold has been exceeded, including an ADC reset event, while the AGC2 and AGC1 pins can be used to control the onchip attenuator. Register 0x18F and Register 0x193 through Register 0x19E are used for AGC purposes. 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –0.35 –0.25 –0.15 –0.05 0.05 0.15 0.25 0.35 FREQUENCY OFFSET FROM IF CENTER (NORMALIZED TO FIQ@2ND STAGE FILTER) 12348-064 0.05 MAGNITUDE (dBFS) 0 12348-063 0.5 –120 Figure 113. Normalized Pass Band Filter Response Seen by the Peak Detector Table 16. Normalized Measurement Bandwidth of Peak Detector Relative to Output Data Rate, fDATA_IQ DEC_ MODE 1 2 3 4 Rev. D | Page 42 of 90 Decimation Factor 32 24 16 12 Normalized Measurement Bandwidth Relative to fDATA_IQ −0.5 −1.0 −2.0 −3.0 dBFS dBFS dBFS dBFS 1.76 2.00 2.40 2.64 1.76 2.00 2.40 2.64 0.88 1.00 1.20 1.32 0.88 1.00 1.20 1.32 Data Sheet AD6676 The AD6676 allows the user to set three threshold settings that can trigger one of two possible flags. PKTHRH0 and PKTHRH1 are two upper threshold settings while LOWTHRH is a lower threshold setting. The threshold settings are 12 bits with an MSB and LSB register assigned to each threshold. The 12-bit decimal equivalent value can be calculated using Equation 12. Threshold = 3584 + (Threshold Setting in dBFS) × 256/3 (12) where 0 dBFS corresponds to 3584 (0xE00) and −6 dBFS corresponds to 3072 (0xC00). In the time domain, a 0 dBFS setting corresponds to a signal whose peaks observed at the I and Q outputs can reach plus or minus full scale. Meaning, if the 16-bit I and Q output data are normalized such that its peak values correspond to ±1, a 0 dBFS setting corresponds to a signal whose peak can reach the unit circle of a normalized I/Q constellation diagram. The LOWTHRH_x register has an associated dwell time of which the signal must remain below this threshold before a flag can be set. The dwell time is represented in exponential form to realize long dwell periods because the counter operates at FADC/12 for decimate by 12 or 24 settings or FADC/16 for decimate by 16 or 32 settings. The dwell time is set in the DWELL_TIME_ MANTISSA register and DWELL_TIME_EXP register using Equation 13 relative to 1/FADC. Dwell Time = N × [DWELL_TIME_MANTISSA] × 2(DWELL_TIME_EXP) (13) where: N = 12 for decimate by 12 or 24. N = 16 for decimate by 16 or 32. Note that the EN_FLAGx bits provide the additional option of logically OR’ing an ADC reset event with an upper peak threshold event to provide an even faster output flag to the host processor indicating that the attenuation must be applied. This scenario applies to the extreme case where the envelope response of a blocker is exceedingly fast, such that the AGC cannot react fast enough to the upper peak threshold setting flag to prevent overloading the Σ-Δ ADC. Figure 114 provides an example of how the Flag 0 and Flag 1 assigned pins behave to the envelope response of an arbitrary IF input signal. Flag 1 is assigned an upper threshold set by PKTHRH1_x, and Flag 0 is assigned a lower threshold and dwell time set by LOWTHRH_x and DWELL_TIME_x. The Flag 1 indicator goes high when the PKTTHR1_x threshold is exceeded and returns low when the signal envelope falls below this threshold. The Flag 0 indicator goes high only when the envelope of the signal remains below the LOWTHRH_x threshold for the designated dwell time. If the signal level exceeds the LOWTHRH_x threshold before the dwell time counter has expired, the dwell time counter resets again and the Flag 0 indicator remains low until the conditions has been met. By offsetting the PKTTHR1_x and LOWTHRH_x threshold settings as well as optimizing the dwell time setting, it may be possible to optimize the operation of an AGC so that it reacts to signal strength variation due to fading conditions as opposed to the peak to minimum response associated with digital modulated signals. IF Attenuator Control via the AGC2 and AGC1 Pins A flag function can be assigned using the FLAG0_SEL register and FLAG1_SEL register to indicate when any of the thresholds have been exceeded or if an ADC reset event has occurred. These flags must also be enabled via the EN_FLAG register such that a CMOS level signal appears on the AGC4 and AGC3 pins where a logic high indicates when a threshold has been exceeded. The delay relative to the ADC input when an AGC threshold is exceeded to when the flag signal goes high is dependent on the DEC_MODE setting selected. For a DEC_MODE value of 1 or 2 (decimate by 32 or 24), the delay equates to 8 to 9 output samples (1/fDATA_IQ). For DEC_MODE values of 3 or 4 (decimate by 16 or 12), the delay is 16 to 18 samples. The delay associated with an ADC reset event is much shorter because it avoids the digital filter path. This delay is 1 sample for DEC_MODE values of 1 or 2 and 2 samples for DEC_MODE values of 3 and 4. Many AGC implementations require fast gain control if the AGC threshold is exceeded. The AD6676 provides two modes in which the IF attenuator can be quickly changed via the AGCx pins. Use Register 0x180, Bit 0, to select the mode. The first mode uses the AGC2 pin to switch between two attenuator settings that are user defined in Register 0x181 and Register 0x182. The second mode uses the AGC2 and AGC1 pins to decrement and increment respectively the attenuation value in 1 dB steps with pulsed inputs. The starting attenuator value is defined in Register 0x183. The actual attenuator value can be read back via Register 0x184. The first mode is used for the default AD6676 power-up setting with both Register 0x181 and Register 0x182 set to 0x0C. For applications that do not require IF attenuator control but require a different attenuator setting, update both registers with the desired attenuator setting value such that the attenuator remains independent of the AGC2 pin state, if it is left floating. Note that connecting the unused AGC2 and AGC1 pins to VSSD via 100 kΩ pull-down resistors is still the preferred method if these pins are unused. Rev. D | Page 43 of 90 AD6676 Data Sheet UPPER THRESHOLD (PKTTHR1) DWELL TIME TIMER RESET BY RISE ABOVE LOWER THRESHOLD MIDSCALE LOWER THRESHOLD (LOWTHRH) DWELL TIME TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LOWER THRESHOLD 12348-065 FLAG1 FLAG0 Figure 114. Example of Flag Behavior as Signal Envelope Crosses Upper and Lower Threshold Settings Table 17. Power Saving for 3.0 GSPS Operation with CLKSYN Enabled and 125 MSPS IQ Rate (Single JESD204B Lane) Power State at 3 GSPS STDBY_SLOW STDBY_FAST Power Down Power Up IVDD2 (mA) 18 95 2.6 146 IVDD1+, IVDDC+ IVDDL (mA) 162 175 25 433 GPIO FUNCTIONALITY The AGCx pins can also be configured for basic GPIO functionality via Register 0x1B0 to Register 0x1B4. Register 0x1B0 determines which pins are used for GPIO functionality, whereas Register 0x1B1 determines if an AGC pin serves as input or output. If the pin serves as an output, Register 0x1B2 determines the high or low state, and Register 0x1B3 reads back the state of these designated output pins. Lastly, if an AGCx pin serves as an input, Register 0x1B4 reads back the state of this pin. POWER SAVING MODES The AD6676 features two SPI configurable and selectable power savings modes. The first mode is a sleep mode where the AD6676 is placed in a low power state for extended periods, and the second mode is a standby mode where the AD6676 enters a reduced power state but still keeps the JESD204B link and digital clocks active to ensure multichip synchronization (or fixed latency) during fast power cycling. Both sleep mode and standby mode can be entered via a SPI write operation to the PD_MODE bits in the DEVICE_CONFIG register (Register 0x002; Bits[1:0]). Note that, depending on whether sleep or standby mode is selected, various functional blocks within the Σ-Δ ADC itself are either powered down, placed in a low bias state, or remain powered. The standby mode is also controllable via a user designated AGCx pin for faster and more precise power cycling. This feature is particularly useful for TDD-based communication protocols, allowing the host processor to quickly power cycle the AD6676 during transmit bursts. The PD_PIN_CTRL register (Register 0x152) enables this feature as well as designates the AGC pin. IVDDD (mA) 216 221 29 310 PTOTAL (mW) 461 673 64 1182 Percent (%) Power Savings 61 43 Not applicable Not applicable The standby register (Register 0x150) powers down different functional blocks during standby mode. However, all functional blocks that affect the clock generation, distribution and the JESD204B link remain enabled to maintain constant latency while in standby. The only exception is STBY_VSS2GEN (Register 0x150, Bit 6) where a trade-off exists in power savings vs. wake-up time, depending on whether the negative voltage generator is placed in standby. Table 17 shows the realized power savings for the different power savings modes at 3.0 GSPS operation with the AD6676 configured for 125 MSPS IQ output and the internal clock synthesizer enabled. Note that STDBY_FAST and STDBY_SLOW correspond to whether the STBY_VSS2GEN bit is enabled or disabled during standby. Note that an additional 18% power savings can be achieved when powering down the STBY_VSS2GEN bit. Although the AD6676 can enter into standby quickly, it does require a few microseconds to exit standby. Figure 115 shows that the AD6676 can achieve a low power state within 100 ns. Figure 116 and Figure 117 show the wake-up time between the STDBY_FAST and STDBY_SLOW cases to achieve 1% envelope settling accuracy being around 2.5 μs and 11.5 μs, respectively. The phase response is not shown because it settles faster than the envelope response. Note that the digital data path is enabled for these time domain figures such that the setting time responses can be observed. Rev. D | Page 44 of 90 Data Sheet AD6676 1.0 INTRODUCTION TO THE JESD204B INTERFACE NORMALIZED ENVELOPE OUTPUT 0.9 The JESD204B interface reduces the PCB area for data interface routing yet enabling the use of smaller packages for converter and logic devices. The AD6676 digital output complies with the JEDEC Standard No. JESD204B, Serial Interface for Data Converters. JESD204B is a protocol to link the AD6676 to a digital processing device over a serial interface. The AD6676 supports link rates of up 5.333 Gbps while operating with two output lanes in support of a maximum I/Q data rate (fDATA_IQ) of 266.67 MSPS. Note that a two output lane configuration is always required for decimation factors of 12 and 16. 0.8 0.7 AD6676 ENTERS STANDBY WITHIN 100ns 0.6 0.5 0.4 0.3 0.2 0 10.0 10.0 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11.0 TIME (µs) 12348-066 0.1 Figure 115. Fast Power-Down Response When the AD6676 Is Placed in Standby 1.0 1% SETTLING TIME = 2.5µs NORMALIZED ENVELOPE OUTPUT 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 TIME (µs) 12348-067 0.1 Figure 116. Settling Time for STDBY_FAST with the STBY_VSS2GEN Enabled for Fastest Recovery, Approximately 2.5 μs to 1 % JESD204B data transmit block assembles the parallel data from the ADC into frames and uses 8-bit/10-bit encoding as well as optional scrambling to form serial output data. Lane synchronization is supported through the use of special characters during the initial establishment of the link and additional synchronization is embedded in the data stream thereafter. A JESD204B receiver is required to complete the serial link. For additional details on the JESD204B interface, refer to the JESD204B standard. Because the AD6676 provides 16-bit complex IQ data, its JESD204B transmit block effectively maps the output of two virtual ADCs (M = 2) over a link. The link is configurable for either single or dual lanes with each lane providing a serial data stream via a differential output. The JESD204B specification refers to a number of parameters to define the link and these parameters must match between the AD6676 JESD204B transmitter and receiver. The following parameters describe a JESD204B link:  1.0 0.9 NORMALIZED ENVELOPE OUTPUT JESD204B Overview 1% SETTLING TIME = 11.5µs  0.8 0.7  0.6 0.5    0.4 0.3 0.2  0 0 2 4 6 8 10 TIME (µs) 12 14 16 18 20 12348-068 0.1 Figure 117. Settling Time for STDBY_SLOW with STBY_VSS2GEN in Standby for Additional Power Savings, Approximately 11.5 μs to 1 %      Rev. D | Page 45 of 90 S = samples transmitted per single converter per frame cycle (AD6676 value = 1) M = number of converters per converter device (AD6676 value = 2) L = number of lanes per converter device (AD6676 value can be 1 or 2) N = converter resolution (AD6676 value = 16) N’ = total number of bits per sample (AD6676 value = 16) CF = number of control words per frame clock cycle per converter device (AD6676 value = 0) CS = number of control bits per conversion sample (AD6676 value = 0) K = number of frames per multiframe (configurable on the AD6676 up to 32) HD = high density mode (AD6676 value = 0) F = octets per frame (AD6676 value = 2 or 4, dependent on L = 2 or 1) T = tail bit (AD6676 value = 0) SCR = scrambler enable or disable (configurable on the AD6676) AD6676 Data Sheet The scrambler uses a self synchronizing polynomial-based algorithm defined by the equation 1 + x14 + x15. The descrambler in the receiver must be a self synchronizing version of the scrambler polynomial. Figure 118 shows a simplified block diagram of the AD6676 JESD204B link mapping the 16-bit I and Q outputs onto the two separate lanes. Other configurations are also possible, such as combining the I and Q outputs onto a single lane (fDATA_IQ ≤ 153.6 MSPS) or changing the mapping of the I and Q output paths. In any case, the 16-bit I and Q data are each broken into two octets (eight bits of data). Bit 15 (MSB) through Bit 8 are in the first octet. The second octet contains Bit 7 through Bit 0 (LSB). The four resulting octets (2 I octets and 2 Q octets) may be scrambled. Scrambling is optional but is available to avoid spectral peaks when transmitting similar digital data patterns. The four octets are then encoded with an 8-bit/10-bit encoder. The 8-bit/10-bit encoder takes eight bits of data (an octet) and encodes them into a 10-bit symbol. Figure 119 shows how the 16-bit I or Q data is taken from the final decimation stage, formed into octets, the two octets are scrambled, and how the octets are encoded into two 10-bit symbols. I CONVERTER 0 JESD204B LINK CONTROL (L.M.F.M.S) (SPI REG 0x1C3 TO 0x1C9) FRAMER SWAP (SPI REG 0x1E1) ADC SERDOUT0–, SERDOUT0+ LANE SWAP (SPI REG 0x1E1) SERDOUT1–, SERDOUT1+ 12348-069 Q CONVERTER 1 SYSREF± SYNCINB± Figure 118. Transmit Link Simplified Block Diagram ADC TEST PATTERNS (REG 0x1E5) JESD204B SAMPLE CONSTRUCTION ADC 16-BIT JESD204B TEST PATTERNS (REG 0x1E5, REG 0x1F8 TO REG 0x1FF) FRAME CONSTRUCTION SCRAMBLER 1 + x14 + x15 (OPTIONAL VIA 0x1C3) JESD204B TEST PATTERNS (REG 0x1E5, REG 0x1F8 TO REG 0x1FF) SERIALIZER 8-BIT/10-BIT ENCODER (0x1E4) a b a b c d e f g h i j SERDOUT0± SERDOUT1± i j a b SYMBOL0 i j SYMBOL1 a b c d e f g h i j 12348-070 JESD204B TEST PATTERNS (0x1E5) Figure 119. Digital Formatting of JESD204B Lanes PROCESSED SAMPLES FROM ADC SAMPLE CONSTRUCTION FRAME CONSTRUCTION DATA LINK LAYER SCRAMBLER ALIGNMENT CHARACTER GENERATION 8-BIT/10-BIT ENCODER PHYSICAL LAYER CROSSBAR MUX SERIALIZER Tx OUTPUT 12348-071 TRANSPORT LAYER SYSREF± SYNCINB± Figure 120. Data Flow Rev. D | Page 46 of 90 Data Sheet AD6676 FUNCTIONAL OVERVIEW The flowchart in Figure 120 shows the flow of data through the JESD204B hardware from the sample input to the physical output. The processing is divided into layers that are derived from the OSI model widely used to describe the abstraction layers of communications systems. These are the transport layer, the data link layer, and the physical layer (serializer and output driver). Transport Layer The transport layer packs the data into JESD204B frames, which are mapped to 8-bit octets that are sent to the data link layer. The transport layer mapping is controlled by rules derived from the link parameters. The AD6676 uses no tail bits in the transport layer because the output of its IQ digital data path is considered two virtual 16-bit converters. Data Link Layer The data link layer is responsible for the low level functions of passing data across the link. These include optional data scrambling, inserting control characters for lane alignment/ monitoring, and encoding 8-bit octets into 10-bit symbols. The data link layer also sends the initial lane alignment sequence (ILAS), which contains the link configuration data, and is used by the receiver to verify the settings in the transport layer. The SYNCINB± pin operation options are controllable via SPI registers. Although the SYNCINB input is configured for a CMOS logic level on its positive pin by default, it can also be configured for a differential LVDS input signal on its positive/ negative pins via Register 0x1E7. The polarity of the SYNCINB input signal can also be inverted via Register 0x1E4. Initial Lane Alignment Sequence (ILAS) The ILAS phase follows the CGS phase and begins on the next LMFC boundary. The ILAS consists of four multiframes, with a /R/ character marking the beginning and an /A/ character marking the end. The ILAS begins by sending an /R/ character followed by a data ramp starting with the value, 0, over four multiframes. On the second multiframe, the link configuration data is sent, starting with the third character. The second character in the second multiframe is a /Q/ character to confirm that the link configuration data follows. All undefined data slots are filled with ramp data. The ILAS sequence is never scrambled. The ILAS sequence construction is shown in Figure 121. The four multiframes include the following:   Physical Layer The physical layer consists of the high speed circuitry clocked at the serial clock rate. For the AD6676, the 16-bit I and Q data are converted into one or two lanes of high speed differential serial data. JESD204B LINK ESTABLISHMENT The AD6676 JESD204B Tx interface operates in Subclass 0 or Subclass 1 as defined in the JEDEC Standard No. 204B (July 2011) specification. The link establishment process is divided into the following steps: code group synchronization, ILAS, and user data. Code Group Synchronization (CGS) and SYNCINB Code group synchronization (CGS) is the process where the JESD204B receiver finds the boundaries between the 10-bit symbols in the stream of data. During the CGS phase, the JESD204B transmit (JESD Tx) block transmits /K28.5/ characters. The receiver must locate /K28.5/ characters in its input data stream using clock and data recovery (CDR) techniques.   Multiframe 1: Begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 2: Begins with an /R/ character followed by a /Q/ (/K28.4/) character, followed by link configuration parameters over 14 configuration octets (see Table 18), and ends with an /A/ character. Many of the parameter values are of the notation of n − 1. Multiframe 3: Begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 4: Begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). User Data and Error Detection After the ILAS is complete, the user data is sent. Normally, in a frame all characters are user data. However, to monitor the frame clock and multiframe clock synchronization, there is a mechanism for replacing characters with /F/ or /A/ alignment characters when the data meets certain conditions. These conditions are different for unscrambled and scrambled data. The scrambling operation is disabled by default, but may be enabled via Register 0x1C3. The receiver issues a synchronization request by asserting a low signal on the SYNCINB± pins of the AD6676. The JESD Tx begins to send /K/ characters. After the receiver has synchronized, it then deasserts its SYNCINB signal, causing it to go high. The AD6676 then transmits an ILAS on the following LMFC boundary. For more information on the CGS phase, see the JEDEC Standard No. 204B (July 2011), Section 5.3.3.1. Rev. D | Page 47 of 90 AD6676 Data Sheet For scrambled data, any 0xFC character at the end of a frame is replaced by an /F/ and any 0x7C character at the end of a multiframe is replaced with an /A/. The JESD204B receiver checks for /F/ and /A/ characters in the received data stream and verifies that they only occur in the expected locations. If an unexpected /F/ or /A/ character is found, the receiver uses dynamic realignment or asserts the SYNCINB± signal for more than four frames to initiate a resynchronization. For unscrambled data, if the final character of two subsequent frames is equal, the second character is replaced with an /F/ if it is at the end of a frame, and an /A/ if it is at the end of a multiframe. K K R D D A R Q C C D Insertion of alignment characters may be modified using SPI. The frame alignment character insertion is enabled by default. More information on the link controls is available in the SPI register descriptions for Register 0x1E0 to Register 0x1E6. 8-Bit/10-Bit Encoder The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols and inserts control characters into the stream when needed. The control characters used in JESD204B are shown in Table 18. The 8-bit/10-bit encoding ensures that the signal is dc balanced by using the same number of ones and zeroes across multiple symbols. Note that the 8-bit/10-bit interface has an invert option available in Register 0x1E4 that has the same effect of swapping the differential output data pins. D A R D D A R D D A D START OF ILAS START OF LINK CONFIGURATION DATA START OF USER DATA 12348-072 END OF MULTIFRAME Figure 121. Initial Lane Alignment Sequence Table 18. Control Characters used in JESD204B Including Running Disparity Values Abbreviation /R/ /A/ /Q/ /K/ /F/ Control Symbol K28.0 K28.3 K28.4 K28.5 K28.7 8-Bit Value 000 11100 011 11100 100 11100 101 11100 111 11100 10-Bit Value (RD = −1) 001111 0100 001111 0011 001111 0010 001111 1010 001111 1000 Rev. D | Page 48 of 90 10-Bit Value (RD = +1) 110000 1011 110000 1100 110000 1101 110000 0101 110000 0111 Description Start of multiframe Lane alignment Start of link configuration data Group synchronization Frame alignment Data Sheet AD6676 Digital Outputs, Timing and Controls The AD6676 physical layer consists of digital drivers that are defined in the JEDEC Standard No. 204B (July 2011). These CML drivers are powered up by default via Register 0x1E2. The drivers utilize a dynamic 100 Ω internal termination to reduce unwanted reflections. A 100 Ω differential termination resistor at each receiver input results in a nominal 300 mV p-p swing at the receiver. The AD6676 JESD204B differential outputs can interface with custom ASICs and FPGA receivers, providing superior switching performance in noisy environments. Single point-to-point network topologies are recommended with receiver inputs having a nominal differential 100 Ω termination. The common mode of the digital output automatically biases itself to half the VDDHSI supply of 1.1 V (VCM = 0.55 V), thus making ac coupling the preferred coupling method to the receiver logic as shown Figure 122. DC coupling can be considered if the receiver device shares the same VDDHSI supply and input common-mode range. SERDOUTx– –100 –300 EYE: ALL BITS, OFFSET: –0.0055 UIs: 4000; 1059998, TOTAL: 4000; 1059998 –400 –150 –100 –50 0 50 100 150 TIME (ps) Figure 123. Digital Outputs Data Eye with External 100 Ω Terminations at 5.333 Gbps in Accordance to LV-OIF-11G-SR Mask 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 –5 –4 –3 –2 –1 0 1 2 3 4 5 TIME (ps) Figure 124. Digital Outputs Histogram with External 100 Ω Terminations at 5.333 Gbps 1 1–2 1–4 RECEIVER 1–6 0.1µF OUTPUT SWING = 300mV 0 VCM = VDDHSI/2 1–8 1–10 Figure 122. AC-Coupled Digital Output Termination Example 1–12 Timing errors caused by a degraded eye diagram at the receiver input can often be attributed to poor far end termination or differential trace routing. These potential error sources can be reduced by using well controlled differential 100 Ω traces with lengths below six inches that connect to receivers with integrated differential 100 Ω resistors. 1–14 1–16 –0.5 –0.4 –0.3 –0.2 –0.1 0 UIs 0.1 0.2 0.3 0.4 0.5 12348-505 100Ω 100 –200 BER SERDOUTx+ 200 100Ω DIFFERENTIAL TRACE PAIR 0.1µF 12348-073 VDDHSI 300 12348-503 The optional SYSREF± input can be used for multichip synchronization or establishing a repeatable latency between the AD6676 and its host. The SYSREF± receiver circuit must be disabled if not used (Register 0x1E7 = 0x04) to prevent potential false triggering if the input pins are left open. The SYSREF± input does not include an internal 100 Ω termination resistor; thus, an external differential termination resistor must be included if this input is used. The SYSREF± input is logic complaint to LVPECL, LVDS, and CMOS. 400 12348-504 The AD6676 physical layer consists of consists of two digital differential inputs, SYSREF± and SYNCINB±, whose equivalent input circuits are shown in Figure 61 and Figure 64. These inputs must be dc-coupled to their respective drivers because they are or can be aperiodic. The SYNCINB± input is logic compliant to both CMOS and LVDS via Register 0x1E7, Bit 2, with CMOS being the default. Note that the SYNCINB± input includes an internal 100 Ω termination resistor when LVDS is selected. VOLTAGE (mV) Digital Inputs Figure 123, Figure 124, and Figure 125 show examples of the digital output data eye, time interval error (TIE) jitter histogram, and bathtub curve for one AD6676 lane running at 5.333 Gbps with Register 0x1EC set to 0xBD. The format of the output data is twos complement by default. The output data format can be changed via Register 0x146. HITS PHYSICAL LAYER INPUT/OUTPUTS Figure 125. Digital Outputs Data Bathtub with External 100 Ω Terminations at 5.333 Gbps Rev. D | Page 49 of 90 AD6676 Data Sheet Preemphasis CONFIGURING THE JESD204B LINK Preemphasis enables the receiver eye diagram mask to be met in conditions where the interconnect insertion loss does not meet the JESD204B specification. The preemphasis feature is controlled via Register 0x1EF and must be used only when the receiver cannot recover the clock due to excessive insertion loss. Under normal conditions, it is disabled to conserve power. Additionally, enabling and setting too high a deemphasis value on a short link may cause the receiver eye diagram to fail or lead to potential EMI issues. For these reasons, consider the use of preemphasis only in instances where meeting the receiver eye diagram mask is a challenge. See the Register Memory Map section for details. The AD6676 has one JESD204B link. The serial outputs (SERDOUT0± and SERDOUT1±) are part of one JESD204B link. The basic parameters that determine the link setup are: Serializer PLL This PLL generates the serializer clock that is equal to the JESD204B lane rate. The on-chip controller automatically configures the PLL parameters based on the user specified IQ data rate (FADC/M) and number of lanes. The status of the PLL lock can be checked via the PLL_LCK status bit in Register 0x2DC. This read only bit lets the user know if the PLL has achieved a lock for the specific setup.    L is the number of lanes per link M is the number of converters per link F is the number of octets per frame The maximum and minimum specified lane rates for the AD6676 are 5.333 Gbps and 3.072 Gbps, respectively. For this reason, the AD6676 supports a single lane interface for IQ data rates (fDATA_IQ) from 76.8 MSPS to 133.3 MSPS and a two lane interface from 153.6 MSPS to 266.7 MSPS. The lane line rate is related to the JESD204B parameters using the following equation: Lane Line Rate  40  F DATA_IQ  (14) L where: FDATA_IQ  FADC DEC The decimation ratio (DEC) is the parameter programmed into Register 0x140. Table 19 shows the JESD204B output configurations supported based on fDATA_IQ. Table 19. JESD204B Output Configurations No. Virtual Converters Supported (same as M) 2 fDATA_IQ (MSPS) 76.8 to 133.3 153.6 to 266.7 JESD Serial Line Rate 40 × fDATA_IQ 20 × fDATA_IQ L 1 2 Rev. D | Page 50 of 90 M 2 2 F 4 2 S 1 1 HD 0 0 N 16 16 N' 16 16 K For F = 4, K ≥ 5 For F = 2, K ≥ 9 Data Sheet AD6676 SYNCHRONIZATION USING SYSREF± The AD6676 uses the SYSREF± input to provide synchronization for the JESD204B serial output and to establish a fixed phase reference for the decimation filters and the NCO within the QDDC. Synchronization options are configurable via Register 0x1E8. When initially synchronizing, the absolute phase offset relative to the input clock applied to the CLK± pins depends on internal clock phases and therefore has an uncertainty of ±1 ADC clock cycles.  A clock tree diagram is shown in Figure 126 with an internal clock signal, DIG_CLK, used to ultimately sample the SYSREF± signal. Note that the SYSREF± setup and hold times are defined with respect to the rising SYSREF± edge and rising CLK± (or CLK+ with the clock synthesizer disabled) edge, as shown in Figure 2. After the SYSREF± signal is sampled, the phase remains locked to the same relative internal ADC_CLK phase offset until the AD6676 is intentionally reset or its clock or power interrupted.  Note the following considerations when using SYSREF± for synchronization.    The SYSREF± pulse width must be at least two ADC_CLK periods. Bit 3 of Register 0x2BB must be set low when synchronizing with the clock synthesizer enabled. In this case, that SYSREF± is sampled on the rising edge of REF_CLK to allow for significant margin in setup and hold time. This synchronization signal is then sampled again with the internally generated DIG_CLK. Because SYSREF± is ultimately sampled with an internal clock greater than 1 GHz, it can be difficult to maintain synchronization of the clock and SYSREF± distribution in a system over supply and temperature variations, as well as  REG 0x2A5 RF_CLK CLK± ADC_CLK CLOCK SYNTHESIZER fOUT = 5.9GHz TO 6.4GHz TO Σ-∆ ADC AND DIGITAL ÷2 ÷2 DIG_CLK TO DIGITAL REF_CLK Q REG 0x2BB SYSREF± Q D Q D Q TO SYNCHRONIZATION CIRCUITRY 12348-131   cumulative jitter affects. Use the one shot with the second SYSREF pulse to avoid unnecessary resetting of the JES204B link by setting Register 0x1E8 to 0x06. A minimum of two SYSREF pulses are required. The coarse and fine digital NCOs can be reset to an initial phase defined in Register 0x143 through Register 0x145 upon receiving SYSREF±. For the recommended one shot with the second SYSREF pulse, set Register 0x1E8 to 0x26 so that the same SYSREF pulse that is used to reset the JESD204 internal dividers is used to reset the NCO phases. If continuous SYSREF± is still preferred, it is recommended to use the SYSREF_WIN_NEG and SYSREF_WIN_POS bits in Register 0x1EA to allow for slight variation in SYSREF± timing relative to DIG_CLK. A phase variance of ±1 ADC clock cycles ultimately results in fractions of a sample when referenced to the IQ output data rate, fDATA_IQ, depending on the decimation factor. For example, for a decimation factor of 32, the phase uncertainty is expressed as ±1/32 samples relative to fDATA_IQ. The course and fine digital NCOs are also set to an initial phase up defined in Register 0x143 thru Register 0x145 upon receiving SYSREF±. Figure 127 shows how the HMC7044 (or the AD9528) can be used for mulichip synchronization. The HMC7044 is best suited for delivering a low phase noise RF clock source for each AD6676 (refer to Figure 135). In addition, its ability to individually control the delays of both the CLK and SYSREF signals to each AD6676 device allows compensation of PCB skew delays. Figure 126. Block Diagram Showing Options of Sampling the SYSREF Input Signal with the Clock Synthesizer Disabled or Enabled Rev. D | Page 51 of 90 AD6676 Data Sheet HMC7044 (OR AD9528) 1nF CLKOUT0 CLKOUT AD6676 CLK+ 1nF CLK– CLKOUT0 240Ω 240Ω 1nF SCLKOUT1 SYSREF+ SYSREF 1nF SCLKOUT1 SYSREF– 240Ω 240Ω 1nF CLKOUT2 AD6676 CLK+ 1nF CLK– CLKOUT2 240Ω 240Ω 1nF SCLKOUT3 SYSREF+ 1nF 240Ω 240Ω 12348-727 SYSREF– SCLKOUT3 Figure 127. Example of Multichip Synchronization of the AD6676 Using the HMC7044 or the AD9528 Rev. D | Page 52 of 90 Data Sheet AD6676 APPLICATIONS INFORMATION ANALOG INPUT CONSIDERATIONS Table 20. Harmonic Levels When Dual Tones = −6 dBFS of PIN_0dBFS Level is Situated at IF/2 Equivalent Input Impedance and S11 10 61 9 60 8 59 7 58 6 57 5 SHUNT SHUNT SHUNT SHUNT 56 55 54 R WITH ATTENUATOR = 0dB R WITH ATTENUATOR = 6dB C WITH ATTENUATOR = 0dB C WITH ATTENUATOR = 6dB 4 3 2 53 52 IF (MHz) 200 250 300 350 400 LEXT (nH) 43 19 19 10 10 PIN_0dBFS (dBm) −2.5 −2.2 −2.2 −2.2 −2.2 Dual Tone Input Power (dBm) −8.5 −8.2 −8.2 −8.2 −8.2 f1 + f2 Spur (dBc) −69.5 −68.3 −73 −66.3 −68.5 Equivalent IP2 (dBm) 61 60 65 58.5 60 Above the IF pass band, the AD6676 is sensitive to high frequency blockers that can increase the noise floor due to jitter or generate an image component that falls back into the pass band. The AD6676 is also fairly insensitive to spurious tones falling in the alias regions occurring at FADC ± FIF because the AD6676 provides over 50 dB of alias rejection. Table 21 shows the typical alias rejection for different FADC and IF combinations. Because mixers often produce fixed large spurious at M × LO as well as its sum term of LO + FRF, determine if any of these spurs can fall in the alias regions and if so, add the appropriate level of filtering to suppress them below the receivers required spurious level. SHUNT C (pF) 62 1 0 100 200 300 400 500 600 700 FREQUENCY (MHz) 800 900 0 1000 12348-703 SHUNT R (Ω) The AD6676 benign input structure along with its low drive level requirements facilitates interfacing it to external driver circuitry. Figure 128 shows the equivalent parallel impedance for attenuator settings of 0 dB and 6 dB. Note that the slight variation in impedance between the different attenuator settings is an error source affecting the absolute accuracy of the attenuator settings. The AD6676 input also displays excellent S11 return loss over a wide frequency range, as shown in Figure 94. Figure 128. Typical Equivalent Parallel Impedance of AIN for Attenuator = 0 and 6 dB Settings Input Driver and Filter Considerations The input driver requirements, along with any additional filtering, are application dependent. Additional filtering maybe considered if any large signal content or blockers falling above or below the IF pass band of interest can cause desensitization by either increasing the ADC noise or spur floor. Below the IF pass band, the AD6676 is most sensitive to second harmonic content that is typically induced by the driver stage itself due to its limited IP2 performance. The AD6676 second-order nonlinearity contribution is typically on par with a balanced mixer and well below the contribution of a single-ended amplifier stage (with output balun) used for VHF applications. Table 20 shows the measured f1 + f2 spurious level and equivalent IIP2 for different IFs when dual tones are injected at −6 dBFS levels and at IF/2. Table 21. Typical Alias Rejection for Different IF and ADC Combinations FADC (MHz) 2000 2400 2800 3200 IF (MHz) 150 200 300 400 FADC − IF Alias Rejection (dBc) 58 53 51 51 FADC + IF Alias Rejection (dBc) 59 54 59 59 Because the required attenuation of out-of-band signal signals is application dependent, evaluate the AD6676 under the desired application conditions to understand the effects and determine what amount of filtering is required. In practice, a simple thirdorder low-pass roofing filter can provide adequate additional suppression against spurs falling in the alias regions as well as large signal signals falling a few 100 MHz above the IF pass band. Note that the AD6676EBZ includes an optional 500 MHz third-order low-pass filter (TDK MEA1210D501R) that may suffice for many applications. This small, 0302 size differential filter is also available with lower frequency options. Its effect on the pass band flatness is mimimal but provides provides additional suppression beyond 700 MHz. as shown in Figure 129 as well as in the alias region as shown in Table 22. Rev. D | Page 53 of 90 AD6676 Data Sheet harmonics that are sensitive to balance fall outside the pass band. Note that the second harmonic of the gain block still must fall outside the VHF pass band so that it can also be digitally filtered. 0 –5 Some additional considerations pertaining to the analog input are as follows: –10 –15  WITHOUT TDK LPF –20 –25 WITH TDK LPF –30 –35 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) 12348-704 NORMALIZED STF RESPONSE (dBFS) 5  Figure 129. TDK Filter Has Minimal Effect on the Pass Band IF Response Table 22. Typical Alias Rejection for Different IF and ADC Combinations with TDK 500 MHz Low-Pass Filter Added FADC (MHz) 2000 2400 2800 3200 IF (MHz) 150 200 300 400 FADC − IF Alias Rejection (dBc) 82 77 71 74  FADC + IF Alias Rejection (dBc) 83 85 83 81 A 1:1 balun is required in applications where the last amplification stage is single-ended with a ZOUT of 50 Ω. This is typically the case in a VHF receiver application where a gain block, such as the ADL5541 to ADL5545 series, precedes the AD6676 for preamplification. ADL5541 TO ADL5545 DEVICES VHF SIGNAL 1:1 BALUN (MABA-007159) 1nF AD6676 VIN+ 12348-077 VIN– 1nF Figure 130. RF Line-Up for Direct Sampling VHF Application For many RF receiver applications, this differential signal may originate from a RF-to-IF mixer whose output impedance often falls within a 50 Ω to 200 Ω range. A low order matching network that also serves as a low-pass roofing filter can compensate for the mismatch impedance. It is worth noting that the impedance mismatch between a source/load mismatch of 200 Ω/60 Ω and 100 Ω/60 Ω is approximately 1.5 dB and 0.3 dB, respectively. This low mismatch loss may be tolerable for some applications seeking a wide, low ripple IF pass band, especially considering the loss of a higher order matching network with finite Q components. Lastly, it is possible to reduce the ADC maximum input power requirements slightly to compensate for this low loss with minimal loss in dynamic range. Other receiver applications in the VHF band may prefer that the AD6676 directly digitize the signal. Typically, the radio lineup may include a low NF gain block whose single-ended output is converted to a differential output via an ac-coupled balun. The amplitude/phase balance requirements of balun can be relaxed (compared to traditional pipeline ADCs) because the even order AC coupling with 10 nF or greater capacitors to the VIN± input is required to a maintain 1 V common-mode voltage. Note that this capacitor provides a high-pass response with the AD6676 input impedance and thus must be sized accordingly for low IF applications to prevent excessive droop on the lower pass band response. A series 10 Ω resistor and 0.1 μF decoupling capacitor is recommended between the 2.5 V supply and first resonators to provide additional filtering of supply induced noise and ADC common-mode currents. The feedback DAC (operating up to 3.2 GHz) also generates high frequency content (that is, images, clock feedthrough and shaped noise) that is ideally absorbed by the internal source follower. Due to its finite impedance at the higher frequencies, a small amount of this undesired signal content leaks through the attenuator path back to the VIN± input. Passive mixers are particularly susceptible to this signal content due to poor isolation between the IF and RF ports while passive mixers with on-chip IF amps and active mixers provide a greater degree of reverse isolation. A simple third-order roofing filter typically provides sufficient rejection to suppress these ADC artifacts while also suppressing the larger M × N artifacts of the mixer. Note that this filter must be designed as two single-ended, pi network filters with shunt capacitors located next to the VIN± pins to steer this undesired signal content to ground. Also, use care in component selection and layout to reduce parasitics that can cause unanticipated peaking in the stop-band region of the filter response. CLOCK INPUT CONSIDERATIONS The AD6676 Σ-Δ ADC operates with an internal ADC clock rate (FADC) between 2.0 GSPS to 3.2 GSPS. The clock signal can originate from an external clock source or, alternatively, from its on-chip clock synthesizer. Consider an external clock source if the on-chip synthesizer phase noise or spurious level is not deemed sufficient or if the desired FADC falls below the 2.94 GHz to 3.2 GHz range of the VCO. Referring to Figure 60, the selfbiased clock receiver is configured as either a differential or singleended receiver, depending on whether the clock synthesizer is disabled. In either case, the external clock source must be ac coupled to the AD6676 CLK± input and meet the minimum specified input level and slew rate. Also, clock jitter and phase noise must always be a concern in selecting the clock source. When the clock synthesizer is enabled, the CLK± inputs are connected to CMOS inverters as shown in Figure 60. These inverters are self-biased at approximately 0.55 V and present an input resistance exceeding 1.2 kΩ when Bit 2 of Register 0x2BB is set. Rev. D | Page 54 of 90 Data Sheet AD6676 When the clock synthesizer is disabled, the CLK± inputs are connected to a high speed differential clock receiver with on-chip 100 Ω termination to simplify interfacing to CML, LVPECL, or sinusoidal clock sources. The clock signal is typically ac-coupled to the CLK+ and CLK− pins via an RF balun or capacitors. These pins are biased internally (see Figure 60) at approximately 700 mV and require no external bias. The equivalent shunt impedance of the CLK± input is shown in Figure 131. It is recommended to use a 100 Ω differential transmission line to route the clock signal to the CLK+ and CLK− pins due to the high frequency nature of the signal. 130 INSTALL 100Ω DIFFERENTIAL RESISTOR ONLY WHEN CLK SYN IS ENABLED HMC7044, AD9528 OR ADCLK925 CLK+ 10nF PECL DRIVER AD6676 10nF CLK– 240Ω 240Ω 1.0 110 0.6 100 0.4 90 0.2 80 0 70 Figure 133. Differential PECL Sample Clock Using the HMC7044, AD9528, and ADCLK925 0.8 CAPACITANCE (pF) REAL SHUNT CAPACITANCE SHUNT 120 –0.2 60 50 2.0 2.5 3.0 –0.4 4.0 3.5 FREQUENCY (GHz) 12348-705 REAL SHUNT (Ω) A single-ended CMOS or differential ac-coupled PECL/HSTL clock signal can be delivered via clock generation and distribution ICs such as the Analog Devices HMC7044, AD9528, and ADCLK925. A PECL clock signal is recommended when providing an RF clock input signal to the AD6676 or in applications that require deterministic latency or synchronization while using the internal clock synthesizer of the AD6676. Figure 133 shows a simple differential interface in which the AD6676 interfaces to the PECL output available from these ICs. The HMC7044 is an excellent choice for JESD204B clock generation and multichip synchronization because it also generates a very low phase noise RF clock from 2.4 GHz to 3.2 GHz for multiple AD6676 devices. 12348-081 A single-ended clock source need only be ac coupled to the CLK+ input because the inverter output for CLK− input is not used. For CMOS drivers, the addition of a 33 Ω series resistor is recommended to dampen the response for long trace lengths. For a differential clock source, such as an LVDS or PECL source, the addition of a 100 Ω external termination resistor across the CLK± pins is recommended to minimize any reflections that result from distorting the clock input waveform. Alternatively, PLL clock synthesizers with on-chip VCOs such as the ADF4351, the ADF4355-2, and HMC1034 also make excellent RF clock sources when multichip synchronization is not required. The CML outputs of these devices allow a simple interface as shown in Figure 134. Figure 135 compares the close in phase noise between the ADF4351, the ADF4355-2, the HMC7044, the AD6676 clock synthesizer, and the R&S SMA100A for a near full-scale sine wave at 300 MHz. Note that the phase noise improvement offered by the high quality RF generator only becomes evident below 400 kHz when compared to the ADF4351. Figure 131. Equivalent Shunt Differential Input Impedance of the CLK± Pins with the Clock Synthesizer Disabled 3.9nH PLL FREF VCO REFOUTA+ AD6676 CLK+ CLK– REFOUTA– ADF4351 ADF4355-2 1nF REFOUTB+ REFOUTB– 1nF 0.8V p-p 12348-079 VVCO DIV-BY-2N Figure 132 shows a single-ended clock solution for the AD6676 when its clock synthesizer is disabled. The low phase noise singleended source can be from an external VCXO. A ceramic RF chip 1:2 ratio balun creates the differential clock input signal. The balun must be specified to have low loss (that is, less than 2 dB) at the clock frequency of interest. The single-ended clock source must be capable of 0 dBm drive capability to ensure adequate signal swing into the clock input. Figure 134. Differential CML Driver from the ADF4351 and the ADF4355-2 100pF 100pF AD6676 CLK+ CLK– JT 4000BL14100 100pF 12348-078 CLOCK INPUT Figure 132. Balun Coupled Differential Clock Rev. D | Page 55 of 90 AD6676 Data Sheet –110 Figure 136 shows a normalized image graph (relative to fDATA_IQ) showing the image location relative for a given input frequency. ADF4351 When N > 1, spurious content is often at lower magnitude than other spurious thus often can be ignored. The exception is when fIN falls below the IF pass band such that its lower order harmonics may fall within the pass band (that is, IF/2 and IF/3). –120 –125 AD6676 CLK SYN –130 –135 ADF4355-2 R&S SMA100A 4.5 M=3 –140 M=2 M=1 4.0 HMC7044 0.1 FREQUENCY OFFSET (MHz) 1 Figure 135. Close In Phase Noise Comparison for Different Analog Devices Clock Sources when Compared to the R&S SMA100A and the AD6676 Clock Synthesizer (IF = 300 MHz, BW = 40 MHz, FADC = 3.2 GHz, L = 19 nH) IF FREQUENCY PLANNING 3.0 M=7 2.5 2.0 M=6 1.5 1.0 The Σ-Δ ADC can achieve exceptional SFDR performance over a wide IF frequency range because its high oversampling ratio prevents low order harmonics from aliasing into the IF pass band. Higher order harmonics that do alias back are typically of much lower magnitude, with the shuffling option further reducing their levels. However, finite isolation between the Σ-Δ ADC and the digital block causes additional spurious signals that are a function of the output data rate, fDATA_IQ, and input frequency, fIN. Specifically, the feedback DACs in the Σ-Δ ADC suffer from digital contamination of its clock signal. Therefore, the same equation used to predict spurious locations on high speed DACs with digital interpolation filters applies. Equation 15 defines this relationship with the spur location falling at fMN. fMN = ±(M × fDATA_IQ) ± (N × fIN) M=8 3.5 (15) where: M is the digital induced harmonic content from internal clocks. N is the harmonics from the Σ-Δ ADC. When N = 0, signal independent spurs fall at integer multiples of fDATA_IQ. Table 23 shows the measured M × fDATA_IQ spurious levels (dBFS) for different IF frequencies and decimation factors with fDATA_IQ equal to 100 MSPS and 200 MSPS. All of the M × fDATA_IQ regions display low spurious with the exception of 200 MHz. This is because a large portion of digital circuitry is clocked at FADC/16 for DEC_MODES of 1 and 3 or FADC/12 for DEC_MODES of 2 and 4. As a result, the M = 2 spur is dominant when operating at the higher decimation factors of 32 and 24 whereas the M = 1 spur is dominant when operating at the lower decimation factors of 16 and 12. When N = 1, signal dependent spurs falls at integer multiples of fDATA_IQ. These M × N spurs are called images because they have a 1:1 relationship in amplitude and frequency with the input signal, fIN. Note that the magnitude of some images can also vary slightly between power cycles, due to different phase relationships among internal clock dividers upon device initialization. M=2 0.5 0.5 1.0 M=3 1.5 2.0 M=4 2.5 3.0 M=5 3.5 4.0 4.5 NORMALIZED INPUT FREQUENCY 12348-082 –150 –155 0.01 NORMALIZED IMAGE LOCATION –145 12348-080 PHASE NOISE @ IF = 300MHz (dBc/Hz) AVG = 300 –115 Figure 136. Image Location for Different M Factors Normalized to fDATA_IQ Table 23. Measured Spurious Levels at Different IFs Where M × fDATA_IQ Falls On for fDATA_IQ of 100 MSPS and 200 MSPS fDATA_IQ 100 MSPS DEC_MODE = 1 DEC_MODE = 2 200 MSPS DEC_MODE = 3 DEC_MODE = 4 1 IF = 100 MHz Spurious Levels (dBFS) IF = IF = IF = 200 MHz 300 MHz 400 MHz