ADPD105BCBZR7

Photometric Front Ends ADPD105/ADPD106/ADPD107 Data Sheet FEATURES GENERAL DESCRIPTION Multifunction photometric front end Fully integrated AFE, ADC, LED drivers, and timing core Enables best-in-class ambient light rejection capability without the need for photodiode optical filters Three 370 mA LED drivers Flexible, multiple, short LED pulses per optical sample 20-bit burst accumulator enabling 20 bits per sample period On-board sample to sample accumulator, enabling up to 27 bits per data read Low power operation SPI, I2C interface, and 1.8 V analog/digital core Flexible sampling frequency ranging from 0.122 Hz to 3820 Hz FIFO data operation The ADPD105/ADPD106/ADPD107 are highly efficient, photometric front ends, each with an integrated 14-bit analogto-digital converter (ADC) and a 20-bit burst accumulator that works with flexible light emitting diode (LED) drivers. The accumulator is designed to stimulate an LED and measure the corresponding optical return signal. The data output and functional configuration occur over a 1.8 V I2C interface on the ADPD105 or SPI on the ADPD106 and ADPD107. The control circuitry includes flexible LED signaling and synchronous detection. APPLICATIONS Couple the ADPD105/ADPD106/ADPD107 with a low capacitance photodiode of 0x3FFF ADPD105/ADPD106/ADPD107 Data Sheet LED SLOTx_AFE_OFFSET + 9 NEGATIVE SAMPLE REGION POSITIVE SAMPLE REGION NEGATIVE SAMPLE REGION 14693-039 SAMPLE Figure 46. Digital Integration Mode in Double-Sample Pair Mode with Continuous Sample Timing LED SAMPLE NEGATIVE SAMPLE REGION POSITIVE SAMPLE REGION SLOTx_AFE_FOFFSET NEGATIVE SAMPLE REGION SLOTx_AFE_FOFFSET 14693-040 SLOTx_AFE_OFFSET + 9 Figure 47. Digital Integration Mode in Double-Sample Pair Mode with Gapped Sample Timing LED SAMPLE NEGATIVE SAMPLE REGION POSITIVE SAMPLE REGION SLOTx_AFE_FOFFSET 14693-041 SLOTx_AFE_OFFSET + 9 Figure 48. Digital Integration Mode in Single-Sample Pair Mode with Gapped Sample Timing LED SLOTx_AFE_OFFSET + 9 NEGATIVE SAMPLE REGION POSITIVE SAMPLE REGION Figure 49. Digital Integration Mode in Single-Sample Pair Mode with Continuous Sample Timing Rev. A | Page 44 of 66 14693-042 SAMPLE Data Sheet ADPD105/ADPD106/ADPD107 Table 27. Configuration Registers to Switch Between the Normal Sample Mode, TIA ADC Mode, and Digital Integration Mode Bit Name SLOTA_AFE_MODE Normal Mode Value 0x1C TIA ADC Mode Value Not applicable Digital Integration Mode Value 0x1D 7 SLOTA_INT_AS_BUF 0x0 0x1 Not applicable 0x43 [15:0] SLOTA_AFE_CFG 0xADA5 0xAE65 0xAE65 0x44 [15:8] SLOTB_AFE_MODE 0x1C Not applicable 0x1D 7 SLOTB_INT_AS_BUF 0x0 0x1 Not applicable 0x45 [15:0] SLOTB_AFE_CFG 0xADA5 0xAE65 0xAE65 0x4E [15:0] ADC_TIMING Not applicable 0x0040 0x58 13 SLOTB_DIGITAL_INT_EN Not applicable 0x0 0x0 0x1 12 SLOTA_DIGITAL_INT_EN 0x0 0x0 0x1 [15:0] DIG_INT_CFG Not applicable Not applicable Variable Address 0x42 0x5A Data Bits [15:8] PULSE CONNECT MODE In pulse connect mode, the photodiode input connections are pulsed according to the timing set up in the LED pulse timing registers. In this mode, if the LED pulse timing is set up to provide a 2 μs LED pulse, the device pulses the connection to the photodiode input for 2 μs instead of providing a 2 μs LED pulse. This mode is an alternate to TIA ADC mode, allowing the entire signal path, including the band-pass filter and integrator, to be used to measure ambient light as well as other types of measurements with different types of sensors (for example, ECGs). Description In normal mode, this setting configures the integrator block for optimal operation. In digital integration mode, this setting configures the integrator block as a buffer. This setting is not important for TIA ADC mode. 0: normal integrator configuration. 1: convert integrator to buffer amplifier (this is done automatically in digital integrate mode). Time Slot A AFE connection. 0xAE65 bypasses the band-pass filter. 0xB065 can also be used in TIA ADC mode. This setting bypasses the BPF and the integrator. In normal mode, this setting configures the integrator block for optimal operation. In digital integration mode, this setting configures the integrator block as a buffer. This setting is not important for TIA ADC mode. 0: normal integrator configuration. 1: convert integrator to buffer amplifier (this is done automatically in digital integrate mode). Time Slot B AFE connection. 0xAE65 bypasses the band-pass filter. 0xB065 can also be used in TIA ADC mode. This setting bypasses the BPF and the integrator. Set ADC clock to 1 MHz in TIA ADC mode. Digital integrate mode enable, Time Slot B. 0: disable. 1: enable. Digital integrate mode enable, Time Slot A. 0: disable. 1: enable. Configuration of digital integration depends on the use case. This register is ignored for other modes. To enable pulse connect mode, the device is configured identically to normal mode, except that Register 0x14, Bits[3:2] = 0 for Time Slot B, and Register 0x14, Bits[1:0] = 0 for Time Slot A. SYNCHRONOUS ECG AND PPG MEASUREMENT USING TIA ADC MODE In wearable devices developed for monitoring the health care of patients, it is often necessary to have synchronized measurements of biomedical signals. For example, a synchronous measurement of patient ECG and PPG can be used to determine the pulse wave transit time (PWTT), which can then be used to estimate blood pressure. Rev. A | Page 45 of 66 ADPD105/ADPD106/ADPD107 Data Sheet ECG measurements. Data can be read out of the on-chip FIFO or straight from data registers. The ADPD105 channel used to process the ECG signal is set up in TIA ADC mode and the input bias voltage must be set to the 0.90 V setting using Bits[5:4] of Register 0x42 if the ECG signal is on Time Slot A, or Register 0x44 on Time Slot B. The TIA gain setting can be set to optimize the dynamic range of the signal path. The channel used to process the PPG signal is configured in its normal operating mode. Figure 51 shows a plot of a synchronized ECG and PPG measurement using the AD8233 with the ADPD105. The circuit shown in Figure 50 shows a synchronous ECG and PPG measurement using the AD8233 and the ADPD105. The AD8233 implements a two-pole high-pass filter with a cutoff frequency at 0.3 Hz, and a two-pole low-pass filter with a cutoff frequency of 37 Hz. The output of the AD8233 is fed to one of the current inputs of the ADPD105 through a 50 kΩ resistor to convert the voltage output of the AD8233 into a current. The ADPD105 is configured to alternately measure the photodiode signal and the ECG signal from the AD8233 on consecutive timeslots to provide fully synchronized PPG and 1.8V 4.7µF 10MΩ 180kΩ 4.7µF –IN REFIN 0.1µF 10MΩ 0.1µF 1nF RLD 1MΩ GND AD8233 1.8V FR OPAMP+ AC/DC REFOUT SDN OPAMP– RLD SDN 6.8nF 250kΩ TO DIGITAL INTERFACE LOD ADPD105 50kΩ 1.8V DVDD PD1-2 0.1µF AVDD VLED PDC 0.1µF AGND DGND LGND PD3-4 1.8V 10kΩ 10kΩ LEDX1 SCL VREF 1µF SDA TO DIGITAL INTERFACE GPIO0 GPIO1 Figure 50. Synchronized PPG and ECG Measurement Using ADPD105 with the AD8233 10000 52000 9500 PPG 8500 8000 51000 ECG 7500 ECG (LSBs) 9000 51500 7000 50500 6500 50000 SAMPLE RATE (ms) Figure 51. Plot of Synchronized ECG and PPG Waveforms Rev. A | Page 46 of 66 14693-044 343 325 307 289 271 253 235 127 91 109 73 55 37 6000 14693-043 OUT 1 1MΩ 19 2.7nF 217 100kΩ 10MΩ +VS RLDFB SW 1MΩ 1.8V 199 360kΩ IAOUT PPG (LSBs) RL 10MΩ +IN 181 RA HPSENSE 163 LA HPDRIVE 180kΩ 145 10MΩ Data Sheet ADPD105/ADPD106/ADPD107 In some situations, as in a case where a synchronized ECG and PPG measurement is being attempted, a voltage measurement must be made using the current inputs of the ADPD105/ ADPD106/ADPD107. First, convert the voltage source to a current by placing a series resistor, RS, in series between the voltage source and the current input of the device, as shown in Figure 52. voltage source through a series resistance, RIN must be taken into consideration. The conversion gain from a voltage into a current can be determined by following the schematic in Figure 52. IIN = (VIN − TIA_VREF)/(RS + RIN) Typically, RIN is approximately 13 kΩ. The value of RIN varies as a function of supply voltage. This variability is shown in Figure 53 45 +85°C +25°C 0°C –40°C 40 ADPD105/ADPD106/ ADPD107 RIN IIN TIA_VREF TIA ADC Figure 52. Using the ADPD105/ADPD106/ADPD107 Inputs with Voltage Sources Secondly, there is a switch resistance, RIN, that must be taken into consideration when converting a voltage source to a current. This switch resistance is not a factor in a typical photodiode application since the device is only dealing with input currents and these currents are not a function of the input resistance. However, when driving the device inputs from a MEASURED R IN (kΩ) RS 14693-108 VIN 35 30 25 20 15 10 5 0 1.70 1.75 1.80 1.85 VDD SUPPLY VOLTAGE (V) 1.90 1.95 14693-112 Measuring Voltages Using the Current Inputs Figure 53. Variability of Switch Input Resistance as a Function of VDD Supply Voltage Rev. A | Page 47 of 66 ADPD105/ADPD106/ADPD107 Data Sheet REGISTER LISTING Table 28. Numeric Register Listing1 Hex. Addr. Name 0x00 Status 0x01 0x02 0x06 INT_MASK GPIO_DRV FIFO_ THRESH 0x08 DEVID 0x09 I2CS_ID 0x0A CLK_RATIO 0x0B GPIO_CTRL 0x0D SLAVE_ ADDRESS_ KEY SW_RESET 0x0F 0x10 Mode 0x11 SLOT_EN 0x12 FSAMPLE 0x14 PD_LED_ SELECT 0x15 NUM_AVG 0x18 SLOTA_CH1_ OFFSET 0x19 SLOTA_CH2_ OFFSET 0x1A SLOTA_CH3_ OFFSET 0x1B SLOTA_CH4_ OFFSET 0x1E SLOTB_CH1_ OFFSET 0x1F SLOTB_CH2_ OFFSET 0x20 SLOTB_CH3_ OFFSET 0x21 SLOTB_CH4_ OFFSET Bit 15 Bit 7 Bits [15:8] [7:0] Reserved [15:8] Bit 14 Bit 6 Bit 13 Bit 5 SLOTB_INT SLOTA_INT [7:0] SLOTB_INT_ MASK [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] Reserved Bit 12 Bit 11 Bit 4 Bit 3 FIFO_SAMPLES[7:0] Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Reset 0x0000 RW R/W 0x00FF R/W GPIO1_POL 0x0000 GPIO0_POL 0x0000 R/W Reserved Reserved FIFO_INT_ MASK Reserved SLOTA_INT_ MASK Reserved Reserved GPIO0_ENA FIFO_THRESH[5:0] Reserved GPIO1_DRV GPIO0_DRV Reserved REV_NUM[7:0] DEV_ID[7:0] ADDRESS_WRITE_KEY[7:0] SLAVE_ADDRESS[6:0] Reserved R/W 0x0516 R 0x00C8 R/W 0x0000 R 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x1000 R/W 0x0028 R/W 0x0541 R/W 0x0600 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 RW Reserved CLK_RATIO[11:8] CLK_RATIO[7:0] Reserved Reserved GPIO1_ALT_CFG[4:0] GPIO0_ALT_CFG[4:0] SLAVE_ADDRESS_KEY[15:8] SLAVE_ADDRESS_KEY[7:0] Reserved Reserved Reserved Reserved Reserved RDOUT_ FIFO_OVRN_ MODE PREVENT SW_RESET Reserved Mode[1:0] SLOTB_ FIFO_ MODE[2] Reserved SLOTA_EN [7:0] SLOTB_FIFO_MODE[1:0] SLOTB_EN SLOTA_FIFO_MODE[2:0] [15:8] FSAMPLE[15:8] [7:0] FSAMPLE[7:0] [15:8] Reserved SLOTB_PD_SEL[3:0] [7:0] SLOTA_PD_SEL[3:0] SLOTB_LED_SEL[1:0] SLOTA_LED_SEL[1:0] [15:8] Reserved SLOTB_NUM_AVG[2:0] [7:0] Reserved SLOTA_NUM_AVG[2:0] Reserved [15:8] SLOTA_CH1_OFFSET[15:8] [7:0] SLOTA_CH1_OFFSET[7:0] [15:8] SLOTA_CH2_OFFSET[15:8] [7:0] SLOTA_CH2_OFFSET[7:0] [15:8] SLOTA_CH3_OFFSET[15:8] [7:0] SLOTA_CH3_OFFSET[7:0] [15:8] SLOTA_CH4_OFFSET[15:8] [7:0] SLOTA_CH4_OFFSET[7:0] [15:8] SLOTB_CH1_OFFSET[15:8] [7:0] SLOTB_CH1_OFFSET[7:0] [15:8] SLOTB_CH2_OFFSET[15:8] [7:0] SLOTB_CH2_OFFSET[7:0] [15:8] SLOTB_CH3_OFFSET[15:8] [7:0] SLOTB_CH3_OFFSET[7:0] [15:8] SLOTB_CH4_OFFSET[15:8] [7:0] SLOTB_CH4_OFFSET[7:0] Rev. A | Page 48 of 66 Data Sheet ADPD105/ADPD106/ADPD107 Hex. Addr. Name 0x22 ILED3_ COARSE 0x23 0x24 0x25 0x30 0x31 0x34 0x35 0x36 0x37 0x38 0x39 0x3B 0x3C Bits [15:8] [7:0] [15:8] ILED1_ COARSE [7:0] [15:8] ILED2_ COARSE [7:0] ILED_FINE [15:8] [7:0] SLOTA_LED_ [15:8] PULSE [7:0] [15:8] SLOTA_ NUMPULSES [7:0] [15:8] LED_ DISABLE [7:0] SLOTB_LED_ [15:8] PULSE [7:0] [15:8] SLOTB_ NUMPULSES [7:0] [15:8] ALT_PWR_ DN [7:0] EXT_SYNC_ [15:8] STARTUP [7:0] SLOTA_AFE_ [15:8] WINDOW [7:0] SLOTB_AFE_ [15:8] WINDOW [7:0] [15:8] AFE_PWR_ CFG1 0x42 SLOTA_ TIA_CFG 0x43 SLOTA_ AFE_CFG 0x44 SLOTB_ TIA_CFG 0x45 SLOTB_ AFE_CFG 0x4B SAMPLE_ CLK 0x4D 0x4E 0x4F 0x50 0x54 [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] ADC_CLOCK [15:8] [7:0] EXT_SYNC_ [15:8] SEL [7:0] [15:8] CLK32M_ CAL_EN [7:0] CLK32M_ ADJUST AFE_PWR_ CFG2 [15:8] [7:0] 0x55 TIA_INDEP_ GAIN [15:8] [7:0] Bit 15 Bit 7 Bit 14 Bit 6 Reserved Reserved Reserved Reserved Reserved Reserved ILED2_FINE[1:0] Reserved Bit 13 Bit 12 Bit 5 Bit 4 ILED3_SCALE ILED3_SLEW[2:0] ILED1_SCALE ILED1_SLEW[2:0] ILED2_SCALE Reserved ILED2_SLEW[2:0] ILED3_FINE[4:0] Reserved Bit 11 Bit 3 Bit 10 Bit 9 Bit 2 Bit 1 Reserved ILED3_COARSE[3:0] Reserved ILED1_COARSE[3:0] Bit 8 Bit 0 ILED2_COARSE[3:0] ILED2_FINE[4:2] ILED1_FINE[4:0] SLOTA_LED_WIDTH[4:0] SLOTA_LED_OFFSET[7:0] SLOTA_LED_NUMBER[7:0] SLOTA_LED_PERIOD[7:0] Reserved SLOTB_ LED_DIS SLOTA_ LED_DIS Reset 0x3000 RW R/W 0x3000 R/W 0x3000 R/W 0x630C R/W 0x0320 R/W 0x0818 R/W 0x0000 R/W 0x0320 R/W 0x0818 R/W 0x0000 R/W 0x000 R/W 0x22FC R/W 0x22FC R/W 0x3006 R/W 0x1C38 R/W Reserved Reserved SLOTB_LED_WIDTH[4:0] SLOTB_LED_OFFSET[7:0] SLOTB_LED_NUMBER[7:0] SLOTB_LED_PERIOD[7:0] CH34_DISABLE[15:13] CH2_DISABLE[12:10] Reserved Reserved EXT_SYNC_STARTUP[15:8] EXT_SYNC_STARTUP[7:0] SLOTA_AFE_WIDTH[4:0] SLOTA_AFE_OFFSET[5:3] SLOTA_AFE_OFFSET[2:0] SLOTA_AFE_FOFFSET[4:0] SLOTB_AFE_WIDTH[4:0] SLOTB_AFE_OFFSET[5:3] SLOTB_AFE_OFFSET[2:0] SLOTB_AFE_FOFFSET[4:0] Reserved Reserved Reserved V_CATHODE AFE_ POWERDOWN[5] AFE_POWERDOWN[4:0] Reserved SLOTA_AFE_MODE[7:0] SLOTA_TIA_VBIAS[1:0] Reserved (write 0x1) SLOTA_TIA_GAIN[1:0] SLOTA_INT_ SLOTA_TIA_ AS_BUF IND_EN SLOTA_AFE_CFG[15:8] SLOTA_AFE_CFG[7:0] SLOTB_AFE_MODE[7:0] SLOTB_TIA_VBIAS[1:0] Reserved (write 0x1) SLOTB_TIA_GAIN[1:0] SLOTB_INT_ SLOTB_ AS_BUF TIA_IND_EN SLOTB_AFE_CFG[15:8] SLOTB_AFE_CFG[7:0] Reserved CLK32K_ BYP CLK32K_EN Reserved CLK32K_ADJUST[5:0] Reserved CLK32M_ADJUST[7:0] ADC_TIMING[15:8] ADC_TIMING[7:0] Reserved Reserved GPIO1_OE GPIO1_IE Reserved EXT_SYNC_SEL[1:0] GPIO0_IE Reserved Reserved Reserved GPIO1_CTRL Reserved CLK32M_ CAL_EN SLEEP_V_CATHODE [1:0] SLOTB_V_CATHODE[1:0] SLOTA_V_CATHODE[1:0] SLOTB_ SLOTA_ SINGLE_CH_ SINGLE_CH_ DIG_INT DIG_INT Reserved REG54_VCAT_ ENABLE DIGINT_POWER[2:0] Reserved SLOTB_TIA_GAIN_4[1:0] SLOTB_TIA_GAIN_3[1:0] SLOTB_TIA_GAIN_2[1:0] SLOTA_TIA_GAIN_4[1:0] SLOTA_TIA_GAIN_3[1:0] SLOTA_TIA_GAIN_2[1:0] Rev. A | Page 49 of 66 0xADA5 R/W 0x1C38 R/W 0xADA5 R/W 0x2612 R/W 0x0098 R/W 0x0060 R/W 0x2090 R/W 0x0000 R/W 0x0020 R/W 0x0000 R/W ADPD105/ADPD106/ADPD107 Hex. Addr. Name 0x58 DIGITAL_ INT_EN 0x5A 0x5F DIG_ INT_CFG Bit 15 Bit 7 Bits [15:8] [7:0] [15:8] [7:0] DIG_INT_ GAPMODE [15:8] DATA_ ACCESS_CTL [7:0] 0x60 FIFO_ ACCESS 0x64 SLOTA_ PD1_16BIT 0x65 SLOTA_ PD2_16BIT 0x66 SLOTA_ PD3_16BIT 0x67 SLOTA_ PD4_16BIT 0x68 SLOTB_ PD1_16BIT 0x69 SLOTB_ PD2_16BIT 0x6A SLOTB_ PD3_16BIT 0x6B SLOTB_ PD4_16BIT 0x70 A_PD1_ LOW 0x71 A_PD2_ LOW 0x72 A_PD3_ LOW 0x73 A_PD4_ LOW 0x74 A_PD1_ HIGH 0x75 A_PD2_ HIGH 0x76 A_PD3_ HIGH 0x77 A_PD4_ HIGH 0x78 B_PD1_ LOW 0x79 B_PD2_ LOW 0x7A B_PD3_ LOW 0x7B B_PD4_ LOW 0x7C B_PD1_ HIGH 0x7D B_PD2_ HIGH [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 14 Bit 6 Reserved SLOTB_DIG_ INT_SAMPLE_ MODE Data Sheet Bit 13 Bit 5 SLOTB_ DIGITAL_ INT_EN Bit 12 Bit 11 Bit 4 Bit 3 SLOTA_ DIGITAL_INT_ EN Reserved Reserved Bit 10 Bit 2 Bit 9 Bit 1 Reserved Bit 8 Bit 0 Reset 0x0000 RW R/W 0x0000 R/W 0x0000 R/W 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R Reserved SLOTA_DIG_ INT_SAMPLE_ MODE Reserved Reserved SLOTB_ DATA_ HOLD FIFO_DATA[15:8] FIFO_DATA[7:0] SLOTA_CH1_16BIT[15:8] SLOTA_CH1_16BIT[7:0] SLOTA_CH2_16BIT[15:8] SLOTA_CH2_16BIT[7:0] SLOTA_CH3_16BIT[15:8] SLOTA_CH3_16BIT[7:0] SLOTA_CH4_16BIT[15:8] SLOTA_CH4_16BIT[7:0] SLOTB_CH1_16BIT[15:8] SLOTB_CH1_16BIT[7:0] SLOTB_CH2_16BIT[15:8] SLOTB_CH2_16BIT[7:0] SLOTB_CH3_16BIT[15:8] SLOTB_CH3_16BIT[7:0] SLOTB_CH4_16BIT[15:8] SLOTB_CH4_16BIT[7:0] SLOTA_CH1_LOW[15:8] SLOTA_CH1_LOW[7:0] SLOTA_CH2_LOW[15:8] SLOTA_CH2_LOW[7:0] SLOTA_CH3_LOW[15:8] SLOTA_CH3_LOW[7:0] SLOTA_CH4_LOW[15:8] SLOTA_CH4_LOW[7:0] SLOTA_CH1_HIGH[15:8] SLOTA_CH1_HIGH[7:0] SLOTA_CH2_HIGH[15:8] SLOTA_CH2_HIGH[7:0] SLOTA_CH3_HIGH[15:8] SLOTA_CH3_HIGH[7:0] SLOTA_CH4_HIGH[15:8] SLOTA_CH4_HIGH[7:0] SLOTB_CH1_LOW[15:8] SLOTB_CH1_LOW[7:0] SLOTB_CH2_LOW[15:8] SLOTB_CH2_LOW[7:0] SLOTB_CH3_LOW[15:8] SLOTB_CH3_LOW[7:0] SLOTB_CH4_LOW[15:8] SLOTB_CH4_LOW[7:0] SLOTB_CH1_HIGH[15:8] SLOTB_CH1_HIGH[7:0] SLOTB_CH2_HIGH[15:8] SLOTB_CH2_HIGH[7:0] Rev. A | Page 50 of 66 SLOTA_ DATA_ HOLD DIGITAL_ CLOCK_ ENA Data Sheet Hex. Addr. Name 0x7E B_PD3_ HIGH 0x7F 1 B_PD4_ HIGH ADPD105/ADPD106/ADPD107 Bit 15 Bit 7 Bits [15:8] [7:0] [15:8] [7:0] Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 11 Bit 4 Bit 3 SLOTB_CH3_HIGH[15:8] SLOTB_CH3_HIGH[7:0] SLOTB_CH4_HIGH[15:8] SLOTB_CH4_HIGH[7:0] Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Reset 0x0000 RW R 0x0000 R The recommended values are not shown. Only power-on reset values are shown in Table 28. The recommended values are largely dependent on use case. See Table 29 to Table 35 for the recommended values. Rev. A | Page 51 of 66 ADPD105/ADPD106/ADPD107 Data Sheet LED CONTROL REGISTERS Table 29. LED Control Registers Address 0x14 0x22 Data Bit [15:12] [11:8] Default Value 0x0 0x5 Access R/W R/W Name Reserved SLOTB_PD_SEL [7:4] 0x4 R/W SLOTA_PD_SEL [3:2] 0x0 R/W SLOTB_LED_SEL [1:0] 0x1 R/W SLOTA_LED_SEL [15:14] 13 0x0 0x1 R/W R/W Reserved ILED3_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED3_SLEW [3:0] 0x0 R/W ILED3_COARSE Description Write 0x0 to these bits for proper operation. PDx connection selection for Time Slot B. See Figure 22 and Figure 23 0x0: all photodiode inputs are floating. 0x1: all photodiode inputs are connected during Time Slot B. 0x5: PD1/PD2/PD3/PD4 are connected during Time Slot B. Other: reserved. PDx connection selection for Time Slot A. See Figure 22 and Figure 23. 0x0: all photodiode inputs are floating. 0x1: all photodiode inputs are connected during Time Slot A. 0x5: PD1/PD2/PD3/PD4 are connected during Time Slot A. Other: reserved. Time Slot B LED configuration. These bits determine which LED is associated with Time Slot B. 0x0: pulse PDx connection to AFE. 0x1: LEDX1 pulses during Time Slot B. 0x2: LEDX2 pulses during Time Slot B. 0x3: LEDX3 pulses during Time Slot B. Time Slot A LED configuration. These bits determine which LED is associated with Time Slot A. 0x0: pulse PDx connection to AFE. 0x1: LEDX1 pulses during Time Slot A. 0x2: LEDX2 pulses during Time Slot A. 0x3: LEDX3 pulses during Time Slot A. Write 0x0. LEDX3 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX3 driver in low power mode. LEDX3 Current Scale = 0.4 + 0.6 × (Register 0x22, Bit 13). Write 0x1. Write 0x0. LEDX3 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0x0: the slowest slew rate. … 0x7: the fastest slew rate. LEDX3 coarse current setting. Coarse current sink target value of LEDX3 in standard operation. 0x0: lowest coarse setting. … 0xF: highest coarse setting. LED3PEAK = LED3COARSE × LED3FINE × LED3SCALE where: LED3PEAK is the LEDX3 peak target value (mA). LED3COARSE = 50.3 + 19.8 × (Register 0x22, Bits[3:0]). LED3FINE = 0.74 + 0.022 × (Register 0x25, Bits[15:11]). LED3SCALE = 0.4 + 0.6 × (Register 0x22, Bit 13). Rev. A | Page 52 of 66 Data Sheet Address 0x23 0x24 ADPD105/ADPD106/ADPD107 Data Bit [15:14] 13 Default Value 0x0 0x1 Access R/W R/W Name Reserved ILED1_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED1_SLEW [3:0] 0x0 R/W ILED1_COARSE [15:14] 13 0x0 0x1 R/W R/W Reserved ILED2_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED2_SLEW [3:0] 0x0 R/W ILED2_COARSE Description Write 0x0. LEDX1 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX1 driver in low power mode. LEDX1 Current Scale = 0.4 + 0.6 × (Register 0x23, Bit 13). Write 0x1. Write 0x0. LEDX1 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0: the slowest slew rate. … 7: the fastest slew rate. LEDX1 coarse current setting. Coarse current sink target value of LEDX1 in standard operation. 0x0: lowest coarse setting. … 0xF: highest coarse setting. LED1PEAK = LED1COARSE × LED1FINE × LED1SCALE where: LED1PEAK is the LEDX1 peak target value (mA). LED1COARSE = 50.3 + 19.8 × (Register 0x23, Bits[3:0]). LED1FINE = 0.74 + 0.022 × (Register 0x25, Bits[4:0]). LED1SCALE = 0.4 + 0.6 × (Register 0x23, Bit 13). Write 0x0. LEDX2 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX2 driver in low power mode. LED2 Current Scale = 0.4 + 0.6 × (Register 0x24, Bit 13) Write 0x1. Write 0x0. LEDX2 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0: the slowest slew rate. … 7: the fastest slew rate. LEDX2 coarse current setting. Coarse current sink target value of LEDX2 in standard operation. 0x0: lowest coarse setting. … 0xF: highest coarse setting. LED2PEAK = LED2COARSE × LED2FINE × LED2SCALE where: LED2PEAK is the LEDX2 peak target value (mA). LED2COARSE = 50.3 + 19.8 × (Register 0x24, Bits[3:0]). LED2FINE = 0.74 + 0.022 × (Register 0x25, Bits[10:6]). LED2SCALE = 0.4 + 0.6 × (Register 0x24, Bit 13). Rev. A | Page 53 of 66 ADPD105/ADPD106/ADPD107 Address 0x25 0x30 0x31 0x34 0x35 0x36 Data Sheet Data Bit [15:11] Default Value 0xC Access R/W Name ILED3_FINE [10:6] 0xC R/W ILED2_FINE 5 [4:0] 0x0 0xC R/W R/W Reserved ILED1_FINE [15:13] [12:8] [7:0] [15:8] 0x0 0x3 0x20 0x08 R/W R/W R/W R/W Reserved SLOTA_LED_WIDTH SLOTA_LED_OFFSET SLOTA_LED_NUMBER [7:0] [15:10] 9 0x18 0x00 0x0 R/W R/W R/W SLOTA_LED_PERIOD Reserved SLOTB_LED_DIS 8 0x0 R/W SLOTA_LED_DIS [7:0] [15:13] [12:8] [7:0] [15:8] 0x00 0x0 0x3 0x20 0x08 R/W R/W R/W Reserved Reserved SLOTB_LED_WIDTH SLOTB_LED_OFFSET SLOTB_LED_NUMBER [7:0] 0x18 R/W SLOTB_LED_PERIOD Description LEDX3 fine adjust. Current adjust multiplier for LED3. LEDX3 fine adjust = 0.74 + 0.022 × (Register 0x25, Bits[15:11]). See Register 0x22, Bits[3:0], for the full LED3 formula. LEDX2 fine adjust. Current adjust multiplier for LED2. LEDX2 fine adjust = 0.74 + 0.022 × (Register 0x25, Bits[10:6]). See Register 0x24, Bits[3:0], for the full LED2 formula. Write 0x0. LEDX1 fine adjust. Current adjust multiplier for LED1. LEDX1 fine adjust = 0.74 + 0.022 × (Register 0x25, Bits[4:0]). See Register 0x23, Bits[3:0], for the full LED1 formula. Write 0x0. LED pulse width (in 1 μs step) for Time Slot A. LED offset width (in 1 μs step) for Time Slot A. LED Time Slot A pulse count. nA: number of LED pulses in Time Slot A. This is typically LED1. Adjust in the application. A setting of six pulses (0x06) is typical. LED Time Slot A pulse period (in 1 μs step). Write 0x0. Time Slot B LED disable. 1: disables the LED assigned to Time Slot B. Register 0x34 keeps the drivers active and prevents them from pulsing current to the LEDs. Disabling both LEDs via this register is often used to measure the dark level. Use Register 0x11 instead to enable or disable the actual time slot usage and not only the LED. Time Slot A LED disable. 1: disables the LED assigned to Time Slot A. Use Register 0x11 instead to enable or disable the actual time slot usage and not only the LED. Write 0x00. Write 0x0. LED pulse width (in 1 μs step) for Time Slot B. LED offset width (in 1 μs step) for Time Slot B. LED Time Slot B pulse count. nB: number of LED pulses in Time Slot B. This is typically LED2. A setting of six pulses (0x06) is typical. LED Time Slot B pulse period (in 1 μs step). AFE GLOBAL CONFIGURATION REGISTERS Table 30. AFE Global Configuration Registers Address 0x37 Data Bit [15:13] Default Value 0x0 Access R/W Name CH34_DISABLE [12:10] 0x0 R/W CH2_DISABLE [9:0] 0x000 R/W Reserved Rev. A | Page 54 of 66 Description Power-down options for Channel 3 and Channel 4 only. Bit 13: power down Channel 3, Channel 4 TIA op amp. Bit 14: power down Channel 3, Channel 4 BPF op amp. Bit 15: power down Channel 3, Channel 4 integrator op amp. Bit 10: power down Channel 2 TIA op amp. Bit 11: power down Channel 2 BPF op amp. Bit 12: power down Channel 2 integrator op amp. Write 0x000. Data Sheet Address 0x3C 0x54 ADPD105/ADPD106/ADPD107 Data Bit [15:14] [13:11] 10 9 Default Value 0x0 0x6 0x0 0x0 Access R/W R/W R/W R/W Name Reserved Reserved Reserved V_CATHODE [8:3] 0x00 R/W AFE_POWERDOWN [2:0] 15 0x6 0x0 R/W R/W Reserved SLOTB_SINGLE_CH_DIG_INT 14 0x0 R/W SLOTA_SINGLE_CH_DIG_INT [13:12] 0x0 R/W SLEEP_V_CATHODE [11:10] 0x0 R/W SLOTB_V_CATHODE [9:8] 0x0 R/W SLOTA_V_CATHODE 7 0x0 R/W REG54_VCAT_ENABLE [6:0] 0x20 R/W Reserved Rev. A | Page 55 of 66 Description Write 0x0. Write 0x6. Reserved. 0x0: 1.3 V (identical to anode voltage); recommended setting. 0x1: 1.8 V (reverse bias photodiode by 550 mV). This setting may add noise. AFE channels power-down select. 0x0: keeps all channels on. Bit 3: power down Channel 1 TIA op amp. Bit 4: power down Channel 1 BPF op amp. Bit 5: power down Channel 1 integrator op amp. Bit 6: power down Channel 2, Channel 3, and Channel 4 TIA op amp. Bit 7: power down Channel 2, Channel 3, and Channel 4 BPF op amp. Bit 8: power down Channel 2, Channel 3, and Channel 4 integrator op amp. Write 0x6. 0: in Time Slot B, use all four photodiode channels in parallel for digital integration (default setting for highest dynamic range). 1: in Time Slot B, use only Channel 1 for digital integration. This limits connection to PD1 or PD5. 0: in Time Slot A, use all four photodiode channels in parallel for digital integration (default setting for highest dynamic range) 1: in Time Slot A, use only Channel 1 for digital integration. This limits connection to PD1 or PD5. If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in sleep mode. The anode voltage is always set to the cathode voltage in sleep mode. 0x0: VDD (1.8 V). 0x1: 1.3 V. 0x2: 1.55 V. 0x3: 0.0 V. If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in Time Slot B operation. The anode voltage is always 1.3 V in Time Slot B mode. 0x0: VDD (1.8 V). 0x1: 1.3 V. 0x2: 1.55 V. 0x3: 0.0 V (this forward biases a diode at the input). If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in Time Slot A operation. The anode voltage is always 1.3 V in Time Slot A mode. 0x0: VDD (1.8 V). 0x1: 1.3 V. 0x2: 1.55 V. 0x3: 0.0 V (this forward biases a diode at the input). 0: use the cathode voltage settings defined by Register 0x3C, Bit 9. 1: override Register 0x3C, Bit 9 with cathode settings defined by Register 0x54, Bits[13:8]. Reserved. ADPD105/ADPD106/ADPD107 Address 0x58 0x5A Data Sheet Data Bit [15:14] 13 Default Value 0x0 0x0 Access R/W R/W Name Reserved SLOTB_DIGITAL_INT_EN 12 0x0 R/W SLOTA_DIGITAL_INT_EN [11:0] [15:8] 7 0x000 0x00 0x0 R/W R/W R/W Reserved Reserved DIG_INT_GAPMODE 6 0x0 R/W SLOTB_DIG_INT_SAMPLE_ MODE 5 0x0 R/W SLOTA_DIG_INT_SAMPLE_ MODE [4:0] 0x00 R/W Reserved Description Reserved. 0x0: Time Slot B operating in normal mode. 0x1: Time Slot B operating in digital integration mode. 0x0: Time Slot A operating in normal mode. 0x1: Time Slot A operating in digital integration mode. Reserved. Write 0x0. Digital integrate gapped mode enable. 0: no gap between negative and positive sample regions. 1: use SLOTA_AFE_FOFFSET for Time Slot A or SLOTB_AFE_ FOFFSET for Time Slot B to specify the gap in μs. Digital integrate single sample pair mode for Time Slot B. 0: double sample pair mode. 1: single sampled pair mode. Digital integrate single sample pair mode for Time Slot A. 0: double sample pair mode. 1: single sampled pair mode. Write 0x00. Table 31. AFE Configuration Registers, Time Slot A Address 0x39 0x42 Data Bit [15:11] [10:5] Default Value 0x4 0x17 Access R/W R/W Name SLOTA_AFE_WIDTH SLOTA_AFE_OFFSET [4:0] 0x1C R/W SLOTA_AFE_FOFFSET [15:8] 0x1C R/W SLOTA_AFE_MODE 7 0x0 R/W SLOTA_INT_AS_BUF 6 0x0 R/W SLOTA_TIA_IND_EN [5:4] 0x3 R/W SLOTA_TIA_VBIAS [3:2] [1:0] 0x2 0x0 R/W R/W Reserved SLOTA_TIA_GAIN Rev. A | Page 56 of 66 Description AFE integration window width (in 1 μs step) for Time Slot A. AFE integration window coarse offset (in 1 μs step) for Time Slot A. AFE integration window fine offset (in 31.25 ns step) for Time Slot A. 0x1C: Time Slot A AFE setting for normal mode. All four blocks of the signal chain are in use during normal mode (the TIA, the BPF, followed by the integrator, and finally the ADC). 0x1D: Time Slot A AFE setting for digital integrate mode. 0: normal integrator configuration. 1: converts integrator to buffer amplifier (this is done automatically in digital integrate mode). Enable Time Slot A TIA gain individual settings. When it is enabled, the Channel 1 TIA gain is set via Register 0x42, Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set via Register 0x55, Bits[5:0]. 0: disable TIA gain individual setting. 1: enable TIA gain individual setting. Set VBIAS of the TIA for Time Slot A. 0: 1.14 V. 1: 1.01 V. 2: 0.90 V. 3: 1.27 V (default recommended). Reserved. Write 0x1. Transimpedance amplifier gain for Time Slot A. When SLOTA_TIA_IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When SLOTA_TIA_IND_EN is disabled, it is for all four Time Slot A channel TIA gain settings. 0: 200 kΩ. 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. Data Sheet ADPD105/ADPD106/ADPD107 Address 0x43 Data Bit [15:0] Default Value 0xADA5 Access R/W Name SLOTA_AFE_CFG 0x55 [15:13] 0x0 R/W DIGINT_POWER [12] [11:10] 0x0 0x0 R/W R/W Reserved SLOTB_TIA_GAIN_4 [9:8] 0x0 R/W SLOTB_TIA_GAIN_3 [7:6] 0x0 R/W SLOTB_TIA_GAIN_2 [5:4] 0x0 R/W SLOTA_TIA_GAIN_4 [3:2] 0x0 R/W SLOTA_TIA_GAIN_3 [1:0] 0x0 R/W SLOTA_TIA_GAIN_2 [15:8] [7] 0x00 0x0 R/W R/W Reserved DIG_INT_GAPMODE [6] 0x0 R/W SLOTB_DIG_INT_SAMPLEMODE [5] 0x0 R/W SLOTA_DIG_INT_SAMPLEMODE [4:0] 0x00 R/W Reserved 0x5A Rev. A | Page 57 of 66 Description AFE connection in Time Slot A. 0xADA5: analog full path mode (TIA_BPF_INT_ADC). 0xAE65: TIA ADC mode (if Register 0x42, Bit 7 = 1). 0xB065: TIA ADC mode (if Register 0x42, Bit 7 = 0). 0xAE65: digital integration mode. Others: reserved. Power-down for Channel 2, Channel 3, and Channel 4 in digital integration mode. 0: keep all channels powered up. 7: powers down Channel 2, Channel 3, and Channel 4. Write 0x0. TIA gain for Time Slot B, Channel 4 (PD4). 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. TIA gain for Time Slot B, Channel 3 (PD3). 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. TIA gain for Time Slot B, Channel 2 (PD2). 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. TIA gain for Time Slot A, Channel 4 (PD4). 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. TIA gain for Time Slot A, Channel 3 (PD3). 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. TIA gain for Time Slot A, Channel 2 (PD2). 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. Write 0x0. Digital integration gapped mode enable. 0: no gap between negative and positive sample regions. 1: use SLOTA_AFE_FOFFSET for Time Slot A or SLOTB_AFE_ FOFFSET for Time Slot B to specify the gap in μs. Digital integration single-sample pair mode for Time Slot B. 0: double-sample pair mode. 1: single-sampled pair mode. Digital integration single-sample pair mode for Time Slot A. 0: double-sample pair mode. 1: single-sampled pair mode. Write 0x0. ADPD105/ADPD106/ADPD107 Data Sheet Table 32. AFE Configuration Registers, Time Slot B Data Bit [15:11] [10:5] Default Value 0x04 0x17 Access R/W R/W Name SLOTB_AFE_WIDTH SLOTB_AFE_OFFSET [4:0] 0x1C R/W SLOTB_AFE_FOFFSET [15:8] 0x1C R/W SLOTB_AFE_MODE 7 0x0 R/W SLOTB_INT_AS_BUF 6 0x0 R/W SLOTB_TIA_IND_EN [5:4] 0x3 R/W SLOTB_TIA_VBIAS [3:2] [1:0] 0x2 0x0 R/W R/W Reserved SLOTB_TIA_GAIN 0x45 [15:0] 0xADA5 R/W SLOTB_AFE_CFG 0x58 [15:14] 13 0x0 0x0 R/W R/W Reserved SLOTB_DIGITAL_INT_EN 12 0x0 R/W SLOTA_DIGITAL_INT_EN [11:0] 0x0000 R/W Reserved Address 0x3B 0x44 Rev. A | Page 58 of 66 Description AFE integration window width (in 1 μs step) for Time Slot B. AFE integration window coarse offset (in 1 μs step) for Time Slot B. AFE integration window fine offset (in 31.25 ns step) for Time Slot B. 0x1C: Time Slot B AFE setting for normal mode (TIA_BPF_INT_ADC). 0x1D: Time Slot B AFE setting for digital integrate mode. 0: normal integrator configuration. 1: convert integrator to buffer amplifier (this is done automatically in digital integrate mode). Enable Time Slot B TIA gain individual settings. When it is enabled, the Channel 1 TIA gain is set via Register 0x44, Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set via Register 0x55, Bits[11:6]. 0: disable TIA gain individual setting. 1: enable TIA gain individual setting. Set VBIAS of the TIA for Time Slot B. 0: 1.14 V. 1: 1.01 V. 2: 0.90 V. 3: 1.27 V (default recommended). Write 0x1. Transimpedance amplifier gain for Time Slot B. When SLOTB_TIA_IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When SLOTB_TIA_IND_EN is disabled, it is for all four Time Slot B channel TIA gain settings. 0: 200 kΩ. 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. AFE connection in Time Slot B. 0xADA5: analog full path mode (TIA_BPF_INT_ADC). 0xAE65: TIA ADC mode (if Register 0x44, Bit 7 = 1). 0xB065: TIA ADC mode (if Register 0x44, Bit 7 = 0). 0xAE65: digital integration mode. Others: reserved. Write 0x0. Digital integration mode, enable Time Slot B. 0: disable. 1: enable. Digital integration mode, enable Time Slot A. 0: disable. 1: enable. Write 0x0000. Data Sheet ADPD105/ADPD106/ADPD107 SYSTEM REGISTERS Table 33. System Registers Address 0x00 0x01 0x02 Data Bit [15:8] Default 0x00 Access R/W Name FIFO_SAMPLES 7 6 0x0 0x0 R/W R/W Reserved SLOTB_INT 5 0x0 R/W SLOTA_INT [4:0] [15:9] 8 0x00 0x00 0x1 R/W R/W R/W Reserved Reserved FIFO_INT_MASK 7 6 0x1 0x1 R/W R/W Reserved SLOTB_INT_MASK 5 0x1 R/W SLOTA_INT_MASK [4:0] [15:10] 9 0x1F 0x00 0x0 R/W R/W R/W Reserved Reserved GPIO1_DRV 8 0x0 R/W GPIO1_POL [7:3] 2 0x00 0x0 R/W R/W Reserved GPIO0_ENA 1 0x0 R/W GPIO0_DRV 0 0x0 R/W GPIO0_POL Description FIFO status. Number of available bytes to be read from the FIFO. When comparing this to the FIFO length threshold (Register 0x06, Bits[13:8]), note that the FIFO status value is in bytes and the FIFO length threshold is in words, where one word = two bytes. Write 1 to Bit 15 to clear the contents of the FIFO. Write 0x1 to clear this bit to 0x0. Time Slot B interrupt. Describes the type of interrupt event. A 1 indicates an interrupt of a particular event type has occurred. Write a 1 to clear the corresponding interrupt. After clearing, the register goes to 0. Writing a 0 to this register has no effect. Time Slot A interrupt. Describes the type of interrupt event. A 1 indicates an interrupt of a particular event type has occurred. Write a 1 to clear the corresponding interrupt. After clearing, the register goes to 0. Writing a 0 to this register has no effect Write 0x1F to clear these bits to 0x00. Write 0x00. Sends an interrupt when the FIFO data length has exceeded the FIFO length threshold in Register 0x06, Bits[13:8]. A 0 enables the interrupt. Write 0x1. Sends an interrupt on the Time Slot B sample. Write a 1 to disable the interrupt. Write a 0 to enable the interrupt. Sends an interrupt on the Time Slot A sample. Write a 1 to disable the interrupt. Write a 0 to enable the interrupt. Write 0x1F. Write 0x0000. GPIO1 drive. 0: the GPIO1 pin is always driven. 1: the GPIO1 pin is driven when the interrupt is asserted; otherwise, it is left floating and requires a pull-up or pull-down resistor, depending on polarity (operates as open drain). Use this setting if multiple devices must share the GPIO1 pin. GPIO1 polarity. 0: the GPIO1 pin is active high. 1: the GPIO1 pin is active low. Write 0x00 GPIO0 pin enable. 0: disable the GPIO0 pin. The GPIO0 pin floats, regardless of interrupt status. The status register (Address 0x00) remains active. 1: enable the GPIO0 pin. GPIO0 drive. 0: the GPIO0 pin is always driven. 1: the GPIO0 pin is driven when the interrupt is asserted; otherwise, it is left floating and requires a pull-up or pull-down resistor, depending on polarity (operates as open drain). Use this setting if multiple devices must share the GPIO0 pin. GPIO0 polarity. 0: the GPIO0 pin is active high. 1: the GPIO0 pin is active low. Rev. A | Page 59 of 66 ADPD105/ADPD106/ADPD107 Address 0x06 0x08 0x09 0x0A 0x0B Data Sheet Data Bit [15:14] [13:8] Default 0x0 0x00 Access R/W R/W Name Reserved FIFO_THRESH [7:0] [15:8] [7:0] [15:8] [7:1] 0 [15:12] [11:0] 0x00 0x04 0x16 0x00 0x64 0x0 0x0 0x000 R/W R R W R/W R R R Reserved REV_NUM DEV_ID ADDRESS_WRITE_KEY SLAVE_ADDRESS Reserved Reserved CLK_RATIO [15:13] [12:8] 0x0 0x00 R/W R/W Reserved GPIO1_ALT_CFG [7:5] [4:0] 0x0 0x00 R/W R/W Reserved GPIO0_ALT_CFG Description Write 0x0. FIFO length threshold. An interrupt is generated when the number of data-words in the FIFO exceeds the value in FIFO_THRESH. The interrupt pin automatically deasserts when the number of data-words available in the FIFO no longer exceeds the value in FIFO_THRESH. Write 0x00. Revision number. Device ID. Write 0xAD when writing to SLAVE_ADDRESS. Otherwise, do not access. I2C slave address. Do not access. Write 0x0. When the CLK32M_CAL_EN bit (Register 0x50, Bit 5) is set, the device calculates the number of 32 MHz clock cycles in two cycles of the 32 kHz clock. The result, nominally 2000 (0x07D0), is stored in the CLK_RATIO bits. Write 0x0. Alternate configuration for the GPIO1 pin. 0x0: GPIO1 is backward compatible to the ADPD103 PDSO pin functionality. 0x1: interrupt function provided on GPIO1, as defined in Register 0x01. 0x2: asserts at the start of the first time slot, deasserts at end of last time slot. 0x5: Time Slot A pulse output. 0x6: Time Slot B pulse output. 0x7: pulse output of both time slots. 0xC: output data cycle occurred for Time Slot A. 0xD: output data cycle occurred for Time Slot B. 0xE: output data cycle occurred. 0xF: toggles on every sample, which provides a signal at half the sampling rate. 0x10: ouput = 0 0x11: output = 1 0x13: 32 kHz oscillator output. Remaining settings are not supported. Write 0x0. Alternate configuration for the GPIO0 pin. 0x0: GPIO0 is backward compatible to the ADPD103 INT pin functionality. 0x1: interrupt function provided on GPIO0, as defined in Register 0x01. 0x2: asserts at the start of the first time slot, deasserts at end of last time slot. 0x5: Time Slot A pulse output. 0x6: Time Slot B pulse output. 0x7: pulse output of both time slots. 0xC: output data cycle occurred for Time Slot A. 0xD: output data cycle occurred for Time Slot B. 0xE: output data cycle occurred. 0xF: toggles on every sample, which provides a signal at half the sampling rate. 0x10: output = 0. 0x11: output = 1. 0x13: 32 kHz oscillator output. Remaining settings are not supported. Rev. A | Page 60 of 66 Data Sheet ADPD105/ADPD106/ADPD107 Data Bit [15:0] Default 0x0000 Access R/W Name SLAVE_ADDRESS_KEY 0x0F [15:1] 0 0x0000 0x0 R R/W Reserved SW_RESET 0x10 [15:2] [1:0] 0x0000 0x0 R/W R/W Reserved Mode 0x11 [15:14] 13 0x0 0x0 R/W R/W Reserved RDOUT_MODE 12 0x1 R/W FIFO_OVRN_PREVENT [11:9] [8:6] 0x0 0x0 R/W R/W Reserved SLOTB_FIFO_MODE 5 [4:2] 0x0 0x0 R/W R/W SLOTB_EN SLOTA_FIFO_MODE 1 0 0x0 0x0 R/W R/W Reserved SLOTA_EN Address 0x0D Description Enable changing the I2C address using Register 0x09. 0x04AD: enable address change always. 0x44AD: enable address change if GPIO0 is high. 0x84AD: enable address change if GPIO1 is high. 0xC4AD: enable address change if both GPIO0 and GPIO1 are high. Write 0x0000. Software reset. Write 0x1 to reset the device. This bit clears itself after a reset. For I2C communications, this command returns an acknowledge and the device subsequently returns to standby mode with all registers reset to the default state. Write 0x000. Determines the operating mode of the ADPD105/ADPD106/ADPD107. 0x0: standby. 0x1: program. 0x2: normal operation. Reserved. Readback data mode for extended data registers. 0x0: block sum of N samples. 0x1: block average of N samples. 0x0: wrap around FIFO, overwriting old data with new. 0x1: new data if FIFO is not full (recommended setting). Reserved. Time Slot B FIFO data format. 0: no data to FIFO. 1: 16-bit sample in digital integration mode or 16-bit sum of all four channels when not in digital integration mode. 2: 32-bit sample in digital integration mode or 32-bit sum of all four channels when not in digital integration mode. 3: 16-bit sample and 16-bit background value in digital integration mode. 4: 32-bit sample and 32-bit background value in digital integration mode or four channels of 16-bit sample data for Time Slot B when not in digital integration mode. 6: four channels of 32-bit extended sample data for Time Slot B when not in digital integration mode. Others: reserved. The selected Time Slot B data is saved in the FIFO. Available only if Time Slot A has the same averaging factor, N (Register 0x15, Bits[10:8] = Bits[6:4]), or if Time Slot A is not saving data to the FIFO (Register 0x11, Bits[4:2] = 0). Time Slot B enable. 1: enables Time Slot B. Time Slot A FIFO data format. 0: no data to FIFO. 1: 16-bit sample in digital integration mode or 16-bit sum of all four channels when not in digital integration mode. 2: 32-bit sample in digital integration mode or 32-bit sum of all four channels when not in digital integration mode. 3: 16-bit sample and 16-bit background value in digital integration mode. 4: 32-bit sample and 32-bit background value in digital integration mode or four channels of 16-bit sample data for Time Slot B when not in digital integration mode. 6: four channels of 32-bit extended sample data for Time Slot B when not in digital integration mode. Others: reserved. Write 0x0. Time Slot A enable. 1: enables Time Slot A. Rev. A | Page 61 of 66 ADPD105/ADPD106/ADPD107 Data Sheet Data Bit [15:0] [15:9] 8 Default 0x0000 0x13 0x0 Access R/W R/W R/W Name EXT_SYNC_STARTUP Reserved CLK32K_BYP 7 0x0 R/W CLK32K_EN 6 [5:0] 0x0 0x12 R/W R/W Reserved CLK32K_ADJUST 0x4D [15:8] [7:0] 0x00 0x98 R/W R/W Reserved CLK32M_ADJUST 0x4E1 [15:0] 0x0060 R/W ADC_TIMING1 0x4F [15:8] 7 6 5 4 [3:2] 0x20 0x1 0x0 0x0 0x1 0x0 R/W R/W R/W R/W R/W R/W Reserved Reserved GPIO1_OE GPIO1_IE Reserved EXT_SYNC_SEL 1 0 [15:7] 6 0x0 0x0 0x000 0x0 R/W R/W R/W R/W GPIO0_IE Reserved Reserved GPIO1_CTRL 5 0x0 R/W CLK32M_CAL_EN [4:0] 0x00 R/W Reserved Address 0x38 0x4B 0x50 Description Write 0x4000 when EXT_SYNC_SEL is b01 or b10. Otherwise, write 0x0. Write 0x26. Bypass internal 32 kHz oscillator. 0x0: normal operation. 0x1: provide external clock on the GPIO1 pin. The user must set Register 0x4F, Bits[6:5] = 01 to enable the GPIO1 pin as an input. Sample clock power-up. Enables the data sample clock. 0x0: clock disabled. 0x1: normal operation. Write 0x0. Data sampling (32 kHz) clock frequency adjust. This register is used to calibrate the sample frequency of the device to achieve high precision on the data rate as defined in Register 0x12. Adjusts the sample master 32 kHz clock by 0.6 kHz per LSB. For a 100 Hz sample rate as defined in Register 0x12, 1 LSB of Register 0x4B, Bits[5:0], is 1.9 Hz. Note that a larger value produces a lower frequency. See the Clocks and Timing Calibration section for more information regarding clock adjustment. 00 0000: maximum frequency. 10 0010: typical center frequency. 11 1111: minimum frequency. Write 0x00. Internal timing (32 MHz) clock frequency adjust. This register is used to calibrate the internal clock of the device to achieve precisely timed LED pulses. Adjusts the 32 MHz clock by 109 kHz per LSB. See the Clocks and Timing Calibration section for more information regarding clock adjustment. 0000 0000: minimum frequency. 1001 1000: default frequency. 1111 1111: maximum frequency. 0x0040: ADC clock speed = 1 MHz. 0x0060: ADC clock speed = 500 kHz. Write 0x20. Write 0x1. GPIO1 pin output enable. GPIO1 pin input enable. Write 0x1. Sample sync select. 00: use the internal 32 kHz clock with FSAMPLE to select sample timings. 01: use the GPIO0 pin to trigger sample cycle. 10: use the GPIO1 pin to trigger sample cycle. 11: reserved. GPIO0 pin input enable. Write 0x0. Write 0x000. Controls the GPIO1 output when the GPIO1 output is enabled (GPIO1_OE = 0x1). 0x0: GPIO1 output driven low. 0x1: GPIO1 output driven by the AFE power-down signal. As part of the 32 MHz clock calibration routine, write 1 to begin the clock ratio calculation. Read the result of this calculation from the CLK_RATIO bits in Register 0x0A. Reset this bit to 0 prior to reinitiating the calculation. Write 0x0. Rev. A | Page 62 of 66 Data Sheet Address 0x5F 1 ADPD105/ADPD106/ADPD107 Data Bit [15:3] 2 Default 0x0000 0x0 Access R/W R/W Name Reserved SLOTB_DATA_HOLD 1 0x0 R/W SLOTA_DATA_HOLD 0 0x0 R/W DIGITAL_CLOCK_ENA Description Write 0x0000. Setting this bit prevents the update of the data registers corresponding to Time Slot B. Set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: hold data registers for Time Slot B. 0: allow data register update. Setting this bit prevents the update of the data registers corresponding to Time Slot A. Set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: hold data registers for Time Slot A. 0: allow data register update. Set to 1 in order to enable the 32 MHz clock when calibrating the 32 MHz clock. Always disable the 32 MHz clock following the calibration by resetting this bit to 0. Clock speed setting is only relevant during digital integrate mode. ADC REGISTERS Table 34. ADC Registers Data Bits [15:0] Default 0x0028 Access R/W Name FSAMPLE [15:11] [10:8] 0x00 0x6 R/W R/W Reserved SLOTB_NUM_AVG 7 [6:4] 0x0 0x0 R/W R/W Reserved SLOTA_NUM_AVG 0x18 [3:0] [15:0] 0x0 0x2000 R/W R/W Reserved SLOTA_CH1_OFFSET 0x19 [15:0] 0x2000 R/W SLOTA_CH2_OFFSET 0x1A [15:0] 0x2000 R/W SLOTA_CH3_OFFSET 0x1B [15:0] 0x2000 R/W SLOTA_CH4_OFFSET 0x1E [15:0] 0x2000 R/W SLOTB_CH1_OFFSET Address 0x12 0x15 Description Sampling frequency: fSAMPLE = 32 kHz/(Register 0x12, Bits[15:0] × 4). For example, 100 Hz = 0x0050; 200 Hz = 0x0028. Write 0x0. Sample sum/average for Time Slot B. Specifies the averaging factor, NB, which is the number of consecutive samples that is summed and averaged after the ADC. Register 0x70 to Register 0x7F hold the data sum. Register 0x64 to Register 0x6B and the data buffer in Register 0x60 hold the data average, which can be used to increase SNR without clipping, in 16-bit registers. The data rate is decimated by the value of the SLOTB_NUMB_AVG bits. 0: 1. 1: 2. 2: 4. 3: 8. 4: 16. 5: 32. 6: 64. 7: 128. Write 0x0. Sample sum/average for Time Slot A. NA: same as Bits[10:8] but for Time Slot A. See description in Register 0x15, Bits[10:8]. Write 0x0. Time Slot A Channel 1 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 2 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 3 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 4 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 1 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Rev. A | Page 63 of 66 ADPD105/ADPD106/ADPD107 Data Sheet Address 0x1F Data Bits [15:0] Default 0x2000 Access R/W Name SLOTB_CH2_OFFSET 0x20 [15:0] 0x2000 R/W SLOTB_CH3_OFFSET 0x21 [15:0] 0x2000 R/W SLOTB_CH4_OFFSET Description Time Slot B Channel 2 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 3 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 4 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. DATA REGISTERS Table 35. Data Registers Address 0x60 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F Data Bits [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Access R R R R R R R R R R R R R R R R R R R R R R R R R Name FIFO_DATA SLOTA_CH1_16BIT SLOTA_CH2_16BIT SLOTA_CH3_16BIT SLOTA_CH4_16BIT SLOTB_CH1_16BIT SLOTB_CH2_16BIT SLOTB_CH3_16BIT SLOTB_CH4_16BIT SLOTA_CH1_LOW SLOTA_CH2_LOW SLOTA_CH3_LOW SLOTA_CH4_LOW SLOTA_CH1_HIGH SLOTA_CH2_HIGH SLOTA_CH3_HIGH SLOTA_CH4_HIGH SLOTB_CH1_LOW SLOTB_CH2_LOW SLOTB_CH3_LOW SLOTB_CH4_LOW SLOTB_CH1_HIGH SLOTB_CH2_HIGH SLOTB_CH3_HIGH SLOTB_CH4_HIGH Description Next available word in FIFO. 16-bit value of Channel1 in Time Slot A. 16-bit value of Channel 2 in Time Slot A. 16-bit value of Channel 3 in Time Slot A. 16-bit value of Channel 4 in Time Slot A. 16-bit value of Channel 1 in Time Slot B. 16-bit value of Channel 2 in Time Slot B. 16-bit value of Channel 3 in Time Slot B. 16-bit value of Channel 4 in Time Slot B. Low data-word for Channel 1 in Time Slot A. Low data-word for Channel 2 in Time Slot A. Low data-word for Channel 3 in Time Slot A. Low data-word for Channel 4 in Time Slot A. High data-word for Channel 1 in Time Slot A. High data-word for Channel 2 in Time Slot A. High data-word for Channel 3 in Time Slot A. High data-word for Channel 4 in Time Slot A. Low data-word for Channel 1 in Time Slot B. Low data-word for Channel 2 in Time Slot B. Low data-word for Channel 3 in Time Slot B. Low data-word for Channel 4 in Time Slot B. High data-word for Channel 1 in Time Slot B. High data-word for Channel 2 in Time Slot B. High data-word for Channel 3 in Time Slot B. High data-word for Channel 4 in Time Slot B. 2. 3. REQUIRED START-UP LOAD PROCEDURE The required start-up load procedure is as follows: 1. Write to 0x1 to Register 0x4B, Bit 7 to enable the clock that drives the state machine. 4. Rev. A | Page 64 of 66 Write 0x0001 to Register 0x10 to enter program mode. Write to the other registers; the register order is not important while the device is in program mode. Write 0x0002 to Register 0x10 to start normal sampling operation. Data Sheet ADPD105/ADPD106/ADPD107 OUTLINE DIMENSIONS 0.25 0.20 0.15 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 22 0.40 BSC PIN 1 INDICATOR 28 1 21 2.70 2.60 SQ 2.50 EXPOSED PAD 7 15 TOP VIEW 0.80 0.75 0.70 14 8 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PKG-003523 SEATING PLANE 0.20 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 06-23-2015-B 0.45 0.40 0.35 COMPLIANT TO JEDEC STANDARDS MO-220-WGGE. Figure 54. 28-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-28-5) Dimensions shown in millimeters 1.44 1.40 1.36 0.225 3 2 1 A BALL A1 IDENTIFIER B 2.00 REF 2.50 2.46 2.42 C D 0.40 BSC E F TOP VIEW 0.235 0.300 (BALL SIDE DOWN) PKG-004659 SEATING PLANE (BALL SIDE UP) 0.330 0.300 0.270 END VIEW COPLANARITY 0.05 0.300 0.260 0.220 0.230 0.200 0.170 Figure 55. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-18) Dimensions shown in millimeters Rev. A | Page 65 of 66 02-03-2015-B 0.560 0.500 0.440 BOTTOM VIEW ADPD105/ADPD106/ADPD107 Data Sheet 1.44 1.40 1.36 3 2 1 A BALL A1 IDENTIFIER B 2.00 REF 2.50 2.46 2.42 C D 0.40 BSC E F BOTTOM VIEW (BALL SIDE DOWN) (BALL SIDE UP) 0.80 REF 0.330 0.300 0.270 END VIEW COPLANARITY 0.05 SEATING PLANE PKG-005139 0.300 0.260 0.220 0.230 0.200 0.170 03-03-2016-A 0.560 0.500 0.440 TOP VIEW Figure 56. 17-Ball Wafer Level Chip Scale Package [WLCSP] (CB-17-1) Dimensions shown in millimeters ORDERING GUIDE Model1 ADPD105BCPZ ADPD105BCPZRL ADPD105BCBZR7 ADPD106BCBZR7 ADPD107BCBZR7 EVAL-ADPD105Z-GEN 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 28-Lead Lead Frame Chip Scale Package [LFCSP] 28-Lead Lead Frame Chip Scale Package [LFCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] 17-Ball Wafer Level Chip Scale Package [WLCSP] Generic ADPD105 Evaluation Board2 Z = RoHS Compliant Part. This evaluation board is used for the ADPD105, ADPD106, and ADPD107. ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14693-0-1/17(A) Rev. A | Page 66 of 66 Package Option CP-28-5 CP-28-5 CB-16-18 CB-16-18 CB-17-1