Wideband Quadrature Modulator with
Integrated Fractional-N PLL and VCOs
ADRF6720-27
Data Sheet
FEATURES
GENERAL DESCRIPTION
I/Q modulator with integrated fractional-N PLL
RF output frequency range: 400 MHz to 3000 MHz
Internal LO frequency range: 356.25 MHz to 2855 MHz
Output P1dB: 10.8 dBm at 2140 MHz
Output IP3: 31.1 dBm at 2140 MHz
Carrier feedthrough: −44.3 dBm at 2140 MHz
Sideband suppression: −40.8 dBc at 2140 MHz
Noise floor: −159.5 dBm/Hz at 2140 MHz
Baseband 1 dB modulation bandwidth: >1000 MHz
Baseband input bias level: 2.68 V
Power supply: 3.3 V/425 mA
Integrated RF tunable balun allowing single-ended RF output
Multicore integrated VCOs
HD3/IP3 optimization
Sideband suppression and carrier feedthrough optimization
High-side/low-side LO injection
Programmable via 3-wire serial port interface (SPI)
40-lead 6 mm × 6 mm LFCSP
The ADRF6720-27 is a wideband quadrature modulator with an
integrated synthesizer ideally suited for 3G and 4G communication systems. The ADRF6720-27 consists of a high
linearity broadband modulator, an integrated fractional-N
phase-locked loop (PLL), and four low phase noise multicore
voltage controlled oscillators (VCOs).
The ADRF6720-27 local oscillator (LO) signal can be generated
internally via the on-chip integer-N and fractional-N synthesizers,
or externally via a high frequency, low phase noise LO signal.
The internal integrated synthesizer enables LO coverage from
356.25 MHz to 2855 MHz using the multicore VCOs. In the
case of internal LO generation or external LO input, quadrature
signals are generated with a divide by 2 phase splitter. When the
ADRF6720-27 is operated with an external 1 × LO input, a
polyphase filter generates the quadrature inputs to the mixer.
The ADRF6720-27 offers digital programmability for carrier
feedthrough optimization, sideband suppression, HD3/IP3
optimization, and high-side or low-side LO injection.
APPLICATIONS
The ADRF6720-27 is fabricated using an advanced silicongermanium BiCMOS process. It is available in a 40-lead,
RoHS-compliant, 6 mm × 6 mm LFCSP package with an
exposed pad. Performance is specified over the −40°C to +85°C
temperature range.
2G/3G/4G/LTE broadband communication systems
Microwave point-to-point radios
Satellite modems
Military/aerospace
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
VPOSx
40
30
26
22
17
11
6
3
ADRF6720-27
V TO I
I–
4
LO NULLING
DAC
LO NULLING
DAC
Q–
8
27
ENBL
24
RFOUT
18
LOOUT+
19
LOOUT–
15
CS
14
SCLK
13
SDIO
PHASE
CORRECTION
PHASE
CORRECTION
V TO I
Q+
9
REFIN
39
CP
36
VTUNE
32
LOIN–
33
LOIN+
34
PLL
QUAD
DIVIDER
POLYPHASE
FILTER
2
5
7 10 16 20 23 25 29 37 38
LDO
2.5V
LDO
VCO
12
28
DECL1
DECL2
SERIAL
PORT
INTERFACE
31
DECL3
GND
12488-001
I+
35
Figure 1.
Rev. B
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ADRF6720-27
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
LO Input ...................................................................................... 24
Applications ....................................................................................... 1
Loop Filter ................................................................................... 24
General Description ......................................................................... 1
RF Output .................................................................................... 24
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 25
Revision History ............................................................................... 2
DAC to I/Q Modulator Interfacing .......................................... 25
Specifications..................................................................................... 3
Baseband Bandwidth ................................................................. 26
Timing Characteristics ................................................................ 7
Carrier Feedthrough Nulling .................................................... 26
Absolute Maximum Ratings............................................................ 8
Sideband Suppression Optimization ....................................... 26
Thermal Resistance ...................................................................... 8
Linearity....................................................................................... 27
ESD Caution .................................................................................. 8
LO Amplitude and Common-Mode Voltage.......................... 27
Pin Configuration and Function Descriptions ............................. 9
Operating Out of Frequency Range ......................................... 28
Typical Performance Characteristics ........................................... 11
Spurious Performance ............................................................... 28
Theory of Operation ...................................................................... 18
Layout .......................................................................................... 29
LO Generation Block ................................................................. 18
Characterization Setups ................................................................. 30
Baseband ...................................................................................... 21
Register Map ................................................................................... 32
Active Mixers .............................................................................. 21
Register Details ............................................................................... 33
Serial Port Interface .................................................................... 22
Outline Dimensions ....................................................................... 43
Basic Connections for Operation ................................................. 23
Ordering Guide .......................................................................... 43
Power Supply and Grounding ................................................... 23
Baseband Inputs.......................................................................... 24
REVISION HISTORY
9/15—Rev. A to Rev. B
Changed RFOUT = 4 dBm to RFOUT ≈ 4 dBm, and USB to
Sideband Suppression ................................................... Throughout
Changes to Spurious Performance Section and Figure 59 ........ 28
Changes to Figure 60 ...................................................................... 29
3/15—Rev. 0 to Rev. A
Added Spurious Performance Section and Figure 57 to
Figure 59; Renumbered Sequentially ........................................... 28
Added Figure 60 ............................................................................. 29
10/14—Revision 0: Initial Version
Rev. B | Page 2 of 43
Data Sheet
ADRF6720-27
SPECIFICATIONS
VPOSx = 3.3 V, TA = 25°C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 2.68 V dc bias, unless otherwise noted.
Table 1.
Parameter
OPERATING FREQUENCY RANGE
RF OUTPUT = 460 MHz
Output Power, POUT
Modulator Voltage Gain
Output P1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
RF OUTPUT = 940 MHz
Output Power, POUT
Modulator Voltage Gain
Output P1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
RF OUTPUT = 1900 MHz
Output Power, POUT
Modulator Voltage Gain
Output P1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Test Conditions/Comments
RF output range
Internal LO range
External LO range
Baseband VIQ = 1 V p-p differential
POUT − P(fLO ± (2 × fBB))
POUT − P(fLO ± (3 × fBB))
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude
per tone = 0.3 V p-p differential
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude
per tone = 0.3 V p-p differential
I/Q input with 2.68 V dc bias and no RF output, 20 MHz carrier
offset
I/Q input with 2.68 V dc bias and −10 dBm RF output, 20 MHz
carrier offset
Baseband VIQ = 1 V p-p differential
POUT − P(fLO ± (2 × fBB))
POUT − P(fLO ± (3 × fBB))
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude
per tone = 0.3 V p-p differential
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude
per tone = 0.3 V p-p differential
I/Q input with 2.68 V dc bias and no RF output, 20 MHz carrier
offset
I/Q input with 2.68 V dc bias and −10 dBm RF output, 20 MHz
carrier offset
Baseband VIQ = 1 V p-p differential
POUT − P(fLO ± (2 × fBB))
POUT − P(fLO ± (3 × fBB))
Rev. B | Page 3 of 43
Min
400
356.25
400
Typ
Max
3000
2855
3000
Unit
MHz
MHz
MHz
−0.7
−4.68
6.1
−53.0
−50.2
0.18
0.023
−77.1
−61.5
58.1
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
27.2
dBm
−161.2
dBm/Hz
−160.1
dBm/Hz
5.0
1.02
11.75
−45.5
−47.3
−0.05
0.022
−69.5
−60.6
65.8
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
34.8
dBm
−158.2
dBm/Hz
−157.3
dBm/Hz
4.5
0.52
11.4
−37.5
−40.4
1.21
0.006
−65.0
−61.4
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
dBc
ADRF6720-27
Parameter
Output IP2
Output IP3
Noise Floor
RF OUTPUT = 2140 MHz
Output Power, POUT
Modulator Voltage Gain
Output P1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
RF OUTPUT = 2300 MHz
Output Power, POUT
Modulator Voltage Gain
Output P1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
RF OUTPUT = 2600 MHz
Output Power, POUT
Modulator Voltage Gain
Output P1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Data Sheet
Test Conditions/Comments
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude
per tone = 0.3 V p-p differential
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude
per tone = 0.3 V p-p differential
I/Q input with 2.68 V dc bias and no RF output, 20 MHz carrier
offset
I/Q input with 2.68 V dc bias and −10 dBm RF output, 20 MHz
carrier offset
Baseband VIQ = 1 V p-p differential
POUT − P(fLO ± (2 × fBB))
POUT − P(fLO ± (3 × fBB))
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude
per tone = 0.3 V p-p differential
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude
per tone = 0.3 V p-p differential
I/Q input with 2.68 V dc bias and no RF output, 20 MHz carrier
offset
I/Q input with 2.68 V dc bias and −10 dBm RF output, 20 MHz
carrier offset
Baseband VIQ = 1 V p-p differential
POUT − P(fLO ± (2 × fBB))
POUT − P(fLO ± (3 × fBB))
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude
per tone = 0.3 V p-p differential
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude
per tone = 0.3 V p-p differential
I/Q input with 2.68 V dc bias and no RF output, 20 MHz carrier offset
I/Q input with 2.68 V dc bias and −10 dBm RF output, 20 MHz
carrier offset
Baseband VIQ = 1 V p-p differential
POUT − P(fLO ± (2 × fBB))
POUT − P(fLO ± (3 × fBB))
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude
per tone = 0.3 V p-p differential
Rev. B | Page 4 of 43
Min
Typ
59.8
Max
Unit
dBm
32.7
dBm
−157.5
dBm/Hz
−156.6
dBm/Hz
4.0
0.02
10.8
−44.3
−40.8
−0.78
−0.015
−58.4
−67.3
58.7
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
31.1
dBm
−159.5
dBm/Hz
−158.6
dBm/Hz
3.5
−0.48
10.3
−40.8
−37.4
−1.38
−0.015
−58.8
−65.8
57.5
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
28.1
dBm
−158.6
−157.5
dBm/Hz
dBm/Hz
2.9
−1.08
9.9
−37.1
−40.7
−0.80
0.003
−61.2
−59.1
53.5
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
Data Sheet
Parameter
Output IP3
Noise Floor
SYNTHESIZER SPECIFICATIONS
Figure of Merit (FOM)1
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Amplitude
Phase Detector Frequency
MUXOUT Output Level
MUXOUT Duty Cycle
CHARGE PUMP
Charge Pump Current
Output Compliance Range
PHASE NOISE, FREQUENCY =
460 MHz, fPFD = 38.4 MHz
Integrated Phase Noise
Reference Spurs
PHASE NOISE, FREQUENCY =
940 MHz, fPFD = 38.4 MHz
Integrated Phase Noise
Reference Spurs
PHASE NOISE, FREQUENCY =
1900 MHz, fPFD = 38.4 MHz
Integrated Phase Noise
ADRF6720-27
Test Conditions/Comments
f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude
per tone = 0.3 V p-p differential
I/Q input with 2.68 V dc bias and no RF output, 20 MHz carrier
offset
I/Q input with 2.68 V dc bias and −10 dBm RF output, 20 MHz
carrier offset
Synthesizer specifications referenced to the modulator output
Min
Typ
27.9
Max
Unit
dBm
−158.6
dBm/Hz
−157.3
dBm/Hz
−218.5
dBc/Hz/Hz
REFIN, MUXOUT pins
5.7
320
4
11.4
Low (lock detect output selected)
High (lock detect output selected)
40
0.25
2.7
50
Programmable to 250 µA, 500 µA, 750 µA, or 1000 µA
1000
1
Closed-loop operation (20 kHz loop filter, see Figure 44 for loop
filter design)
10 kHz offset
100 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
20 MHz offset
1 kHz to 40 MHz integration bandwidth, with spurs
fPFD
fPFD × 2
fPFD × 3
fPFD × 4
Closed-loop operation (20 kHz loop filter, see Figure 44 for loop
filter design)
10 kHz offset
100 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
20 MHz offset
1 kHz to 40 MHz integration bandwidth, with spurs
fPFD
fPFD × 2
fPFD × 3
fPFD × 4
Closed-loop operation (20 kHz loop filter, see Figure 44 for loop
filter design)
10 kHz offset
100 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
20 MHz offset
1 kHz to 40 MHz integration bandwidth, with spurs
Rev. B | Page 5 of 43
2.8
MHz
dBm
MHz
V
V
%
µA
V
−102.1
−125.2
−144.4
−149.6
−150.8
−150.6
0.09
−97.7
−93.3
−91.5
−96.2
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
dBc
dBc
dBc
dBc
−97.9
−121.3
−144.3
−153.7
−154.3
−154.7
0.15
−99.2
−92.3
−95.2
−101.3
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
dBc
dBc
dBc
dBc
−92.2
−114.8
−139.8
−151.4
−152.8
−153.4
0.31
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
ADRF6720-27
Parameter
Reference Spurs
PHASE NOISE, FREQUENCY =
2140 MHz, fPFD = 38.4 MHz
Integrated Phase Noise
Reference Spurs
PHASE NOISE, FREQUENCY =
2300 MHz, fPFD = 38.4 MHz
Integrated Phase Noise
Reference Spurs
PHASE NOISE, FREQUENCY =
2600 MHz, fPFD = 38.4 MHz
Integrated Phase Noise
Reference Spurs
LO INPUT/OUTPUT
LO Output Frequency Range
LO Output Level
LO Input Level
LO Input Impedance
Data Sheet
Test Conditions/Comments
fPFD
fPFD × 2
fPFD × 3
fPFD × 4
Closed-loop operation (20 kHz loop filter, see Figure 44 for loop
filter design)
10 kHz offset
100 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
20 MHz offset
1 kHz to 40 MHz integration bandwidth, with spurs
fPFD
fPFD × 2
fPFD × 3
fPFD × 4
Closed-loop operation (20 kHz loop filter, see Figure 44 for loop
filter design)
10 kHz offset
100 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
20 MHz offset
1 kHz to 40 MHz integration bandwidth, with spurs
fPFD
fPFD × 2
fPFD × 3
fPFD × 4
Closed-loop operation (20 kHz loop filter, see Figure 44 for loop
filter design)
10 kHz offset
100 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
20 MHz offset
1 kHz to 40 MHz integration bandwidth, with spurs
fPFD
fPFD × 2
fPFD × 3
fPFD × 4
Min
1 × LO mode
2 × LO mode
2 × LO or 1 × LO mode, into a 50 Ω load, LO buffer enabled at
2140 MHz
LO_DRV_LVL = 0
LO_DRV_LVL = 1
LO_DRV_LVL = 2
Externally applied LO, PLL disabled
Externally applied LO, PLL disabled
356.25
712.5
Rev. B | Page 6 of 43
−6
Typ
−93.2
−86.8
−89.8
−101.7
Max
Unit
dBc
dBc
dBc
dBc
−92.9
−116.2
−140.3
−150.7
−151.8
−152.5
0.29
−91.3
−90.3
−85.6
−91.0
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
dBc
dBc
dBc
dBc
−94.6
−114.8
−139.0
−149.4
−151.1
−151.5
0.26
−96.1
−91.9
−88.2
−94.8
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
dBc
dBc
dBc
dBc
−92.4
−111.4
−137.2
−147.7
−148.9
−149.9
0.36
−95.5
−85.4
−93.4
−91.0
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
dBc
dBc
dBc
dBc
2855
5710
−5.8
−1.0
2.2
0
50
+6
MHz
MHz
dBm
dBm
dBm
dBm
Ω
Data Sheet
ADRF6720-27
Parameter
BASEBAND INPUTS
I and Q Input DC Bias Level
Bandwidth
Differential Input
Impedance
Differential Input
Capacitance
OUT ENABLE
Turn-On Settling Time
Test Conditions/Comments
I± and Q± pins
Min
DIGITAL LOGIC
Input Voltage High (VIH)
Input Voltage Low (VIL)
Input Current (IIH/IIL)
Input Capacitance (CIN)
Output Voltage High (VOH)
Output Voltage Low (VOL)
POWER SUPPLIES
Voltage Range
Supply Current
Max
Unit
1 dB
Frequency = 100 MHz2
2.68
>1000
55
V
MHz
KΩ
Frequency = 100 MHz2
0.97
pF
170
ns
10
ns
ENBL pin
ENBL low to high (90% of envelope), when Register 0x01[10] =
1, Register 0x10[10] = 1
ENBL high to low (10% of envelope), when Register 0x01[10] =
1, Register 0x10[10] = 1
SCLK, SDIO, CS, and ENBL
Turn-Off Settling Time
Typ
1.4
V
V
µA
pF
V
V
0.7
+1
−1
5
IOH = −100 µA
IOL = +100 µA
2.3
0.2
VPOSx
Tx mode at internal LO mode (PLL, internal VCO , and modulator
enabled, LO output driver disabled)
Tx mode at external 1× LO mode (PLL, internal VCO disabled,
modulator enabled, LO output driver disabled)
LO output driver; LO_DRV_LVL bits (Register 0x22[7:6]) = 10
Power-down mode
3.3
425
V
mA
218
mA
42
14.5
mA
mA
The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10log10(fPFD) − 20log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF =
153.6 MHz, fREF power = 4 dBm with a 38.4 MHz fPFD. The FOM was computed at a 50 kHz offset.
2
Refer to Figure 47 for a plot of input impedance over frequency.
1
TIMING CHARACTERISTICS
Table 2.
Parameter
tSCLK
tDS
tDH
tS
tH
tHIGH
tLOW
tACCESS
tz
Description
Serial clock period
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Setup time between falling edge of CS and SCLK
Hold time between rising edge of CS and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Maximum time delay between falling edge of SCLK and output data valid for a read operation
Maximum time delay between CS deactivation and SDIO bus return to high impedance
tHIGH
tDS
tS
Min
38
8
8
10
10
10
10
Max
13
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tH
tSCLK
tACCESS
tLOW
tDH
Typ
CS
DON'T CARE
DON'T CARE
tZ
SDIO
DON'T CARE
A6
A5
A4
A3
A2
A1
A0
R/W
D15
D14
D13
Figure 2. Serial Port Timing Diagram
Rev. B | Page 7 of 43
D3
D2
D1
D0
DON'T CARE
12488-002
SCLK
ADRF6720-27
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Supply Voltage
I+, I−, Q+, Q−
LOIN+, LOIN−
REFIN
ENBL
VTUNE
CS, SCLK, SDIO
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
θJA is thermal resistance, junction to ambient (°C/W), and θJC is
thermal resistance, junction to case (°C/W).
Rating
−0.3 V to +3.6 V
−0.5 V to +3.6 V
16 dBm differential
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
150°C
−40°C to +85°C
−65°C to +150°C
Table 4. Thermal Resistance
Package Type
40-Lead LFCSP
1
θJA1
30.23
θJC1
0.44
Unit
°C/W
See JEDEC standard JESD51-2 for information on optimizing thermal
impedance.
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 8 of 43
Data Sheet
ADRF6720-27
40
39
38
37
36
35
34
33
32
31
VPOS8
REFIN
GND
GND
CP
VPOS7
LOIN+
LOIN–
VTUNE
DECL3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADRF6720-27
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
VPOS6
GND
DECL2
ENBL
VPOS5
GND
RFOUT
GND
VPOS4
NIC
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. SOLDER THE EXPOSED PAD TO A LOW IMPEDANCE
GROUND PLANE.
12488-003
VPOS2
DECL1
SDIO
SCLK
CS
GND
VPOS3
LOOUT+
LOOUT–
GND
11
12
13
14
15
16
17
18
19
20
MUXOUT 1
GND 2
I+ 3
I– 4
GND 5
VPOS1 6
GND 7
Q– 8
Q+ 9
GND 10
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
MUXOUT
2, 10
3, 4
5, 7
6
8, 9
11
12
13
14
15
16
17
18, 19
GND
I+, I−
GND
VPOS1
Q−, Q+
VPOS2
DECL1
SDIO
SCLK
CS
GND
VPOS3
LOOUT+,
LOOUT−
GND
NIC
VPOS4
GND
RFOUT
VPOS5
ENBL
20
21
22
23, 25
24
26
27
28
29
30
31
32
33, 34
35
DECL2
GND
VPOS6
DECL3
VTUNE
LOIN−,
LOIN+
VPOS7
Description
Multiplexer Output. This output allows a digital lock detect signal, a voltage proportional to absolute temperature
(VPTAT), or a buffered, frequency-scaled reference signal to be accessed externally. The output is selected by
programming Bits[6:4] in Register 0x21.
Baseband Ground.
Differential In-Phase Baseband Inputs.
Mixer Core (I and Q) Ground.
3.3 V Supply Voltage for Baseband. Decouple VPOS1 with 100 pF and 0.1 µF capacitors located close to the pin.
Differential Quadrature Baseband Inputs.
3.3 V Supply Voltage for 2.5 V LDO. Decouple VPOS2 with 100 pF and 0.1 µF capacitors located close to the pin.
Decoupling Pin for 2.5 V LDO. Connect 100 pF, 0.1 µF, and 10 µF capacitors between this pin and ground.
Serial Data Input/Output for SPI.
Serial Clock Input/Output for SPI.
Chip Select Input/Output for SPI.
Digital Ground.
3.3 V Supply Voltage for LO. Decouple VPOS3 with 100 pF and 0.1 µF capacitors located close to the pin.
Differential LO Outputs. Either the internally generated LO or external 1 × LO/2 × LO is available at 1 × LO or 2 ×
LO on these pins.
LO Ground.
Not Internally Connected. This pin can be left open or tied to RF ground.
3.3 V Supply Voltage for RF. Decouple VPOS4 with 100 pF and 0.1 µF capacitors located close to the pin.
RF Ground.
Single-Ended 0 V DC RF Output.
3.3 V Supply Voltage for RF. Decouple VPOS5 with 100 pF and 0.1 µF capacitors located close to the pin.
Enables/Disables the Circuit Blocks. References the settings at Register 0x01 and Register 0x10. Refer to the ENBL
section for more information.
Decoupling Pin for VCO LDO. Connect 100 pF, 0.1 µF, and 10 µF capacitors between this pin and ground.
VCO Ground.
3.3 V Supply Voltage for VCO LDO. Decouple VPOS6 with 100 pF and 0.1 µF capacitors located close to the pin.
Decoupling Pin for VCO LDO. Connect 100 pF, 0.1 µF, and 10 µF capacitors between this pin and ground.
VCO Tuning Voltage.
Differential External LO Inputs.
3.3 V Supply Voltage for Charge Pump. Decouple VPOS7 with 100 pF and 0.1 µF capacitors located close to the
pin.
Rev. B | Page 9 of 43
ADRF6720-27
Pin No.
36
37
38
39
40
Mnemonic
CP
GND
GND
REFIN
VPOS8
EP
Data Sheet
Description
Charge Pump Output.
Charge Pump Ground.
PLL Reference Ground.
PLL Reference Input.
3.3 V Supply Voltage for PLL Reference. Decouple VPOS8 with 100 pF and 0.1 µF capacitors located close to the
pin.
Exposed Pad. Solder the exposed pad to a low impedance ground plane.
Rev. B | Page 10 of 43
Data Sheet
ADRF6720-27
TYPICAL PERFORMANCE CHARACTERISTICS
VPOSx = 3.3 V; TA = 25°C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 2.68 V dc bias; baseband I/Q
frequency (fBB) = 1 MHz; fPFD = 38.4 MHz; fREF = 153.6 MHz at 4 dBm referred to 50 Ω (1 V p-p); 20 kHz loop filter, unless otherwise noted.
8
6
SSB OUTPUT POWER (dBm)
4
2
0
–2
–4
–6
1900
2400
1dB OUTPUT COMPRESSION (dBm)
1dB OUTPUT COMPRESSION (dBm)
14
TA = –40°C
TA = +25°C
TA = +85°C
10
8
6
4
2
1400
1900
2400
LO FREQUENCY (MHz)
1900
2400
3.15
3.30
3.45
10
8
6
4
2
900
1400
1900
2400
Figure 8. SSB 1 dB Output Compression Point (OP1dB) vs. LO Frequency (fLO)
and Supply
0
TA = –40°C
TA = +25°C
TA = +85°C
–10
CARRIER FEEDTHROUGH (dBm)
CARRIER FEEDTHROUGH (dBm)
1400
LO FREQUENCY (MHz)
Figure 5. SSB 1 dB Output Compression Point (OP1dB) vs. LO Frequency (fLO)
and Temperature; Multiple Devices Shown
–20
–30
–40
–50
–60
–70
–80
TA = –40°C
TA = +25°C
TA = +85°C
–20
–30
–40
–50
–60
–70
–80
900
1400
1900
LO FREQUENCY (MHz)
2400
–90
400
12488-006
–90
400
12
0
400
12488-005
900
900
Figure 7. SSB Output Power (POUT) vs. LO Frequency (fLO) and Supply
12
–10
0
LO FREQUENCY (MHz)
16
0
2
–4
400
Figure 4. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO)
and Temperature; Multiple Devices Shown
0
400
4
12488-007
1400
12488-004
900
LO FREQUENCY (MHz)
14
6
–2
–8
–10
400
3.15
3.30
3.45
12488-008
SSB OUTPUT POWER (dBm)
8
10
TA = –40°C
TA = +25°C
TA = +85°C
900
1400
1900
LO FREQUENCY (MHz)
Figure 6. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature Before
Nulling; Multiple Devices Shown
2400
12488-009
10
Figure 9. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature After
Nulling Using DCOFF_I and DCOFF_Q at 25°C; Multiple Devices Shown
Rev. B | Page 11 of 43
ADRF6720-27
0
0
TA = –40°C
TA = +25°C
TA = +85°C
–20
–30
–40
–50
–60
–70
–80
–20
–30
–40
–50
–60
–70
2400
–90
400
LO FREQUENCY (MHz)
Figure 13. Sideband Suppression vs. LO Frequency (fLO) and Temperature
After Nulling Using I_LO and Q_LO at 25°C; Multiple Devices Shown
80
–20
70
THIRD-ORDER HARMONIC (dBc),
SECOND-ORDER HARMONIC (dBc)
60
50
40
30
OIP3
20
TA = –40°C
TA = +25°C
TA = +85°C
900
1400
1900
2400
LO FREQUENCY (MHz)
–30
THIRD-ORDER
DISTORTION (dBC)
–10
0
–50
–5
–10
–15
–70
–80
900
1400
1900
2400
20
SSB OUTPUT
POWER (dBm)
5
SIDEBAND
SUPPRESSION (dBC)
–70
15
–40
–60
–60
0
10
CARRIER
FEEDTHROUGH (dBm)
–50
20
SECOND-ORDER DISTORTION (dBc),
THIRD-ORDER DISTORTION (dBc),
CARRIER FEEDTHROUGH (dBm),
SIDEBAND SUPPRESSION (dBc)
–20
–40
Figure 14. Second- and Third-Order Harmonics vs. LO Frequency (fLO) and
Temperature (POUT ≈ 5 dBm)
SSB OUTPUT POWER (dBm)
SSB OUTPUT
POWER (dBm)
–10
–30
LO FREQUENCY (MHz)
Figure 11. OIP3 and OIP2 vs. LO Frequency (fLO) and Temperature (POUT ≈
−5 dBm per Tone); Multiple Devices Shown
0
TA = –40°C
TA = +25°C
TA = +85°C
SECOND HARMONIC
THIRD HARMONIC
–90
400
12488-011
OUTPUT IP3 AND IP2 (dBm)
OIP2
0
400
2400
1900
LO FREQUENCY (MHz)
Figure 10. Sideband Suppression vs. LO Frequency (fLO) and Temperature
Before Nulling; Multiple Devices Shown
10
1400
900
12488-014
1900
15
THIRD-ORDER
DISTORTION (dBc)
10
–20
SIDEBAND
SUPPRESSION (dBc)
–30
5
CARRIER
FEEDTHROUGH (dBm)
–40
0
–50
–5
–10
–60
SECOND-ORDER
DISTORTION (dBc)
SSB OUTPUT POWER (dBm)
1400
12488-010
900
12488-013
–80
–90
400
SECOND-ORDER DISTORTION (dBc),
THIRD-ORDER DISTORTION (dBc),
CARRIER FEEDTHROUGH (dBm),
SIDEBAND SUPPRESSION (dBc)
TA = –40°C
TA = +25°C
TA = +85°C
–10
SIDEBAND SUPPRESSION (dBc)
–10
SIDEBAND SUPPRESSION (dBc)
Data Sheet
–15
–70
1
–20
10
BASEBAND INPUT VOLTAGE (Vp-p Differential)
Figure 12. SSB Output Power, Second- and Third-Order Harmonics, Carrier
Feedthrough, and Sideband Suppression vs. Baseband Differential Input
Voltage (fOUT = 940 MHz)
–80
0.1
12488-012
–80
0.1
1
–20
10
BASEBAND INPUT VOLTAGE (Vp-p Differential)
Figure 15. SSB Output Power, Second- and Third-Order Harmonics, Carrier
Feedthrough, and Sideband Suppression vs. Baseband Differential Input
Voltage (fOUT = 2140 MHz)
Rev. B | Page 12 of 43
12488-015
SECOND-ORDER
DISTORTION(dBC)
Data Sheet
ADRF6720-27
–10
–20
–30
SIDEBAND
SUPPRESSION (dBc)
20
0
15
–20
10
CARRIER
FEEDTHROUGH (dBm)
5
–40
0
–50
–5
–60
–10
SECOND-ORDER
DISTORTION (dBc)
–70
TA = –40°C
TA = +25°C
TA = +85°C
–40
PHASE NOISE (dBc/Hz)
THIRD-ORDER
DISTORTION (dBc)
SSB OUTPUT
POWER (dBm)
SSB OUTPUT POWER (dBm)
SECOND-ORDER DISTORTION (dBc),
THIRD-ORDER DISTORTION (dBc),
CARRIER FEEDTHROUGH (dBm),
SIDEBAND SUPPRESSION (dBc)
0
–60
–80
–100
–120
–140
–15
1
12488-016
–20
10
BASEBAND INPUT VOLTAGE (Vp-p Differential)
–180
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
Figure 16. SSB Output Power, Second- and Third-Order Harmonics, Carrier
Feedthrough, and Sideband Suppression vs. Baseband Differential Input
Voltage (fOUT = 2600 MHz)
0
TA = –40°C
TA = +25°C
TA = +85°C
–20
PHASE NOISE (dBc/Hz)
–40
–60
–80
–100
–120
–80
–100
–120
–140
–160
–160
–180
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
Figure 17. Closed-Loop Phase Noise vs. Offset Frequency and Temperature,
fLO = 1900 MHz; 20 kHz Loop Filter
0
–20
–180
1k
100k
1M
10M
Figure 20. Closed-Loop Phase Noise vs. Offset Frequency and Temperature,
fLO = 2140 MHz; 20 kHz Loop Filter
0
TA = –40°C
TA = +25°C
TA = +85°C
–20
TA = –40°C
TA = +25°C
TA = +85°C
–40
PHASE NOISE (dBc/Hz)
–60
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M
–180
1k
12488-018
–180
1k
10k
OFFSET FREQUENCY (Hz)
–40
PHASE NOISE (dBc/Hz)
–60
–140
12488-017
PHASE NOISE (dBc/Hz)
–40
TA = –40°C
TA = +25°C
TA = +85°C
12488-020
–20
Figure 19. Closed-Loop Phase Noise vs. Offset Frequency and Temperature,
fLO = 940 MHz; 20 kHz Loop Filter
Figure 18. Closed-Loop Phase Noise vs. Offset Frequency and Temperature,
fLO = 2300 MHz; 20 kHz Loop Filter
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M
12488-021
0
12488-019
–160
–80
0.1
Figure 21. Closed-Loop Phase Noise vs. Offset Frequency and Temperature,
fLO = 2600 MHz; 20 kHz Loop Filter
Rev. B | Page 13 of 43
ADRF6720-27
Data Sheet
–80
TA = –40°C
TA = +25°C
TA = +85°C
–90
–80
–90
OFFSET = 1kHz
–110
OFFSET = 100kHz
–120
–130
–140
OFFSET = 5MHz
2400
–170
400
TA = –40°C
TA = +25°C
TA = +85°C
SPUR LEVEL (dBc)
–85
–90
–95
–100
–105
–95
–100
–105
–110
–115
–115
1900
2400
LO FREQUENCY (MHz)
Figure 23. PLL Reference Spurs vs. LO Frequency (1 × PFD and 3 × PFD) at
Modulator Output
–120
400
1400
1900
2400
Figure 26. PLL Reference Spurs vs. LO Frequency (1 × PFD and 3 × PFD) at
LO Output
TA = –40°C
TA = +25°C
TA = +85°C
–75
–85
SPUR LEVEL (dBc)
–80
–85
–90
–95
–100
–105
–90
–95
–100
–105
–110
–110
–115
–115
1900
LO FREQUENCY (MHz)
2400
–120
400
12488-024
1400
900
–70
2× PFD FREQUENCY
4× PFD FREQUENCY
900
TA = –40°C
TA = +25°C
TA = +85°C
1× PFD FREQUENCY
3× PFD FREQUENCY
LO FREQUENCY (MHz)
–80
–120
400
2400
–90
–110
–70
1900
–75
–85
–75
1400
Figure 25. Closed-Loop Phase Noise vs. LO Frequency at 10 kHz, 1 MHz, and
10 MHz Offsets
–80
1400
900
–70
1× PFD FREQUENCY
3× PFD FREQUENCY
900
TA = –40°C
TA = +25°C
TA = +85°C
OFFSET = 10MHz
LO FREQUENCY (MHz)
–80
–120
400
OFFSET = 1MHz
12488-025
1900
12488-023
SPUR LEVEL (dBc)
–140
12488-026
1400
12488-022
900
Figure 22. Closed-Loop Phase Noise vs. LO Frequency at 1 kHz, 100 kHz, and
5 MHz Offsets
–75
–130
–160
LO FREQUENCY (MHz)
–70
–120
–150
–160
–170
400
–110
Figure 24. PLL Reference Spurs vs. LO Frequency (2 × PFD and 4 × PFD) at
Modulator Output
TA = –40°C
TA = +25°C
TA = +85°C
2× PFD FREQUENCY
4× PFD FREQUENCY
900
1400
1900
LO FREQUENCY (MHz)
2400
12488-027
–150
SPUR LEVEL (dBc)
OFFSET = 10kHz
–100
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–100
Figure 27. PLL Reference Spurs vs. LO Frequency (2 × PFD and 4 × PFD) at
LO Output
Rev. B | Page 14 of 43
ADRF6720-27
2.8
0.9
2.6
0.8
2.4
0.7
2.2
0.6
2.0
VTUNE (V)
1
0.5
0.4
1.6
1.2
0.2
TA = –40°C
TA = +25°C
TA = +85°C
900
1400
1900
1.0
2400
0.8
2800
LO FREQUENCY (MHz)
–60
–60
PHASE NOISE (dBc/Hz)
4800
5300
5800
–80
–100
–120
–80
–100
–120
–140
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–160
12488-029
1k
Figure 29. Open-Loop VCO Phase Noise for VCO 0 Measured at 2302.24 MHz,
2578.49 MHz, and 2858.07 MHz (VCO ÷ 2)
–60
PHASE NOISE (dBc/Hz)
–60
–120
10k
100k
1M
10M
100M
Figure 32. Open-Loop VCO Phase Noise for VCO 1 Measured at 2009.39 MHz,
2156.68 MHz, and 2303.74 MHz (VCO ÷ 2)
–40
–100
1k
FREQUENCY (Hz)
–40
–80
2303.74MHz
2156.68MHz
2009.39MHz
12488-032
2858.07MHz
2578.49MHz
2302.24MHz
–80
–100
–120
–140
–140
2011.44MHz
1880.53MHz
1750.79MHz
10k
100k
1M
FREQUENCY (Hz)
10M
100M
–160
12488-030
1k
Figure 30. Open-Loop VCO Phase Noise for VCO 2 Measured at 1750.79 MHz,
1880.53 MHz, and 2011.44 MHz (VCO ÷ 2)
1750.85MHz
1588.9MHz
1425.84MHz
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
12488-033
PHASE NOISE (dBc/Hz)
–40
–140
PHASE NOISE (dBc/Hz)
4300
Figure 31. VTUNE vs. VCO Frequency and Temperature
–40
–160
3800
VCO FREQUENCY (MHz)
Figure 28. Integrated Phase Noise with Spurs vs. LO Frequency and
Temperature
–160
3300
12488-031
0.1
0
400
1.8
1.4
0.3
12488-028
INTEGRATED PHASE NOISE (°rms)
Data Sheet
Figure 33. Open-Loop VCO Phase Noise for VCO 3 Measured at 1425.84 MHz,
1588.9 MHz, and 1750.85 MHz (VCO ÷ 2)
Rev. B | Page 15 of 43
ADRF6720-27
Data Sheet
100
5
450
940
1900
2140
2300
2600
80
70
60
50
40
30
20
2
1
LO_DRV_LVL = 1
0
–1
–2
–3
–4
LO_DRV_LVL = 0
–5
–6
12488-034
NOISE FLOOR (dBm/Hz)
–8
400
0.48
TA = –40°C
TA = +25°C
TA = +85°C
60
50
40
30
0.44
0.42
0.40
0.38
0.36
20
0.34
10
0.32
NOISE FLOOR (dBm/Hz)
0.30
400
12488-035
0
–163 –162 –161 –160 –159 –158 –157 –156 –155 –154 –153
Figure 35. Noise Floor Cumulative Distribution at Various LO Frequencies
Using Internal LO; I/Q Input with 2.68 V DC Bias and RF Output = −10 dBm
900
1400
1900
12488-038
70
2400
LO FREQUENCY (MHz)
Figure 38. Supply Current vs. LO Frequency and Temperature (PLL and
I/Q Modulator Enabled, LO Buffer Disabled)
0
20
15
–5
5
0
–5
–10
–15
–20
–10
–25
–15
0.5
1.0
1.5
2.0
2.5
3.0
TIME (ms)
3.5
4.0
4.5
5.0
–30
0.35
12488-036
0
Figure 36. Frequency Deviation from LO Frequency at LO = 1.91 GHz to
1.9 GHz vs. Lock Time
BAL_CIN = 0, BAL_COUT = 0
BAL_CIN = 1, BAL_COUT = 0
BAL_CIN = 2, BAL_COUT = 0
BAL_CIN = 3, BAL_COUT = 0
BAL_CIN = 4, BAL_COUT = 0
BAL_CIN = 8, BAL_COUT = 0
BAL_CIN = 9, BAL_COUT = 0
BAL_CIN = 10, BAL_COUT = 0
BAL_CIN = 11, BAL_COUT = 0
BAL_CIN = 12, BAL_COUT = 0
BAL_CIN = 13, BAL_COUT = 0
BAL_CIN = 14, BAL_COUT = 0
BAL_CIN = 15, BAL_COUT = 0
BAL_CIN = 15, BAL_COUT = 3
BAL_CIN = 15, BAL_COUT = 8
BAL_CIN = 15, BAL_COUT = 11
BAL_CIN = 15, BAL_COUT = 15
0.85
1.35
1.85
LO FREQUENCY (GHz)
2.35
2.85
12488-039
RETURN LOSS (dB)
10
–20
2400
0.46
SUPPLY CURRENT (A)
80
1900
Figure 37. LO Output Power vs. LO Frequency at Various LO_DRV_LVL
Settings
0.50
450
940
1900
2140
2300
2600
90
1400
LO FREQUENCY (MHz)
Figure 34. Noise Floor Cumulative Distribution at Various LO Frequencies
Using Internal LO; I/Q Input with 2.68 V DC Bias and No RF Output
100
900
12488-037
–7
0
–163 –162 –161 –160 –159 –158 –157 –156 –155 –154 –153
CUMMULATIVE PERCENTAGE (%)
LO_DRV_LVL = 2
3
10
FREQUENCY DEVIATION (MHz)
TA = –40°C
TA = +25°C
TA = +85°C
4
LO OUTPUT POWER (dBm)
CUMMULATIVE PERCENTAGE (%)
90
Figure 39. RF Output Return Loss vs. LO Frequency (fLO) for Multiple BAL_CIN
and BAL_COUT Combinations
Rev. B | Page 16 of 43
ADRF6720-27
0
–5
–5
RETURN LOSS (dB)
0
–10
–15
–15
1.3
2.3
3.3
4.3
5.3
LO FREQUENCY (GHz)
6.3
Figure 40. LO Input Return Loss vs. LO Frequency (fLO)
–25
0.3
1.3
2.3
3.3
4.3
5.3
LO FREQUENCY (GHz)
Figure 41. LO Output Return Loss vs. LO Frequency (fLO)
Rev. B | Page 17 of 43
6.3
12488-041
–25
0.3
–10
–20
–20
12488-040
RETURN LOSS (dB)
Data Sheet
ADRF6720-27
Data Sheet
THEORY OF OPERATION
Internal LO Mode
The ADRF6720-27 integrates a high performance broadband
I/Q modulator with a fractional-N PLL and low noise multicore
VCOs. The baseband inputs mix with the LO generated
internally or provided externally, and convert it to a singleended RF using an integrated RF balun. A block diagram of the
device is shown in Figure 1. The ADRF6720-27 is programmed
via an SPI.
For internal LO mode, the ADRF6720-27 uses the on-chip PLL
and VCO to synthesize the frequency of the LO signal. The
PLL, shown in Figure 42, consists of a reference path, phase and
frequency detector (PFD), charge pump, and a programmable
integer divider with prescaler. The reference path takes in a
reference clock and divides it down by a factor of 2, 4, or 8, or
multiplies it by a factor of 1 or 2, and then passes it to the PFD.
The PFD compares this signal to the divided down signal from
the VCO. Depending on the PFD polarity selected, the PFD
sends either an up or down signal to the charge pump if the
VCO signal is either slow or fast compared to the reference
frequency. The charge pump sends a current pulse to the offchip loop filter to increase or decrease the tuning voltage
(VTUNE).
LO GENERATION BLOCK
The ADRF6720-27 supports the use of both internal and
external LO signals for the mixers. The internal LO is generated
by an on-chip VCO, which is tunable over an octave frequency
range of 2850 MHz to 5710 MHz. The output of the VCO is
phase-locked to an external reference clock through a fractional-N
PLL that is programmable through the SPI control registers. To
produce in-phase and quadrature phase LO signals over the
356.25 MHz to 2855 MHz frequency range to drive the mixers,
steer the VCO outputs through a combination of frequency
dividers, as shown in Figure 42.
The ADRF6720-27 integrates four VCO cores, covering an octave
range of 2850 MHz to 5710 MHz.
Table 6 lists the frequency range covered by each VCO. The
desired VCO can be selected by addressing the VCO_SEL bits at
Register 0x22[2:0].
Alternatively, an external signal can be used with the dividers or
a polyphase phase splitter to generate the LO signals in quadrature
to the mixers. In demanding applications that require the lowest
possible phase noise performance, it may be necessary to source
the LO signal externally. The different methods of quadrature
LO generation and the control register programming needed
are listed in Table 6.
The LO source and quadrature generation path can be selected
by setting the QUAD_DIV_EN bit (Register 0x01[9]) and the
LO_1XVCO_EN bit (Register 0x01[11]).
The mode of the VCO signal through a polyphase filter is
intended to extend the operating frequency with an internal
VCO and is only useful for baseband input frequencies high
enough to prevent the RF output from pulling the VCO.
POLYPHASE
FILTER
LOIN+ 34
REF_SEL
REG 0x21[2:0]
÷8
÷4
REFIN 39
LOIN– 33
PFD
+
×1
CHARGE
PUMP
CP
VTUNE
36
32
LPF
CP_CTL
REG 0x20[14:0]
×2
÷1, ÷2,
÷4
QUAD
DIVIDER
EXTERNAL
LOOP
FILTER
PFD_POLARITY
REG 0x21[3]
÷2
LO_1XVCO_EN
REG 0x01[11]
QUAD_DIV_EN
REG 0x01[9]
LO_I+
LO_I–
LO_Q+
LO_Q–
TO
MIXER
DIV8 _EN/
DIV4_EN
REG 0x22[4:3]
N = INT +
FRAC
MOD
÷1,÷2
÷2
DRVDIV2_EN
REG 0x22[5]
LOOUT+
LOOUT–
MUXOUT 1
DIV_MODE: REG 0x02[11]
INT_DIV: REG 0x02[10:0]
FRAC_DIV: REG 0x03[15:0]
MOD_DIV: REG 0x04[15:0]
VCO_SEL
REG 0x22[2:0]
REF_MUX_SEL
REG 0x21[6:4]
Figure 42. LO Block Diagram
Rev. B | Page 18 of 43
LO_DRV2X_EN REG 0x01[8]
LO_DRV1X_EN REG 0x01[7]
12488-042
LOCK_DET
VPTAT
Data Sheet
ADRF6720-27
Table 6. LO Mode Selection
LO
Selection
Internal
(VCO)
fVCO or fEXT (MHz)
2850 to 3500
3500 to 4020
4020 to 4600
4600 to 5710
2855 to 3000
700 to 6000
700 to 3000
External
1
Quadrature
Generation
Divide by 2
Divide by 2
Divide by 2
Divide by 2
Polyphase
Divide by 2
Polyphase
QUAD_DIV_EN
(Register 0x01[9])
1
1
1
1
0
1
0
LO_1XVCO_EN
(Register 0x1[11])
0
0
0
0
1
0
0
Enables
(Register 0x01[6:0])
111 111X1
111 111X1
111 111X1
111 111X1
111 111X1
101 000X1
000 000X1
VCO_SEL
(Register 0x22[2:0])
011
010
001
000
011
1XX1
XXX1
X = don’t care.
LO Frequency and Dividers
The signal coming from the VCO or the external LO inputs
goes through a series of dividers before it is buffered to drive
the active mixers. Two programmable divide by 2 stages divide
the frequency of the incoming signal by 1, 2, or 4 before
reaching the quadrature divider that further divides the signal
frequency by 2 to generate the in-phase and quadrature phase
LO signals for the mixers. The control bits (Register 0x22[4:3])
needed to select the different LO frequency ranges are listed in
Table 7.
Table 7. LO Frequency and Dividers
LO Frequency
Range (MHz)
1425 to 2855
712.5 to 1425
356.25 to 712.5
fVCO/fLO or
fEXT LO/fLO
2
4
8
DIV8_EN
(Register
0x22[4])
0
0
1
DIV4_EN
(Register
0x22[3])
0
1
1
The N divider with divide by 2 divides down the VCO signal to
the PFD frequency. The N divider can be configured for
fractional or integer mode by addressing the DIV_MODE bit
(Register 0x02[11]). The default configuration is set for
fractional mode. Use the following equations to determine the
N value and PLL frequency:
f VCO
2× N
N = INT +
f LO =
Loop Filter
The loop filter is connected between the CP and VTUNE pins.
The recommended components for 20 kHz filter designs are
shown in Table 8 and referenced in Figure 44.
The ADRF6720-27 closed-loop phase noise is characterized
using a 20 kHz loop filter. Operation with an external VCO is
possible. In this case, the output of the loop filter is connected
to the tuning pin of the external VCO. The output of the VCO is
brought back into the device on the LOIN+ and LOIN− pins.
For assistance in designing loop filters with other characteristics,
download the most recent revision of ADIsimPLL™ from
www.analog.com/adisimpll.
Table 8. Recommended Loop Filter Components
PLL Frequency Programming
f PFD =
LO_DIVIDER is the final frequency divider ratio that divides
the frequency of the VCO or the external LO signal down by 2,
4, or 8 before it reaches the mixer, as shown in Table 7.
Component
C57
R12
C58
R23
C59
R26
C60
20 kHz Loop Filter
2700 pF
300 Ω
100 nF
5.6 Ω
2700 pF
820 Ω
1500 pF
PLL Lock Time
It takes time to lock the PLL after the last register is written.
VCO band calibration time and loop settling time are used to
determine the PLL lock time.
FRAC
MOD
f ×2×N
fvco
= PFD
LO _ DIVIDER LO_DIVIDER
where:
fPFD is the phase frequency detector frequency.
fVCO is the VCO frequency.
N is the fractional divide ratio (INT + FRAC/MOD).
INT is the integer divide ratio programmed in Register 0x02.
FRAC is the fractional divider programmed in Register 0x03.
MOD is the modulus divide ratio programmed in Register 0x04.
fLO is the LO frequency going to the mixer core when the loop is
locked.
After writing to the last register, the PLL automatically performs
a VCO band calibration to choose the correct VCO band. This
calibration takes approximately 94,208 PFD cycles. For a
40 MHz fPFD, this corresponds to 2.36 ms. After a band calibration
completes, the feedback action of the PLL results in the VCO
locking to the correct frequency. The speed to be locked depends
on the nonlinear cycle slipping behavior, as well as the small
signal settling of the loop. For an accurate estimation of the lock
time, download the ADIsimPLL tool to capture these effects
correctly. In general, higher bandwidth loops tend to lock more
quickly than lower bandwidth loops.
Rev. B | Page 19 of 43
ADRF6720-27
Data Sheet
The lock detect signal is available as one of the selectable
outputs through the MUXOUT pin, with a logic high signifying
that the loop is locked. The control bits for the MUXOUT pin
are the REF_MUX_SEL bits (Register 0x21[6:4]), and the
default configuration is for PLL lock detect.
Table 10. LO Polarity Setting
Address
0x32[11:10]
Bit
Name
POL_Q
01
Required PLL/VCO Settings and Register Write Sequence
In addition to writing to the necessary registers to configure the
PLL and VCO for the desired LO frequency and phase noise
performance, the registers listed in Table 9 are the required
registers to write.
To ensure that the PLL locks to the desired frequency, follow the
proper write sequence of the PLL registers. Configure the PLL
registers accordingly to achieve the desired frequency, and the
last writes must be to Register 0x02 (INT_DIV), Register 0x03
(FRAC_DIV), or Register 0x04 (MOD_DIV). When Register 0x02,
Register 0x03, and Register 0x04 are programmed, an internal
VCO calibration initiates, which is the last step to locking the PLL.
Table 9. Required PLL/VCO Register Writes
Address
0x21[3]
0x49[13:0]
Bit Name
PFD_POLARITY
SET_1[13:9],
SET_0[8:0]
Setting
0x01
0x14B4
Description
Negative polarity
Internal settings
External LO Mode
Use the VCO_SEL bits (Register 0x22[2:0]) to select external or
internal LO mode. To configure for external LO mode, set
Register 0x22[2:0] to 4 decimal and apply the differential LO
signals to Pin 33 (LOIN−) and Pin 34 (LOIN+). The external
LO frequency range is 700 MHz to 3 GHz. When the polyphase
phase splitter is selected, a 1 × LO signal is required for the
active mixer, or a 2 × LO can be used with the internal
quadrature divider, as shown in Table 6.
There is also the option of using an external VCO with the
internal PLL. In this case, the PLL is enabled, but the VCO
blocks are turned off.
The LOIN+ and LOIN− input pins must be ac-coupled. When
not in use, leave the LOIN+ and LOIN− pins unconnected.
LO Polarity
The ADRF6720-27 offers the flexibility of specifying the
quadrature polarity on LO to the I channel or Q channel
mixers. This specification determines whether the LO is
injected above or below the RF frequency. RF frequency can
place either above or below the LO depending on the
Register 0x32[11:8] setting as well as the phase relationship
between the baseband I and Q. For normal operation and
characterization, the Register 0x32 settings are 2 decimal for POL_I
(Register 0x32[9:8]) and 1 decimal for POL_Q (Register 0x32,
Bits[11:10]). Setting Register 0x32 as such places the RF
frequency below the LO (fRF < fLO) when Q leads I and places the
RF frequency above the LO (fRF > fLO) when I leads Q.
Settings
10
0x32[9:8]
POL_I
01
10
Description
Quadrature polarity
switch, Q channel
Inverted Q channel
polarity
Normal polarity
Quadrature polarity
switch, I channel.
Normal polarity
Inverted I channel
polarity
LO Outputs
The ADRF6720-27 can provide either a differential 1 × or 2 ×
LO output signal at the LOOUT+ and LOOUT− pins (Pin 18
and Pin 19, respectively). The availability of the LO signal
makes it possible to daisy-chain many devices. One ADRF6720-27
device can serve as the master where the LO signal is sourced,
and the subsequent slave devices can share the same LO output
signal from the master.
When the quadrature LO signals are generated using the
quadrature divider, the output signal is available at either 2× or
1× the frequency of the LO signal at the mixer by setting
LO_DRV2X_EN bit (Register 0x1[8]) and DRVDIV2_EN bit
(Register 0x22[5]). However, 1× the frequency of the LO signal
in this case has a phase ambiguity of 180° relative to the LO
signal that drives the mixer core. Because of this phase ambiguity,
the utility of this 1 × LO output signal as a system daisy-chained
LO signal is compromised. To avoid this ambiguity, a second 1×
the frequency of the LO signal output is made available after the
quadrature divider. This second 1 × LO output path is enabled
by setting the LO_DRV1X_EN bit (Register 0x01[7]) high.
When the quadrature LO signals are generated using the
polyphase phase splitter, the output signal is also available at 1×
the frequency of the LO signal by setting LO_DRV1X_EN bit
(Register 0x10[7]) high.
Set the output to different drive levels by accessing the
LO_DRV_LVL bits (Register 0x22[7:6]), as shown in Table 11.
Table 11. LO Output Level at 2140 MHz
LO_DRV_LVL (Register 0x22[7:6])
00
01
10
Rev. B | Page 20 of 43
Amplitude (dBm)
−5.8
−1.0
2.2
Data Sheet
ADRF6720-27
BASEBAND
The baseband inputs are designed to work with a 2.68 V
common-mode voltage. To match the 100 Ω impedance of the
DAC, place a shunt 100 Ω external resistor across the I and Q
inputs.
The voltages applied to the differential baseband inputs (I+, I−,
Q+, and Q−) drive the V-to-I stage that converts baseband
voltages into currents. The converted modulated signal current
feeds the modulator mixer core.
A programmable dc current can be added to both the I and Q
channels to null any carrier feedthrough at the RF output. Refer
to the Carrier Feedthrough Nulling section for more
information
The linearity can be optimized by adding the amplitude and
phase correction signals to the current output via the MOD_RSEL
(Register 0x31[12:6]) and MOD_CSEL (Register 0x31[5:0])
adjustment. Refer to the Linearity section for more information.
ACTIVE MIXERS
The ADRF6720-27 has two double balanced mixers: one for the
in-phase channel (I channel) and the other for the quadrature
channel (Q channel). They upconvert the modulated baseband
signal currents by the LO signals to the RF.
Tunable RFOUT Balun
The ADRF6720-27 integrates a programmable balun operating
over a frequency range from 700 MHz to 3000 MHz. It offers
single-ended-to-differential conversion and provides additional
common-mode noise rejection.
The capacitors at the input and output of the balun in parallel
with the inductive windings of the balun change the resonant
frequency of the inductor capacitor (LC) tank. Therefore,
selecting the proper combination of BAL_CIN (Register 0x30[3:0])
and BAL_COUT (Register 0x30[7:4]) sets the desired frequency
and optimizes gain. Under most circumstances, it is suggested to
set BAL_CIN and BAL_COUT over the frequency profile given
in Table 12. However, for matching reasons, it is advantageous
to tune the registers independently.
BAL_COUT
REG 0x30[7:4]
BAL_CIN
0
1
2
3
4
8
9
10
11
12
13
14
15
15
15
15
15
BAL_COUT
0
0
0
0
0
0
0
0
0
0
0
0
0
3
8
11
15
Frequency Range (MHz)
fRF > 1730
1550 < fRF < 1730
1380 < fRF < 1550
1250 < fRF < 1380
1170 < fRF < 1250
1100 < fRF < 1170
1020 < fRF < 1100
970 < fRF < 1020
930 < fRF < 970
890 < fRF < 930
840 < fRF < 890
820 < fRF < 840
780 < fRF < 820
730 < fRF < 780
680 < fRF < 730
630 < fRF < 680
fRF < 630
ENBL
The ENBL pin quickly enables/disables the RF output. The
circuit blocks that are enabled/disabled with the ENBL pin can
be programmed by setting the appropriate bits in the enables
register (Register 0x01) and the ENBL_MASK register
(Register 0x10). When the bits in the enables and the
ENBL_MASK register are 1, pulling the ENBL pin low disables
and pulling high enables the internal blocks more quickly than
possible with an SPI write operation.
Table 13. Enable/Disable Settings
Register
0x01
Enables
Bit1
0
Register 0x10
ENBL_MASK
Bit1
X2
ENBL Pin
Voltage
X2
1
0
X2
1
1
>1.8 V
1
1