ADRF6801-EVALZ

750 MHz to 1150 MHz Quadrature Demodulator with Fractional-N PLL and VCO ADRF6801 Data Sheet FEATURES GENERAL DESCRIPTION IQ demodulator with integrated fractional-N PLL LO frequency range: 750 MHz to 1150 MHz Input P1dB: 12.5 dBm Input IP3: 25 dBm Noise figure (DSB): 14.3 dB Voltage conversion gain: 5.1 dB Quadrature demodulation accuracy Phase accuracy: 0.3° Amplitude accuracy: 0.05 dB Baseband demodulation: 275 MHz, 3 dB bandwidth SPI serial interface for PLL programming 40-lead, 6 mm × 6 mm LFCSP The ADRF6801 is a high dynamic range IQ demodulator with integrated PLL and VCO. The fractional-N PLL/synthesizer generates a frequency in the range of 3.0 GHz to 4.6 GHz. A divide-by-4 quadrature divider divides the output frequency of the VCO down to the required local oscillator (LO) frequency to drive the mixers in quadrature. Additionally, an output buffer can be enabled that generates an fVCO/2 signal for external use. The PLL reference input is supported from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The IQ demodulator mixes the differential RF input with the complex LO derived from the quadrature divider. The differential I and Q output paths have excellent quadrature accuracy and can handle baseband signaling or complex IF up to 120 MHz. APPLICATIONS QAM/QPSK RF/IF demodulators Cellular W-CDMA/CDMA/CDMA2000 Microwave point-to-(multi)point radios Broadband wireless and WiMAX The ADRF6801 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, exposed-paddle, RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is specified over the −40°C to +85°C temperature range. FUNCTIONAL BLOCK DIAGRAM GND VCCLO VCCLO 34 35 17 LOSEL IBBP 36 33 BUFFER CTRL IBBN GND 32 31 ADRF6801 30 GND LON 37 29 VCCBB BUFFER 28 GND LOP 38 27 VCCRF FRACTION MODULUS REG GND 11 BUFFER INTEGER REG MUX DATA 12 SPI INTERFACE QUAD ÷2 THIRD-ORDER FRACTIONAL INTERPOLATOR LE 14 GND 15 PRESCALER ÷2 N COUNTER 26 RFIN VCO CORE 25 GNDRF ×2 REFIN 6 GND 7 ÷2 24 GND MUX – PHASE + FREQUENCY DETECTOR TEMP SENSOR ÷4 3.3V LDO MUXOUT 8 1 2 10 16 VCC1 DECL3 VCC2 GND CHARGE PUMP 250µA, 500µA (DEFAULT), 750µA, 1000µA 3 4 5 CPOUT GND RSET 23 GND 22 VCCBB 2.5V LDO VCO LDO 9 39 40 DECL2 VTUNE DECL1 21 GND 18 19 20 QBBP QBBN GND 09576-001 CLK 13 DIVIDER ÷1 OR ÷2 Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF6801 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Structure ....................................................................... 14 Applications ....................................................................................... 1 Applications Information .............................................................. 21 General Description ......................................................................... 1 Basic Connections ...................................................................... 21 Functional Block Diagram .............................................................. 1 Supply Connections ................................................................... 21 Revision History ............................................................................... 2 Synthesizer Connections ........................................................... 21 Specifications..................................................................................... 3 I/Q Output Connections ........................................................... 22 Timing Characteristics ................................................................ 5 RF Input Connections ............................................................... 22 Absolute Maximum Ratings ............................................................ 6 Charge Pump/VTUNE Connections ...................................... 22 Pin Configuration and Function Descriptions ............................. 7 LO Select Interface ..................................................................... 22 Typical Performance Characteristics ............................................. 9 External LO Interface ................................................................ 22 Synthesizer/PLL .......................................................................... 12 Setting the Frequency of the PLL ............................................. 22 Complementary Cumulative Distribution Functions (CCDF) ....................................................................................................... 13 Register Programming ............................................................... 22 Circuit Description ......................................................................... 14 Evaluation Board Layout and Thermal Grounding ................... 24 LO Quadrature Drive ................................................................. 14 ADRF6801 Software .................................................................. 28 V-to-I Converter ......................................................................... 14 Characterization Setups ................................................................. 30 Mixers........................................................................................... 14 Outline Dimensions ....................................................................... 34 Emitter Follower Buffers ........................................................... 14 Ordering Guide .......................................................................... 34 EVM Measurements .................................................................. 23 Bias Circuitry .............................................................................. 14 REVISION HISTORY 6/2018—Rev. 0 to Rev. A Change to Register Structure Section .......................................... 14 Changes to Register Programming Section ................................ 22 1/2011—Revision 0: Initial Version Rev. A | Page 2 of 34 Data Sheet ADRF6801 SPECIFICATIONS VS = 5 V; ambient temperature (TA) = 25°C; fREF = 26 MHz, fLO = 900 MHz, fBB = 4.5 MHz, RLOAD = 450 Ω differential, all register and PLL settings use the recommended values shown in the Register Structure section, unless otherwise noted. Table 1. Parameter RF INPUT AT 900 MHz Internal LO Frequency Range Input Return Loss Input P1dB Second-Order Input Intercept (IIP2) Third-Order Input Intercept (IIP3) Noise Figure LO-to-RF Leakage I/Q BASEBAND OUTPUTS Voltage Conversion Gain Demodulation Bandwidth Quadrature Phase Error I/Q Amplitude Imbalance Output DC Offset (Differential) Output Common-Mode Voltage Gain Flatness Maximum Output Swing Maximum Output Current LO INPUT/OUTPUT Output Level Input Level Input Impedance VCO Operating Frequency SYNTHESIZER SPECIFICATIONS Channel Spacing PLL Bandwidth SPURS Reference Spurs Test Conditions/Comments RFIN pins With VCO amplitude = 63 (R6 [DB15 to DB10]) With VCO amplitude = 24 (R6 [DB15 to DB10]) Measured at 900 MHz Min Rev. A | Page 3 of 34 Max Unit 1125 1150 65 25 14.3 18.9 −75 MHz MHz dB dBm dBm dBm dB dB dBm 5.1 275 0.3 0.05 ±5 VPOS − 2.4 0.2 4 2.4 12 dB MHz Degrees dB mV V dB p-p V p-p V p-p mA p-p −2.5 dBm 0 50 dBm Ω MHz MHz 750 750 −5 dBm each tone −5 dBm each tone Double sideband from RF to either I or Q output With a −10 dBm interferer 5 MHz away At 1×LO frequency, 50 Ω termination at the RF port IBBP, IBBN, QBBP, QBBN pins 450 Ω differential load across IBBP, IBBN (or QBBP, QBBN) 1 V p-p signal 3 dB bandwidth Any 5 MHz (