LT8650S-1
Dual Channel 4A, 42V,
Synchronous Step-Down Silent Switcher 2
with 6.2µA Quiescent Current
DESCRIPTION
FEATURES
Silent Switcher®2 Architecture:
nn Ultralow EMI on Any PCB
nn Eliminates PCB Layout Sensitivity
nn Internal Bypass Capacitors Reduce Radiated EMI
nn Optional Spread Spectrum Modulation
nn 4A DC from Each Channel Simultaneously
nn Up to 6A on Either Channel
nn Ultralow Quiescent Current Burst Mode® Operation:
nn 6.2μA I Regulating 12V to 5V
Q
IN
OUT1 and 3.3VOUT2
nn Output Ripple 0.8V, VVC1 = VVC2 = VCC,
VSYNC = 0V
l
VIN1 + VCC Quiescent Current in
Sleep with External Compensation
VEN/UV1 = VEN/UV2 = 2V, VFB1 = VFB2 >0.8V, VVC1 = VVC2 = Float,
VSYNC = 0V
l
2
UNITS
Rev 0
For more information www.analog.com
LT8650S-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
VIN1 + VCC Quiescent Current when
Active
VEN/UV1 = VEN/UV2 = 2V, VFB1 = VFB2 >0.8V, VVC1 = VVC2 = VCC, VSYNC = 3.4V
MIN
VIN Current in Regulation
VIN = 12V, VOUT = 3.3V, Output Load = 100µA, VVC1 = VVC2 = VCC, VSYNC = 0V
VIN = 12V, VOUT = 3.3V, Output Load = 1mA, VVC1 = VVC2 = VCC, VSYNC = 0V
l
Feedback Reference Voltage
l
Feedback Voltage Line Regulation
0.794
0.790
VIN = 4.0V to 36V
Feedback Pin Input Current
VFB = 0.8V
Minimum On-Time
ILOAD = 3A, SYNC = 3.4V
l
Oscillator Frequency
RT = 133k
RT = 35.7k
RT = 15k
l
l
l
l
MAX
5
7
mA
45
350
75
550
µA
µA
0.800
0.800
0.806
0.810
V
V
0.004
0.02
%/V
–20
Top Power NMOS Current Limit
Bottom Power NMOS Current Limit
SW Leakage Current
VIN = 42V, VSW = 0V,42V
EN/UV Pin Threshold
EN/UV Falling
20
nA
60
ns
270
0.95
1.85
300
1.0
2.00
330
1.05
2.15
10
12
14
6.5
8.5
10.5
A
2
µA
–2
l
0.7
0.74
–20
kHz
MHz
MHz
A
0.78
30
VEN/UV = 2V
UNITS
40
EN/UV Pin Hysteresis
EN/UV Pin Current
TYP
V
mV
20
nA
PG Upper Threshold Offset from VFB VFB Falling
l
5.5
7.5
9
%
PG Lower Threshold Offset from VFB VFB Rising
PG Hysteresis
l
–9.5
–7.5
–6
%
40
nA
0.3
PG Leakage
VPG = 12V
PG Pull-Down Resistance
VPG = 0.1V
SYNC Threshold
SYNC DC and Clock Low Level Voltage
SYNC Clock High Level Voltage
SYNC DC High Level Voltage
SYNC Pin Current
VSYNC = 6V
–40
600
l
0.4
%
1200
l
1.0
V
V
V
1.5
2.8
120
SS Source Current
Ohm
2.0
µA
3.0
µA
SS Pull-Down Resistance
Fault Condition, SS = 0.1V
200
Ω
Error Amplifier Transconductance
VC = 1.25V
0.9
mS
VC Source Current
VFB = 0.6V, VVC = 1.25V
170
µA
VC Sink Current
VFB = 1.0V, VVC = 1.25V
170
µA
VC Pin to Switch Current Gain
TEMP Output Voltage
9.6
ITEMP = 0µA, Temperature = 25°C
ITEMP = 0µA, Temperature = 125°C
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:The LT8650S-1 is guaranteed over the full –40°C to 150°C
operating junction temperature range. High junction temperatures degrade
operating lifetimes. Operating lifetime is derated at junction temperatures
greater than 125°C. The junction temperature (TJ, in °C) is calculated from
190
1100
250
1200
A/V
310
1300
mV
mV
the ambient temperature (TA in °C) and power dissipation (PD, in Watts)
according to the formula:
TJ = TA + (PD • θJA) where θJA (in °C/W) is the package thermal
impedance.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during overload conditions. Junction temperature will
exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
will reduce lifetime
Rev 0
For more information www.analog.com
3
LT8650S-1
TYPICAL PERFORMANCE CHARACTERISTICS
5VOUT Efficiency
fSW = 2MHz
FCM
95
100
5.5
90
5.0
85
4.5
80
4.0
3.5
75
12V
24V
36V
70
65
60
3.0
2.5
2.0
55
50
45
40
1.5
POWER LOSS
0
1
2
3
4
LOAD CURRENT (A)
5
BURST
70
60
50
FCM
40
12V
24V
36V
30
10
0.5
6
fSW = 2MHz
20
1.0
L = XFL5030, 1.0µH
5VOUT Efficiency
80
POWER LOSS (W)
EFFICIENCY (%)
90
EFFICIENCY
6.0
EFFICIENCY (%)
100
L = XFL5030, 1.0µH
0
0.1
0
1
10
100
1k
LOAD CURRENT (mA)
8650s1 G02
8650s1 G01
fSW = 2MHz
FCM
95
90
EFFICIENCY
6.0
100
5.5
90
5.0
85
4.5
80
4.0
75
3.5
12V
24V
36V
70
65
3.0
2.5
60
50
55
1.5
50
POWER LOSS 1.0
20
0.5
10
L = XFL5030, 1.0µH
0
1
2
3
4
LOAD CURRENT (A)
5
6
FCM
40
2.0
40
BURST
70
60
45
fSW = 2MHz
80
POWER LOSS (W)
EFFICIENCY (%)
3.3VOUT Efficiency
3.3VOUT Efficiency
EFFICIENCY (%)
100
12V
24V
36V
30
L = XFL5030, 1.0µH
0
0.1
0
1
10
100
1k
LOAD CURRENT (mA)
Efficiency at Different fSW
100
10k
8650s1 G04
8650s1 G03
100
10k
Efficiency vs fSW
Reference Voltage
0.810
90
90
85
80
75
12VIN
3.3VOUT
L = IHLP2525EZ–01
70
0.5
1
1.5
0.5MHz 2.2µH
1MHz 1.5µH
2MHz 1.5µH
3MHz 1.5µH
2 2.5 3 3.5 4
LOAD CURRENT (A)
4.5
8650s1 G05
4
85
80
75
5
REFERENCE VOLTAGE (V)
95
EFFICIENCY (%)
EFFICIENCY (%)
0.808
95
12VIN
3.3VOUT
1.8A LOAD
L = IHLP2525EZ–01, 1.5µH
70
0.5
0.806
0.804
0.802
0.800
0.798
0.796
0.794
0.792
1
1.5
2
2.5
SWITCHING FREQUENCY (MHz)
3
8650s1 G06
0.790
–55
–25
5
35
65
95
TEMPERATURE (°C)
125
155
8650s1 G07
Rev 0
For more information www.analog.com
LT8650S-1
TYPICAL PERFORMANCE CHARACTERISTICS
Load Regulation
0.30
0.20
0.10
0.00
–0.10
–0.20
–0.30
–0.40
CH1
CH2
0
1
2
3
4
OUTPUT CURRENT (A)
5
6
20
VIN1 = VIN2
IOUT = 0A
0.3
CHANGE IN VOUT (%)
CHANGE IN VOUT (%)
0.4
VIN1 = VIN2 = 12V
VOUT1 = 5V, VOUT2 = 3.3V
FCM, fSW = 2MHz
16
0.2
0.1
0.0
–0.1
–0.2
4
0
0
5
10
15 20 25 30 35
INPUT VOLTAGE (V)
40
120
45
35
VIN1 = VIN2 = 12V
VOUT1 = 5V, VOUT2 = 3.3V
VBIAS = VOUT1
SYNC = 0V
40
–25
5
35
65
95
TEMPERATURE (°C)
CURRENT LIMIT (A)
4
5
35
65
95
TEMPERATURE (°C)
125
8
6
2
155
125
155
8650s1 G14
0
0.2
0.4
0.6
DUTY CYCLE
0.8
1
8650s1 G13
11
500
10
450
9
400
8
350
SWITCH VDS (mV)
30% DC
–25
10
8650s1 G12
14
2
–55
12
Bottom FET Current Limit
6
40
BOTH CHANNELS IN REGULATION
INTERNAL COMP
EXTERNAL COMP
Top FET Current Limit
8
35
4
8650s1 G11
10
15
20
25
30
INPUT VOLTAGE (V)
14
60
0
–55
40
12
10
Top FET Current Limit
80
BOTH CHANNELS ENABLED, BIAS = FLOAT
ONLY CHANNEL 2 ENABLED, BIAS = FLOAT
BOTH CHANNELS ENABLED, BIAS = VOUT2
ONLY CHANNEL 2 ENABLED, BIAS = VOUT2
16
5
8650s1 G10
20
15
20
25
30
INPUT VOLTAGE (V)
BOTH CHANNELS ENABLED
ONLY CHANNEL 2 ENABLED
16
100
20
CURRENT LIMIT (A)
40
CURRENT LIMIT (A)
INPUT CURRENT (µA)
INPUT CURRENT (µA)
140
60
10
6
No Load Supply Current
80
5
8
2
160
100
0
10
8650s1 G09
VIN1 = VIN2
VOUT1 = 5V, VOUT2 = 3.3V
IN REGULATION
SYNC = 0V
120
12
–0.4
No Load Supply Current with
External Compensation
140
14
–0.3
8650s1 G08
160
VIN1 = VIN2
VOUT1 = 5V, VOUT2 = 3.3V
IN REGULATION
SYNC = 0V, VBIAS = VOUT2
18
INPUT CURRENT (µA)
0.40
No Load Supply Current with
Internal Compensation
Line Regulation
7
6
5
4
300
250
200
150
3
100
2
50
1
–55
–25
5
35
65
95
TEMPERATURE (°C)
125
155
8650s1 G15
Switch VDS
0
TOP FET
BOT FET
0
1
2
3
IDS (A)
4
5
8650s1 G16
Rev 0
For more information www.analog.com
5
LT8650S-1
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum On-Time
Minimum Off-Time
60
FCM, 2A LOAD
50
40
30
20
10
58
57
56
55
54
53
52
–25
5
35
65
95
TEMPERATURE (°C)
125
–25
5
35
65
95
TEMPERATURE (°C)
RT = 15kΩ
2.00
1.95
1.90
1.85
125
0
155
0
0.5
1
1.5 2 2.5 3
LOAD CURRENT (A)
1.75
1.50
3.5
4
8650s1 G19
Soft-Start Tracking
1.0
0.8
1.25
1.00
0.75
0.50
0.6
0.4
0.2
–25
5
35
65
95
TEMPERATURE (°C)
125
0
155
0
0.20
0.40 0.60 0.80
LOAD CURRENT (A)
1.00
8650s1 G20
EN Pin Thresholds
1.9
0.75
0.74
0.73
1.8
0.72
1.7
0.71
1.6
–55
0.70
–55
5
35
65
95
TEMPERATURE (°C)
125
155
8650s1 G23
0.4
0.6
0.8
SS VOLTAGE (V)
1.0
1.2
PG High Threshold
0.76
EN THRESHOLD (V)
2.2
2.0
0.2
10.0
0.77
2.1
0
8650s1 G22
0.78
VSS = 0.4V
–25
0
1.20
8650s1 G21
Soft-Start Current
SS PIN CURRENT (µA)
Burst Mode
OPERATION
200
0.25
1.80
–55
6
300
FB VOLTAGE (V)
2.05
2.3
400
VIN1 = VIN2 = 12V
VOUT = 5V
SYNC = 0V
RT = 15kΩ
L = 1.0µH
2.00
SWITCHING FREQUENCY (MHz)
SWITCHING FREQUENCY (MHz)
2.25
2.10
2.4
500
Burst Frequency
Switching Frequency
2.15
600
8650s1 G18
8650s1 G17
2.20
700
100
50
–55
155
FCM
800
51
0
–55
fSW = 2MHz
VOUT = 3V
900
DROPOUT VOLTAGE (mV)
MINIMUM OFF–TIME (ns)
60
MINIMUM ON–TIME (ns)
FCM, 1A LOAD
59
70
Dropout Voltage
1000
EN RISING
EN FALLING
–25
5
35
65
95
TEMPERATURE (°C)
125
155
8650s1 G24
PG THRESHOLD OFFSET FROM VREF (%)
80
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
–55
RISING
–25
5
35
65
95
TEMPERATURE (°C)
125
155
86501s1 G25
Rev 0
For more information www.analog.com
LT8650S-1
TYPICAL PERFORMANCE CHARACTERISTICS
RT Programmed Switching
Frequency
–5.0
150
–5.5
135
–6.0
120
–6.5
–7.0
–7.5
–8.0
–8.5
–9.0
Minimum Input Voltage
3.0
VIN1 = VIN2
2.8
105
INPUT VOLTAGE (V)
RT PIN RESISTOR (kΩ)
PG THRESHOLD OFFSET FROM VREF (%)
PG Low Threshold
90
75
60
45
30
–9.5
–10.0
–55
5
35
65
95
TEMPERATURE (°C)
125
2.2
0
155
0
0.5
1
1.5
2
2.5
SWITCHING FREQUENCY (MHZ)
8650s1 G26
EN2 = 0V, SS1=0V, FCM
0.35
0.05
BELOW 5°C: 10kΩ RESISTOR
FROM TEMP TO –2V
ABOVE 5°C: FLOAT TEMP
–0.55
–55
–25
5
35
65
95
TEMPERATURE (°C)
125
155
20
17.0
16.5
16.0
15.5
15.0
14.0
14
12
10
8
6
5
10
15
20 25 30 35
INPUT VOLTAGE (V)
40
45
0
0.5
1
1.5
2
2.5
SWITCHING FREQUENCY (MHZ)
3
Transient Response External
Compensation
ILOAD
2A/DIV
VOUT
100mV/DIV
VOUT
100mV/DIV
8650s1 G32
0
8650s1 G31
Transient Response Internal
Compensation
VOUT
100mV/DIV
2A TO 4A TRANSIENT
3.3VOUT
COUT = 47µF ×2
FCM, fSW = 2MHz
16
2
ILOAD
2A/DIV
20µs/DIV
18
8650s1 G30
Transient Response Internal
Compensation
155
4
14.5
8650s1 G29
ILOAD
2A/DIV
125
VIN = 12V
LOAD = 2A
22
BIAS PIN CURRENT (mA)
BIAS PIN CURRENT (mA)
TEMP PIN VOLTAGE (V)
0.65
5
35
65
95
TEMPERATURE (°C)
Bias Pin Current per Channel
24
fSW = 2MHz
LOAD = 1A
17.5
0.95
–25
8650s1 G28
Bias Pin Current per Channel
18.0
1.25
–0.25
2.0
–55
3
8650s1 G27
Temperature Monitor Pin
1.55
2.4
15
FALLING
–25
2.6
20µs/DIV
8650s1 G33
40mA TO 2A TRANSIENT
3.3VOUT
COUT = 47µF ×2
FCM, fSW = 2MHz
20µs/DIV
8650s1 G34
2A TO 4A TRANSIENT
3.3VOUT
COUT = 47µF ×2
FCM, fSW = 2MHz
CC = 220pF, RC = 14kΩ
Rev 0
For more information www.analog.com
7
LT8650S-1
TYPICAL PERFORMANCE CHARACTERISTICS
Transient Response External
Compensation
Forced Continuous Mode (FCM)
ILOAD
2A/DIV
VOUT
100mV/DIV
20µs/DIV
Burst Mode Operation
SW
5V/DIV
SW
5V/DIV
IL
1A/DIV
IL
1A/DIV
8650s1 G35
8650s1 G36
2µs/DIV
2µs/DIV
40mA TO 2A TRANSIENT
3.3VOUT
COUT = 47µF ×2
FCM, fSW = 2MHz
CC = 220pF, RC = 14kΩ
12VIN TO 5VOUT AT 100mA
SYNC = FLOAT
12VIN TO 5VOUT AT 100mA
SYNC = 0V
CH1, CH2, and CLKOUT
Switch Rising Edge
Start-Up Dropout Performance
SW1
10V/DIV
FCM
(SYNC FLOAT)
VIN
2V/DIV
SW2
10V/DIV
VSW
2V/DIV
VOUT
2V/DIV
CLKOUT
2V/DIV
500ns/DIV
8650s1 G38
8650s1 G40
1ns/DIV
100ms/DIV
VIN = 12V
CH1 = 5VOUT
CH2 = 3.3VOUT
SYNC = FLOAT
8650s1 G40
5Ω LOAD
(1A IN REGULATION)
Case Temperature Rise
120
Burst Mode OPERATION
(SYNC = 0V)
5Ω LOAD
(1A IN REGULATION)
8650s1 G41
CASE TEMPERATURE RISE (°C)
VOUT
2V/DIV
100ms/DIV
24VIN, LOAD2 = LOAD1
12VIN, LOAD2 = LOAD1
12VIN, LOAD2 = 4A
12VIN, LOAD2 = 0A
110
VIN
2V/DIV
Case Temperature Rise
100
100
90
80
70
60
50
40
30
20
80
70
60
50
40
30
20
10
10
0
DC2407A DEMO BOARD
VIN1,2 = 12V, fSW = 2MHz
VOUT1 = 5V, VOUT2 = 3.3V
90
CASE TEMPERATURE RISE (°C)
Start-Up Dropout Performance
0
1
2
3
4
LOAD1 CURRENT (A)
5
6
8650s1 G42
DC2407A DEMO BOARD
VOUT1 = 5V, VOUT2 = 3.3V, fSW = 2MHz
8
8650s1 G37
0
0
0.2
0.4
0.6
0.8
DUTY CYCLE OF PULSED LOAD
1
8650s1 G43
CH1 = 0.5A STANDBY, 6A PULSED; CH2 = 0A DC
CH1 = 0.5A STANDBY, 6A PULSED; CH2 = 4A DC
CH1 = CH2 = 2A STANDBY, 6A PULSED
Rev 0
For more information www.analog.com
LT8650S-1
TYPICAL PERFORMANCE CHARACTERISTICS
60
Radiated EMI Performance (CISPR25 Radiated
Emission Test with Class 5 Peak Limits)
Conducted EMI Performance
50
40
VERTICAL POLARIZATION
45 PEAK DETECTOR
40
30
35
AMPLITUDE (dBµV/m)
AMPLITUDE (dBµV/m)
50
20
10
0
–10
–20
–40
0
3
6
9
12
15
18
FREQUENCY (MHz)
21
24
27
25
20
15
10
5
SPREAD SPECTRUM MODE
FIXED FREQUENCY MODE
–30
30
CLASS 5 PEAK LIMIT
SPREAD SPECTRUM MODE
FIXED FREQUENCY MODE
0
30
8650s1 G44
DC2407A DEMO BOARD
(WITH EMI FILTER INSTALLED)
12V INPUT TO 5V OUTPUT1 AT 4A AND 3.3V OUTPUT2 AT 4A, fSW = 2MHz
–5
0
100
200
300
400
500
600
FREQUENCY (MHz)
700
800
900
1000
8650s1 G45
DC2407A DEMO BOARD
(WITH EMI FILTER INSTALLED)
12V INPUT TO 5V OUTPUT1 AT 4A AND 3.3V OUTPUT2 AT 4A, fSW = 2MHz
Rev 0
For more information www.analog.com
9
LT8650S-1
PIN FUNCTIONS
RT (Pin 1): A resistor is tied between RT and ground to
set the switching frequency.
VIN1 (Pin 4, 5): The VIN1 pin supplies current to the
LT8650S-1 internal circuitry and to the internal top side
power switch of channel 1. This pin must be locally
bypassed. Be sure to place the positive terminal of the
input capacitor as close as possible to the VIN1 pin, and
the negative capacitor terminal as close as possible to
the GND pins.
VIN2 (Pin 7, 8): The VIN2 pin supplies current to the internal
top side power switch of channel 2. This pin must be locally bypassed. Be sure to place the positive terminal of
the input capacitor as close as possible to the VIN2 pin,
and the negative capacitor terminal as close as possible
to the GND pins. This input is capable of operating from
a different supply than VIN1. VIN1 must be present to run
channel 2.
EN/UV1 (Pin 11): Channel 1 of the LT8650S-1 is shut down
when this pin is low and active when this pin is high. The
hysteretic threshold voltage is 0.77V going up and 0.74V
going down. Tie to VIN1 if the shutdown feature is not
used. An external resistor divider from VIN1 can be used
to program a VIN threshold below which channel 1 of the
LT8650S-1 will shut down. Do not float this pin.
EN/UV2 (Pin 12): Channel 2 of the LT8650S-1 is shut
down when this pin is low and active when this pin is high.
The hysteretic threshold voltage is 0.77V going up and
0.74V going down. Tie to VIN2 if shutdown feature is not
used. An external resistor divider from VIN2 can be used
to program a VIN threshold below which channel 2 of the
LT8650S-1 will shut down. Do not float this pin.
TEMP (Pin 13): Temperature Output Pin. This pin outputs
a voltage proportional to junction temperature. The pin is
250mV for 25°C and has a slope of 9.5mV/°C. The output
of this pin is not valid during light output loads on both
channels while in Burst Mode operation. Put the LT8650S-1
in forced continuous mode for the TEMP output to be valid
across the entire output load range. See the Applications
Information section for more information.
PG1 (Pin 14): The PG1 pin is the open-drain output of an
internal comparator. PG1 remains low until the FB1 pin
10
is within ±7.5% of the final regulation voltage, and there
are no fault conditions. PG1 is pulled low during VIN1
UVLO, VCC UVLO, Thermal Shutdown, or when both EN/
UV pins are low.
PG2 (Pin 15): The PG2 pin is the open-drain output of an
internal comparator. PG2 remains low until the FB2 pin
is within ±7.5% of the final regulation voltage, and there
are no fault conditions. PG2 is pulled low during VIN1
UVLO, VCC UVLO, Thermal Shutdown, or when both EN/
UV pins are low.
SYNC (Pin 16): External Clock Synchronization Input.
Ground this pin for low ripple Burst Mode operation at
low output loads. Apply a DC voltage of 2.8V to 4V or tie
to VCC for forced continuous mode with spread spectrum
modulation. Float the SYNC pin for forced continuous mode
without spread spectrum modulation. When in forced continuous mode, the IQ will increase to several hundred µA.
Apply a clock source to the SYNC pin for synchronization
to an external frequency. The LT8650S-1 will be in forced
continuous mode when an external frequency is applied.
CLKOUT (Pin 17): In forced continuous mode, the CLKOUT
pin provides a 50% duty cycle square wave 90 degrees
out of phase with channel 1. This allows synchronization
with other regulators with up to four phases. When an
external clock is applied to the SYNC pin, the CLKOUT pin
will output a waveform with the same phase, duty cycle,
and frequency as the SYNC waveform. In burst mode,
the CLKOUT pin will be low. Float this pin if the CLKOUT
function is not used.
BST2 (Pin 18): This pin is used to provide a drive voltage,
higher than the input voltage, to the top side power switch
of channel 2. Place a 0.1µF boost capacitor as close as
possible to the IC.
SW2 (Pin 19, 20): The SW2 pin is the output of the channel 2 internal power switches. Tie these pins together and
connect them to the inductor and boost capacitor. This node
should be kept small on the PCB for good performance.
SW1 (Pin 22, 23): The SW1 pin is the output of the channel 1 internal power switches. Tie these pins together and
connect them to the inductor and boost capacitor. This node
should be kept small on the PCB for good performance.
Rev 0
For more information www.analog.com
LT8650S-1
PIN FUNCTIONS
BST1 (Pin 24): This pin is used to provide a drive voltage,
higher than the input voltage, to the top side power switch
of channel 1. Place a 0.1µF boost capacitor as close as
possible to the IC.
VCC (Pin 25): Internal Regulator Bypass Pin. The internal
power drivers and control circuits are powered from this
voltage. VCC current will be supplied from BIAS if VBIAS >
3.1V, otherwise current will be drawn from VIN1. Voltage
on VCC will vary between 2.8V and 3.3V when VBIAS is
between 3.0V and 3.5V. Decouple this pin to ground with
at least a 1μF low ESR ceramic capacitor. Do not load the
VCC pin with external circuitry.
BIAS (Pin 26): The internal regulator will draw current from
BIAS instead of VIN1 when BIAS is tied to a voltage higher
than 3.1V. For output voltages of 3.3V and above this pin
should be tied to VOUT. If this pin is tied to a supply other
than VOUT use a 1µF local bypass capacitor on this pin.
VC1 (Pin 27): Channel 1 Error Amplifier Output and
Switching Regulator Compensation Pin. Connect this pin
to appropriate external components to compensate the
regulator loop frequency response. Connect this pin to
VCC to use the default internal compensation. If internal
compensation is used, the burst mode quiescent current
is only 2.5µA for channel 1. If external compensation is
used, the burst mode quiescent current is increased to
about 50µA for channel 1.
FB1 (Pin 28): The LT8650S-1 regulates the FB1 pin to
800mV. Connect the feedback resistor divider tap to this pin.
SS1 (Pin 29): Channel 1 Output Tracking and Soft-Start
Pin. This pin allows user control of output voltage ramp
rate during startup. A SS1 voltage below 0.8V forces the
LT8650S-1 to regulate the FB1 pin to equal the SS1 pin
voltage. When SS1 is above 0.8V, the tracking function is
disabled and the internal reference resumes control of the
error amplifier. An internal 2μA pull-up current from VCC
on this pin allows a capacitor to program output voltage
slew rate. This pin is pulled to ground with an internal
200Ω MOSFET during shutdown and fault conditions; use
a series resistor if driving from a low impedance output.
This pin may be left floating if the soft-start feature is not
being used.
SS2 (Pin 30): Channel 2 Output Tracking and Soft-Start
Pin. This pin allows user control of output voltage ramp
rate during startup. A SS2 voltage below 0.8V forces the
LT8650S-1 to regulate the FB2 pin to equal the SS2 pin
voltage. When SS2 is above 0.8V, the tracking function is
disabled and the internal reference resumes control of the
error amplifier. An internal 2μA pull-up current from VCC
on this pin allows a capacitor to program output voltage
slew rate. This pin is pulled to ground with an internal
200Ω MOSFET during shutdown and fault conditions; use
a series resistor if driving from a low impedance output.
This pin may be left floating if the soft-start feature is not
being used.
FB2 (Pin 31): The LT8650S-1 regulates the FB2 pin to
800mV. Connect the feedback resistor divider tap to this pin.
VC2 (Pin 32): Channel 2 Error Amplifier Output and
Switching Regulator Compensation Pin. Connect this pin
to appropriate external components to compensate the
regulator loop frequency response. Connect this pin to
VCC to use the default internal compensation. If internal
compensation is used, the burst mode quiescent current
is only 2.5µA for channel 2. If external compensation is
used, the burst mode quiescent current is increased to
about 50µA for channel 2.
GND (Pin 2, 10, Exposed Pad Pins 33–38): LT8650S-1
System Ground. Connect these pins to the system ground
and the board ground plane. Place the negative terminal of
the input capacitors as close to the GND pins as possible.
The exposed pad must be soldered to the PCB in order to
lower the thermal resistance.
Rev 0
For more information www.analog.com
11
LT8650S-1
BLOCK DIAGRAM
TEMP
VIN1
R5
0.74V
EN/UV1
+
–
SHDN1
R6
VIN2
R7
EN/UV2
R8
VC1
0.74V
RC1
+
–
SHDN2
SHDN1
TSD
VIN1 UVLO
CC1
PG1
VCC – 0.2V
VCC UVLO
R1
VCC
C1
10nF
×2
+
–
+
VC1
ERROR
AMP
BURST
LOGIC
SWITCH
LOGIC
AND ANTISHOOT
THROUGH
DRIVER
CIN1
CVCC
SW1
L1
VOUT1
COUT1
VCC
R2
VIN1
VCC
BST1
0.8V
±7.5V
FB1
VIN1
–
+
VOUT1
CFF1
BIAS
INTERNAL
REFERENCE AND
3.4V REGULATOR
GND
2µA
SS1
SHDN1
TSD
VIN1 UVLO
CSS1
SLOPE
COMP
RT
RT
CLKOUT
OSCILLATOR
300kHz TO 3MHz
SYNC
SLOPE
COMP
VIN2
VC2
RC2
SHDN2
TSD
VIN1 UVLO
CC2
PG2
VCC – 0.2V
VCC UVLO
R3
±7.5V
FB2
VCC
+
–
+
VC2
BURST
LOGIC
SWITCH
LOGIC
AND ANTISHOOT
THROUGH
VCC
R4
VIN2
CIN2
BST2
0.8V
VOUT2
CFF2
–
+
C2
10nF
×2
DRIVER
SW2
L2
VOUT2
COUT2
GND
2µA
SS2
CSS2
SHDN2
TSD
VIN1 UVLO
GND
8650s1 BD
12
Rev 0
For more information www.analog.com
LT8650S-1
OPERATION
Foreword
The LT8650S-1 is a dual monolithic step down regulator. The two channels are the same in terms of current
capability and power switch size. The following sections
describe the operation of channel 1 and common circuits.
They will highlight channel 2 differences and interactions
only when relevant. To simplify the application, both VIN1
and VIN2 are assumed to be connected to the same input
supply. However, note that VIN1 must be greater than 3V
for either channel to operate.
Operation
The LT8650S-1 is a dual monolithic, constant frequency,
peak current mode step-down DC/DC converter. An oscillator, with frequency set using a resistor on the RT pin,
turns on the internal top power switch at the beginning of
each clock cycle. Current in the inductor then increases
until the top switch current comparator trips and turns
off the top power switch. The peak inductor current at
which the top switch turns off is controlled by the voltage
on the VC node. The error amplifier servos the VC node
by comparing the voltage on the VFB pin with an internal
0.8V reference. When the load current increases it causes
a reduction in the feedback voltage relative to the reference
leading the error amplifier to raise the VC voltage until the
average inductor current matches the new load current.
When the top power switch turns off, the synchronous
power switch turns on until the next clock cycle begins or
inductor current falls to zero when not in forced continuous mode (FCM). If overload conditions result in more
than the bottom NMOS current limit flowing through the
bottom switch, the next clock cycle will be delayed until
switch current returns to a safe level.
The S in LT8650S-1 refers to the second generation Silent
Switcher technology. This technology allows fast switching
edges for high efficiency at high switching frequencies,
while simultaneously achieving good EMI performance.
This includes the integration of ceramic capacitors into the
package for VIN1 and VIN2 (C1 to C2 in the Block Diagram).
These caps keep all the fast AC current loops small, which
improves EMI performance.
If either EN/UV pin is low, the corresponding channel is
shut down. If both EN/UV pins are low, the LT8650S-1 is
fully shut down and draws 1.7µA from the input supply.
When the EN/UV pins are above 0.74V, corresponding
switching regulators will become active. 3.7μA is supplied
by VIN1 to common bias circuits for both channels.
Each channel can independently enter Burst Mode operation to optimize efficiency at light load. Between bursts,
all circuitry associated with controlling the output switch
is shut down, reducing the channel’s contribution to
input supply current. In a typical application, 6.2μA will
be consumed from input supply when regulating both
channels with no load. Ground the SYNC pin for Burst
Mode operation, float it for forced continuous mode (FCM)
or apply a DC voltage from 2.8V to 4V to use FCM with
spread spectrum modulation (SSM). If a clock is applied
to the SYNC pin both channels will synchronize to the
external clock frequency and operate in FCM. While in
FCM the oscillator operates continuously and rising SW
transitions are aligned to the clock. During light loads,
the inductor current is allowed to go negative to maintain
the programmed switching frequency. Minimum current
limits for both power switches are enforced to prevent
large negative inductor current from flowing back to the
input. SSM dithers the switching frequency from the
programmed value set by the RT pin up to 20% higher
than the programmed value to spread out the switching
energy in the frequency domain. The CLKOUT pin has
no output in Burst Mode, but outputs a square wave 90
degrees phase shifted from channel 1 when in FCM. If a
clock is applied to the SYNC pin, the CLKOUT pin has the
same phase and duty cycle as the external clock.
To improve efficiency across all loads, supply current to
internal circuitry can be sourced from the BIAS pin when
biased at 3.3V or above. Otherwise, the internal circuitry
will draw current exclusively from VIN1. The BIAS pin
should be connected to the lowest VOUT programmed at
3.3V or above.
The VC pin allows the loop compensation of the switching regulator to be optimized based on the programmed
switching frequency. Internal compensation can be se-
Rev 0
For more information www.analog.com
13
LT8650S-1
OPERATION
lected by connecting the VC pin to VCC, which simplifies
the application circuit. External compensation improves
the transient response at the expense of about 50µA more
quiescent current per channel.
Comparators monitoring the FB pin voltage will pull the
corresponding PG pin low if the output voltage varies
more than ±7.5% (typical) from the regulation voltage or
if a fault condition is present.
The voltage present at the TEMP pin is proportional to the
average die temperature of the LT8650S-1. The TEMP pin
will be 250mV for a die temperature of 25°C and will have
a slope of 9.5mV/°C
14
Tracking soft-start is implemented by providing constant
current via the SS pin to an external soft-start capacitor
to generate a voltage ramp. FB voltage is regulated to
the voltage at the SS pin until it exceeds 0.8V; FB is then
regulated to the reference 0.8V. When the SS pin is below
40mV, the corresponding switching regulator will stop
switching. The SS capacitor is reset during shutdown,
VIN1 undervoltage, or thermal shutdown.
Both channels are designed for output currents up to 6A,
but thermal considerations practically limit the output
currents to 4A of continuous current from each channel
simultaneously. Channel 1 has a minimum VIN1 requirement of 3V, channel 2 can operate with no minimum VIN2
provided the minimum VIN1 has been satisfied.
Rev 0
For more information www.analog.com
LT8650S-1
APPLICATIONS INFORMATION
2.25
Achieving Ultralow Quiescent Current
SWITCHING FREQUENCY (MHz)
To enhance efficiency at light loads, the LT8650S-1 operates in low ripple Burst Mode operation, which keeps
the output capacitor charged to the desired output voltage while minimizing the input quiescent current and
minimizing output voltage ripple. 3.7μA is supplied by
VIN1 to common bias circuits. In Burst Mode operation
the LT8650S-1 delivers single small pulses of current to
the output capacitor followed by sleep periods where the
output power is supplied by the output capacitor. While in
sleep mode both channels consume a combined 6.2μA.
For some applications it is desirable to select forced continuous mode (FCM) to maintain full switching frequency
down to zero output load. See Forced Continuous Mode
section.
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0
0.20
0.40 0.60 0.80
LOAD CURRENT (A)
1.00
Figure 1. Burst Frequency
As the output load decreases, the frequency of single current pulses decreases (see Figure 1) and the percentage
of time the LT8650S-1 is in sleep mode increases, resulting in much higher light load efficiency than for typical
converters. By maximizing the time between pulses, the
converter quiescent current approaches 6.2µA for a typical application when there is no output load. Therefore,
to optimize the quiescent current performance at light
loads, the current in the feedback resistor divider must
be minimized as it appears to the output as load current.
While in Burst Mode operation the current limit of the top
switch is approximately 1.2A resulting in output voltage
ripple shown in Figure 2. Increasing the output capacitance
will decrease the output ripple proportionally. As load ramps
upward from zero the switching frequency will increase
but only up to the switching frequency programmed by
the resistor at the RT pin as shown in Figure 1. The output
load at which the LT8650S-1 reaches the programmed
frequency varies based on input voltage, output voltage,
and inductor choice.
VIN1 = VIN2 = 12V
VOUT = 5V
SYNC = 0V
RT = 15kΩ
L = 1.0µH
2.00
1.20
LT8650s1 F01
SW
5V/DIV
IL
1A/DIV
2µs/DIV
LT8650s1 F02
12VIN TO 5VOUT AT 100mA
SYNC = 0V
Figure 2. Burst Mode Operation
FB Resistor Network
The output voltage is programmed with a resistor divider
between the output and the FB pin (R1-2 for channel 1, R3-4
for channel 2). Choose the resistor values according to:
⎛V
⎞
R1= R2 ⎜ OUT1 – 1⎟
⎝ 0.8V ⎠
Reference designators refer to the Block Diagram. 1%
resistors are recommended to maintain output voltage
accuracy.
Rev 0
For more information www.analog.com
15
LT8650S-1
APPLICATIONS INFORMATION
If low input quiescent current and good light-load efficiency
are desired, use large resistor values for the FB resistor
divider. The current flowing in the divider acts as a load
current, and will increase the no-load input current to the
converter, which is approximately:
The two channels of the LT8650S-1 operate 180° out of
phase to avoid aligned switching edge noise and reduce
input current ripple.
Table 1. SW Frequency vs RT Value
fSW (MHz)
RT (kΩ)
0.3
137
0.4
100
0.5
78.7
where 3.7µA is the quiescent current of channel 1 and
common circuitries, the second term is the current in the
feedback divider reflected to the input of channel 1 operating at its light load efficiency n. For a 3.3V application
with R1 = 1M and R2 = 316k, the feedback divider draws
2.5µA. With VIN = 12V and n = 80%, this adds 0.9µA to the
3.7µA quiescent current resulting in 4.6µA no-load current
from the 12V supply. Note that this equation implies that
the no-load current is a function of VIN; this is plotted in
the Typical Performance Characteristics section.
0.6
63.4
0.8
46.4
1.0
35.7
1.2
28.7
1.4
23.7
1.6
20
1.8
17.4
2.0
15
2.2
13
2.5
11
A similar calculation can be done to determine the input
current contribution from the channel 2 feedback resistors. For a 5V application with R3 = 1M, R4 = 191k, VIN
= 12V, and h = 80%, this adds 2.2µA to the input current
resulting in a total of 6.8µA with both channels on.
3.0
8.06
⎞
⎛ V
⎞⎛V
IQ = 3.7µA + ⎜ OUT1 ⎟ ⎜ OUT1 ⎟
⎝ R1+R2 ⎠ ⎝ VIN1 ⎠
⎛ 1⎞
⎜⎝ ⎟⎠
n
For a typical FB resistor of 1M, a 4.7pF to 10pF phase-lead
capacitor should be connected from VOUT to FB.
Setting the Switching Frequency
The LT8650S-1 uses a constant frequency PWM architecture that can be programmed to switch from 300kHz to
3MHz by using a resistor tied from the RT pin to ground.
Table 1 shows the necessary RT value for a desired switching frequency.
The RT resistor required for a desired switching frequency
can be calculated using:
RT =
41.7
fSW
– 5.8
where RT is in kΩ and fSW is the desired switching frequency in MHz.
16
Operating Frequency Selection and Trade-Offs
Selection of the operating frequency is a trade-off between
efficiency, component size, and input voltage range. The
advantage of high frequency operation is that smaller inductor and capacitor values may be used. The disadvantages
are lower efficiency and a smaller input voltage range.
The highest switching frequency (fSW(MAX)) for a given
application can be calculated as follows:
fSW(MAX) =
VOUT + VSW(BOT)
(
t ON(MIN) VIN – VSW(TOP) + VSW(BOT)
)
where VIN is the typical input voltage, VOUT is the output
voltage, VSW(TOP) and VSW(BOT) are the internal switch
drops (~0.3V, ~0.12V, respectively at maximum load) and
tON(MIN) is the minimum top switch on-time of 60ns (see
the Electrical Characteristics). This equation shows that a
slower switching frequency is necessary to accommodate
a high VIN/VOUT ratio. Choose the switching frequency
based on which channel has the lower frequency constraint.
Rev 0
For more information www.analog.com
LT8650S-1
APPLICATIONS INFORMATION
For transient operation, VIN may go as high as the absolute
maximum rating of 42V regardless of the RT value, however
the LT8650S-1 will reduce switching frequency on each
channel independently as necessary to maintain control
of inductor current to assure safe operation.
In Burst Mode, the LT8650S-1 is capable of a maximum
duty cycle of greater than 99%, and the VIN to VOUT dropout
is limited by the RDS(ON) of the top switch. In this mode the
channel that enters dropout skips switch cycles, resulting
in a lower switching frequency. In forced continuous mode,
the LT8650S-1 will not skip cycles to achieve a higher duty
cycle. The part will maintain the programmed switching
frequency and the dropout voltage will be larger due to
the smaller maximum duty cycle.
For applications that cannot allow deviation from the programmed switching frequency at low VIN/VOUT ratios use
the following formula to set switching frequency:
VIN(MIN) =
VOUT + VSW(BOT)
1– fSW • t OFF(MIN)
– VSW(BOT) + VSW(TOP)
where VIN(MIN) is the minimum input voltage without
skipped cycles, VOUT is the output voltage, VSW(TOP) and
VSW(BOT) are the internal switch drops (~0.3V, ~0.12V,
respectively at maximum load), fSW is the switching frequency (set by RT), and tOFF(MIN) is the minimum switch
off-time. Note that higher switching frequency will increase
the minimum input voltage below which cycles will be
dropped to achieve higher duty cycle.
Note there is no minimum VIN2 voltage requirement as it
does not supply the internal common bias circuits, making
the channel 2 uniquely capable of operating from very low
input voltages as long as VIN1 has a supply of 3V or greater.
Inductor Selection and Maximum Output Current
The LT8650S-1 is designed to minimize solution size by
allowing the inductor to be chosen based on the output
load requirements of the application. During overload or
short-circuit conditions the LT8650S-1 safely tolerates
operation with a saturated inductor through the use of a
high speed peak-current mode architecture.
A good first choice for the inductor value is:
L1,2 =
VOUT1,2 + VSW(BOT)
2fSW
where fSW is the switching frequency in MHz, VOUT is the
output voltage, VSW(BOT) is the bottom switch drop (~0.12V)
and L is the inductor value in μH. To avoid overheating and
poor efficiency, an inductor must be chosen with an RMS
current rating that is greater than the maximum expected
output load of the application. In addition, the saturation
current (typically labeled ISAT) rating of the inductor must
be higher than the load current plus 1/2 of in inductor
ripple current:
1
IL(PEAK) =ILOAD(MAX) + ΔIL
2
where ∆IL is the inductor ripple current as calculated in
Equation 1 and ILOAD(MAX) is the maximum output load
for a given application.
As a quick example, an application requiring 1A output
should use an inductor with an RMS rating of greater than
1A and an ISAT of greater than 1.3A. During long duration
overload or short-circuit conditions, the inductor RMS rating requirement must be greater to avoid overheating of the
inductor. To keep the efficiency high, the series resistance
(DCR) should be less than 0.04Ω, and the core material
should be intended for high frequency applications.
The LT8650S-1 limits the peak switch current in order to
protect the switches and the system from overload faults.
The top switch current limit (ILIM) is at least 10A at low
duty cycles and decreases linearly to 7A at DC = 0.8. The
inductor value must then be sufficient to supply the desired
maximum output current (IOUT(MAX)), which is a function
of the switch current limit (ILIM) and the ripple current.
IOUT(MAX) =ILIM –
ΔIL
2
The peak-to-peak ripple current in the inductor can be
calculated as follows:
IL =
VOUT
V
• 1– OUT (1)
L • fSW
VIN(MAX)
Rev 0
For more information www.analog.com
17
LT8650S-1
APPLICATIONS INFORMATION
where fSW is the switching frequency of the LT8650S-1,
and L is the value of the inductor. Therefore, the maximum
output current that the LT8650S-1 will deliver depends on
the switch current limit, the inductor value, and the input
and output voltages.
Each channel has a secondary bottom switch current limit.
After the top switch has turned off, the bottom switch carries
the inductor current. If for any reason the inductor current
is too high, the bottom switch will remain on, delaying the
top switch turning on until the inductor current returns to
a safe level. This level is specified as the Bottom NMOS
Current Limit, and is independent of duty cycle. Maximum
output current in the application circuit is limited to this
valley current plus one half of the inductor ripple current.
In most cases current limit is enforced by the top switch.
The bottom switch limit controls the inductor current when
the minimum on-time condition is violated (high input
voltage, high frequency or saturated inductor).
The bottom switch current limit is designed to be equal to
the peak current limit to avoid any contribution to maximum
rated current of the LT8650S-1.
For more information about maximum output current and
discontinuous operation, see the Analog Devices Application Note 44.
Finally, for duty cycles greater than 50% (VOUT/VIN > 0.5),
a minimum inductance is required to avoid sub-harmonic
oscillation. See Application Note 19.
Table 2. Inductor Manufacturers
VENDOR
URL
Coilcraft
www.coilcraft.com
Sumida
www.sumida.com
Toko
www.toko.com
Würth Elektronik
www.we-online.com
Vishay
www.vishay.com
Input Capacitor
Bypass the input of the LT8650S-1 circuit with a ceramic
capacitor of X7R or X5R type placed as close as possible
to the VIN and GND pins. Y5V types have poor performance
over temperature and applied voltage, and should not be
used. A 4.7μF to 10μF ceramic capacitor is adequate to
18
bypass the LT8650S-1 and will easily handle the ripple
current. Note that larger input capacitance is required
when a lower switching frequency is used. If the input
power source has high impedance, or there is significant
inductance due to long wires or cables, additional bulk
capacitance may be necessary. This can be provided with
a low performance electrolytic capacitor.
Step-down regulators draw current from the input supply in pulses with very fast rise and fall times. The input
capacitor is required to reduce the resulting voltage ripple
at the LT8650S-1 and to force this very high frequency
switching current into a tight local loop, minimizing EMI.
Typically a 0.1µF capacitor in a small 0402 case size is
placed as close as possible to the LT8650S-1 and a larger
bulk ceramic is added for more capacitance (see the PCB
Layout section). A second precaution regarding the ceramic
input capacitor concerns the maximum input voltage rating
of the LT8650S-1. A ceramic input capacitor combined
with trace or cable inductance forms a high quality (under
damped) tank circuit. If the LT8650S-1 circuit is plugged
into a live supply, the input voltage can ring to twice its
nominal value, possibly exceeding the LT8650S-1’s voltage rating. This situation is easily avoided (see the Analog
Devices Application Note 88).
Output Capacitor and Output Ripple
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
the LT8650S-1 to produce the DC output. In this role it
determines the output ripple, thus low impedance at the
switching frequency is important. The second function is to
store energy in order to satisfy transient loads and stabilize
the LT8650S-1’s control loop. Ceramic capacitors have
very low equivalent series resistance (ESR) and provide
the best ripple performance. For good starting values, see
the Typical Applications section.
Use X5R or X7R types. This choice will provide low output
ripple and good transient response. Transient performance
can be improved with a higher value output capacitor and
the addition of a feed forward capacitor placed between
VOUT and FB. Increasing the output capacitance will also
decrease the output voltage ripple. A lower value of output
capacitor can be used to save space and cost but transient
Rev 0
For more information www.analog.com
LT8650S-1
APPLICATIONS INFORMATION
performance will suffer and may cause loop instability. See
the Typical Applications in this data sheet for suggested
capacitor values.
When choosing a capacitor, special attention should be
given to the data sheet to calculate the effective capacitance
under the relevant operating conditions of voltage bias and
temperature. A physically larger capacitor or one with a
higher voltage rating may be required.
switching regulator draws constant power from the source,
so source current increases as source voltage drops. This
looks like a negative resistance load to the source and can
cause the source to current limit or latch low under low
source voltage conditions. The VIN(EN) threshold prevents
the regulator from operating at source voltages where the
problems might occur. This threshold can be adjusted by
setting the values R5 and R6 (R7 and R8 for channel 2)
such that they satisfy the following equation:
Ceramic Capacitors
Ceramic capacitors are small, robust and have very low
ESR. However, ceramic capacitors can cause problems
when used with the LT8650S-1 due to their piezoelectric
nature. When in Burst Mode operation, the LT8650S-1’s
switching frequency depends on the load current, and at
very light loads the LT8650S-1 can excite the ceramic
capacitor at audio frequencies, generating audible noise.
Since the LT8650S-1 operates at a lower current limit
during Burst Mode operation, the noise is typically very
quiet to a casual ear. If this is unacceptable, use a high
performance tantalum or electrolytic capacitor at the
output. Low noise ceramic capacitors are also available.
Table 3. Ceramic Capacitor Manufacturers
MANUFACTURER
WEB
Taiyo Yuden
www.t-yuden.com
AVX
www.avxcorp.com
Murata
www.murata.com
TDK
www.tdk.com
Enable Pin
The LT8650S-1 is in shutdown when both EN/UV pins
are low and active when either pin is high. The rising
threshold of the EN/UV comparator is 0.74V, with 30mV
of hysteresis. The EN/UV pins can be tied to VIN if the
shutdown feature is not used, or tied to a logic level if
shutdown control is required.
Adding a resistor divider from VIN to EN/UV programs the
LT8650S-1 to operate only when VIN is above a desired
voltage (see the Block Diagram). Typically, this threshold,
VIN(EN), is used in situations where the input supply is current limited, or has a relatively high source resistance. A
⎛ R5 ⎞
VIN(EN) = ⎜ +1⎟ • 0.74V
⎝ R6 ⎠
where the corresponding channel will remain off until VIN is
above VIN(EN). Due to the comparator’s hysteresis, switching will not stop until the input falls slightly below VIN(EN).
When operating in Burst Mode operation for light load
currents, the current through the VIN(EN) resistor network
can easily be greater than the supply current consumed
by the LT8650S-1. Therefore, the VIN(EN) resistors should
be large to minimize their effect on efficiency at low loads.
VCC Regulator
An internal low dropout (LDO) regulator produces the 3.4V
supply from VIN1 that powers the drivers and the internal
bias circuitry. For this reason, VIN1 must be present and
valid to use either channel. The VCC can supply enough
current for the LT8650S-1’s circuitry and must be bypassed
to ground with a 1μF ceramic capacitor. Good bypassing is
necessary to supply the high transient currents required
by the power MOSFET gate drivers. To improve efficiency
the internal LDO can also draw current from the BIAS pin
when the BIAS pin is at 3.1V or higher. Typically the BIAS
pin can be tied to the lowest output or external supply
above 3.1V. If BIAS is connected to a supply other than
VOUT, be sure to bypass with a local ceramic capacitor. If
the BIAS pin is below 3V, the internal LDO will consume
current from VIN1.
Applications with high input voltage and high switching
frequency where the internal LDO pulls current from VIN1
will increase die temperature because of the higher power
dissipation across the LDO. Do not connect an external
load to the VCC pin.
Rev 0
For more information www.analog.com
19
LT8650S-1
APPLICATIONS INFORMATION
Frequency Compensation
The LT8650S-1 has VC pins which can be used to optimize
the loop compensation of each channel. If the VC pins are
shorted to VCC, then internal compensation is used. This
simplifies the circuit design and minimizes the quiescent
current, but since the internal compensation has to be
stable across the 300kHz to 3MHz range of switching
frequencies, the internal compensation will not be optimal, especially at high switching frequencies. If the best
transient response is desired, an external compensation
network can be connected to the VC pin, which usually
consists of a series resistor and capacitor (see RC and CC
in the Block Diagram).
Designing the compensation network is a bit complicated
and the best values depend on the application and in particular the type of output capacitor. A practical approach
is to start with one of the circuits in the data sheet that
is similar to your application and tune the compensation
network to optimize the performance. LTspice® simulations
can help in this process. Stability should then be checked
across all operating conditions, including load current,
input voltage, and temperature.
Figure 3 shows an equivalent circuit for the LT8650S-1
control loop. The error amplifier is a transconductance
amplifier with finite output impedance. The power section,
consisting of the modulator, power switches, and inductor,
is modeled as a transconductance amplifier generating an
output current proportional to the voltage at the VC pin.
Note that the output capacitor integrates this current and
that the capacitor on the VC pin (CC) integrates the error
amplifier output current, resulting in two poles in the loop.
A zero is required and comes from a resistor RC in series
with CC. This simple model works well as long as the value
of the inductor is not too high and the loop crossover
frequency is much lower than the switching frequency. A
phase lead capacitor (CPL) across the feedback divider can
be used to improve the transient response and is required
to cancel the parasitic pole caused by the feedback node
to ground capacitance.
Figure 4a shows the transient response for the front page
application which uses internal compensation. Figure 4b
shows the improved transient response of the same application when a 14kΩ RC and 220pF CC compensation
network is used. Use of an external compensation network
increases the quiescent current by about 50µA per channel.
ILOAD
2A/DIV
VOUT
100mV/DIV
20µs/DIV
2A TO 4A TRANSIENT
3.3VOUT
COUT = 47µF ×2
FCM, fSW = 2MHz
LT8650s1 F04a
a)
LT8650S-1
CURRENT MODE
POWER STAGE
ILOAD
2A/DIV
OUTPUT
VOUT
100mV/DIV
CPL
gm = 9.6S
R1
gm = 0.9mS
RC
1.25M
CF
+
–
VC
FB
C1
20µs/DIV
2A TO 4A TRANSIENT
3.3VOUT
COUT = 47µF ×2
FCM, fSW = 2MHz
CC = 220pF, RC = 14kΩ
0.8V
R2
CC
8650s1 F03
b)
Figure 4 Transient Response
Figure 3. Model for Loop Response
20
LT8650s1 F04b
Rev 0
For more information www.analog.com
LT8650S-1
APPLICATIONS INFORMATION
Output Voltage Tracking and Soft-Start
Output Power Good
The LT8650S-1 allows the user to program its output voltage ramp rate with the SS pin. An internal 2μA current pulls
up the SS pin to VCC. Putting an external capacitor on SS
enables soft starting the output to prevent current surge
on the input supply. During the soft-start ramp the output
voltage will proportionally track the SS pin voltage. For
output tracking applications, SS can be externally driven
by another voltage source. From 0V to 0.04V, the SS pin
will stop the corresponding channel from switching, thus
allowing the SS pin to be used as a shutdown pin. From
0.04V to 0.8V, the SS voltage will override the internal
0.8V reference input to the error amplifier, thus regulating
the FB pin voltage to that of SS pin (Figure 5). When SS is
above 0.8V, tracking is disabled and the feedback voltage
will regulate to the internal reference voltage. The SS pin
may be left floating if the function is not needed. Note that
in both Burst Mode and forced continuous mode (FCM)
the LT8650S-1 will not discharge the output to regulate
to a lower SS voltage. This is achieved by disabling FCM
when the SS voltage is below 2V.
When the LT8650S-1’s output voltage is within the ±7.5%
window of the regulation point, which is a FB voltage in
the range of 0.74V to 0.86V (typical), the output voltage
is considered good and the open-drain PG pin goes high
impedance and is typically pulled high with an external
resistor. Otherwise, the internal pull-down device will pull
the PG pin low. To prevent glitching both the upper and
lower thresholds include 0.3% of hysteresis.
In Burst Mode operation (SYNC low), an active pull-down
circuit is connected to the SS pin which will discharge the
external soft-start capacitor in the case of fault conditions
and restart the ramp when the faults are cleared. Fault
conditions that clear the soft-start capacitor are the corresponding EN/UV pin below 0.74V, VIN1 voltage falling
too low, or thermal shutdown.
0.8
FB VOLTAGE (V)
Sequencing
Startup sequencing and tracking can be configured in
several ways with the LT8650S-1. One channel can be
required to be valid before enabling the other channel to
sequence their startup order. This can be done by connecting the PG pin of the first channel to either the EN/
UV pin or SS pin of the second channel. The SS pin of
the first channel can also be connected to the EN/UV pin
of the second channel (see Figure 6).
The channels can also be started at the same time where
the output voltages can track in a ratiometric fashion (see
Figure 6).
Paralleling
To increase the possible output current the two channels
can be connected in parallel to the same output. To do this
the VC, SS, and FB pins of each channel are connected
together, while each channel’s SW node is connected to
the common output through its own inductor. External
compensation network must be used when paralleling
outputs. Figure 7 shows an application where the two
channels of one LT8650S-1 regulator are combined to
get one output capable of 8A DC with 12A peak transients.
1.0
0.6
0.4
0.2
0
The PG pin is also actively pulled low during several fault
conditions: corresponding EN/UV pin below 0.74V, VCC
voltage falling too low, VIN1 under voltage, or thermal
shutdown.
0
0.2
0.4
0.6
0.8
SS VOLTAGE (V)
1.0
1.2
8650s1 F05
Figure 5. SS Pin Tracking
Rev 0
For more information www.analog.com
21
LT8650S-1
APPLICATIONS INFORMATION
SEQUENCED
START-UP
SEQUENCED
START-UP
LT8650S-1
EN/UV1
RATIOMETRIC
START-UP
LT8650S-1
VIN1
EN/UV1
EN/UV2
LT8650S-1
VIN1
EN/UV1
VIN1
EN/UV2
EN/UV2
VIN2
PG1
VOUT1
SS1
SS1
PG2
VOUT2
SS2
SS2
SEQUENCED START-UP: SS1 TIED TO EN2
RATIOMETRIC START-UP: SS1 TIED TO SS2
SEQUENCED START-UP: PG1 TIED TO EN2
VOUT1
2V/DIV
VOUT1
2V/DIV
VOUT1
2V/DIV
VOUT2
2V/DIV
VOUT2
2V/DIV
VOUT2
2V/DIV
PG1
5V/DIV
PG1
5V/DIV
PG2
5V/DIV
PG2
5V/DIV
PG1
5V/DIV
PG2
5V/DIV
2ms/DIV
2ms/DIV
2ms/DIV
8650s1 F06
Figure 6. Sequencing and Start-Up Configurations
BST1
0.1µF
VIN
3.8V TO 42V
LT8650S-1
VIN1
4.7µF
×2
BST2
0.1µF
VIN2
1µH
SW1
1µH
SW2
EN/UV1
4.7pF
EN/UV2
1M
47µF
×2
VOUT
3.3V
8A
FB1
SS1
FB2
SS2
VC1
22nF
220pF
VC2
100k
PG1
CLKOUT
PG2
TEMP
BIAS
VCC
RT
GND
316k
15k
SYNC
1µF
15k
8650s1 F07
fSW = 2MHz
Figure 7 Two-Phase Application
22
Rev 0
For more information www.analog.com
LT8650S-1
APPLICATIONS INFORMATION
Synchronization
To select low ripple Burst Mode operation, tie the SYNC pin
below 0.4V (this can be ground or a logic low output). To
select forced continuous mode (FCM), float the SYNC pin.
To select FCM with spread spectrum modulation (SSM),
tie the SYNC pin above 2.8V (SYNC can be tied to VCC).
To synchronize the LT8650S-1 oscillator to an external
frequency connect a square wave (with 20% to 80% duty
cycle) to the SYNC pin. The square wave amplitude should
have valleys that are below 0.4V and peaks above 1.5V
(up to 6V). When synchronized to an external clock the
LT8650S-1 will use FCM.
Channel 1 will synchronize its positive switch edge transitions to the positive edge of the SYNC signal, and channel
2 will synchronize to the negative edge of the SYNC signal.
The LT8650S-1 may be synchronized over a 300kHz to
3MHz range. The RT resistor should be chosen to set the
LT8650S-1 switching frequency equal to or below the
lowest synchronization input. For example, if the synchronization signal will be 500kHz and higher, the RT should
be selected for nominal 500kHz.
The slope compensation is set by the RT value, while the
minimum slope compensation required to avoid subharmonic oscillations is established by the inductor size,
input voltage, and output voltage. Since the synchronization frequency will not change the slopes of the inductor
current waveform, if the inductor is large enough to avoid
subharmonic oscillations at the frequency set by RT, then
the slope compensation will be sufficient for all synchronization frequencies.
A synchronizing signal that incorporates spread spectrum
may reduce EMI. The duty cycle of the SYNC signal can
be used to set the relative phasing of the two channels
for minimizing input ripple.
Forced Continuous Mode
Forced continuous mode (FCM) is activated by either floating the SYNC pin, tying the SYNC pin to VCC, applying a
DC voltage above 2.8V to the SYNC pin, or applying an
external clock to the SYNC pin.
While in FCM discontinuous mode operation is disabled
and the inductor current is allowed to go negative so that
the regulator can switch at the programmed frequency
all the way down to zero output current. This has the
advantage of maintaining the programmed switching
frequency across the entire load range so that the switch
harmonics and EMI are consistent and predictable. The
disadvantage of FCM is that the light load efficiency will
be low compared to Burst Mode operation.
At low input voltages when the part enters dropout, the
programmed switching frequency will be maintained
and off time skipping will not be allowed. This keeps the
switching frequency controlled, but the dropout voltage
will be higher than in burst mode, due to maximum duty
cycle constraints.
The negative inductor current is limited to a maximum of
about –2.5A, so the LT8650S-1 can only sink a maximum
of about –1.3A. This prevents boosting an excessive
amount of current back from the output to the input. FCM
is disabled if the input voltage is greater than 37V to prevent overvoltaging the LT8650S-1 if the input capacitor is
charged when sinking current from the output. Additional
safety features include disabling FCM when the SS pin
voltage is below 1.8V to prevent discharging the output
when starting up into a pre-biased output, and a bottom
FET current limit to prevent over charging the output if
the minimum on time is violated.
Spread Spectrum Modulation
Spread spectrum modulation (SSM) is activated by tying
the SYNC pin to VCC or applying a DC voltage from 2.8V
to 4V to the SYNC pin. SSM reduces the EMI emissions
by modulating the switching frequency between the value
programmed by RT to approximately 20% higher than that
value. The switching frequency is modulated linearly up
and then linearly down at a 5kHz rate. This is an analog
function, so each switching period will be different than
the previous one. For example, when the LT8650S-1 is
programmed to 2MHz and the SSM feature is enabled,
the switching frequency will vary from 2MHz to 2.4MHz
at a 5kHz rate. When in SSM, the part will also operate in
forced continuous mode.
Rev 0
For more information www.analog.com
23
LT8650S-1
APPLICATIONS INFORMATION
Clock Output
Shorted and Reversed Input Protection
The CLKOUT pin outputs a clock which can be used to
synchronous other regulators to the LT8650S-1. In Burst
Mode (SYNC pin low), the CLKOUT pin is grounded. In
forced continuous mode (SYNC pin float or DC high), the
CLKOUT pin outputs a 50% duty cycle clock where the
CLKOUT rising edge is approximately 90 degrees phase
shifted relative to channel 1. If this CLKOUT waveform is
applied to the SYNC pin of another LT8650S-1 regulator,
then four-phase operation can be achieved. If an external
clock is applied to the SYNC pin of the LT8650S-1, then the
CLKOUT pin will output a waveform with the same phasing
and duty cycle as the SYNC pin clock. The low and high
levels of the CLKOUT pin are ground and VCC, respectively.
The drive strength of the CLKOUT pin is several hundred
ohms, so the CLKOUT waveform has rise and fall times
of several tens of ns. The edge rates will be slower if the
CLKOUT trace has extra capacitance.
The LT8650S-1 will tolerate a shorted output. The bottom
switch current is monitored such that if inductor current
is beyond safe levels switching of the top switch will be
delayed until such time as the inductor current falls to
safe levels. Fault condition of one channel will not affect
the operation of the other channel, unless the part goes
into thermal shutdown.
Temperature Monitor Function
The TEMP pin will output a voltage proportional to die
temperature. The TEMP pin typically outputs 250mV for
25°C and has a slope of 9.5mV/°C. Without the aid of an
external circuitry, the TEMP pin output is valid from 20°C
to 150°C (200mV to 1.5V). Do not load the TEMP pin with
more than 100µA. To extend the TEMP pin output below
20°C, connect a resistor from the TEMP pin to a negative
voltage.
As a safeguard, the LT8650S-1 has an additional thermal
shutdown set at a typical value of 165°C. If the thermal
shutdown is exceeded, both channels of the LT8650S-1
will be shutdown until the thermal overload event expires.
It should be noted that the TEMP pin voltage represents
the steady-state, average die temperature and should not
be used to guarantee that maximum junction temperatures
are not exceeded. Instantaneous power along with thermal gradients and time constants may cause portions of
the die to exceed maximum ratings. Be sure to calculate
die temperature rise for steady state (>1 Min) as well as
impulse conditions.
There is another situation to consider in systems where the
output will be held high when the input to the LT8650S-1 is
absent. This may occur in battery charging applications or
in battery backup systems where a battery or some other
supply is ORed with channel 1’s output. If the VIN1 pin is
allowed to float and either EN/UV pin is held high (either
by a logic signal or because it is tied to VIN1), then the
LT8650S-1’s internal circuitry will pull its quiescent current
through its SW1 pin. This is acceptable if the system can
tolerate current draw in this state. If both EN/UV pins are
grounded the SW1 pin current will drop to near 1.7µA.
However, if the VIN1 pin is grounded while channel 1 output
is held high, regardless of EN/UV1, parasitic body diodes
inside the LT8650S-1 can pull current from the output
through the SW1 pin and the VIN1 pin, damaging the IC.
VIN2 is not connected to the shared internal supply and
will not draw any current if left floating. If both VIN1 and
VIN2 are floating, regardless of EN/UV pins states, no load
will be present at the output of channel 2. However, if the
VIN2 pin is grounded while channel 2 output is held high,
parasitic body diodes inside the LT8650S-1 can pull current from the output through the SW2 pin and the VIN2
pin, damaging the IC.
Figure 8 shows a connection of the VIN and EN/UV pins
that will allow the LT8650S-1 to run only when the input
voltage is present and that protects against a shorted or
reversed input.
VIN1
VIN1
VIN2
VIN2
LT8650S-1
EN/UV1
EN/UV2
GND
8650s1 F08
Figure 8. Reverse VIN Protection for Two Independent Input Voltages
24
Rev 0
For more information www.analog.com
LT8650S-1
APPLICATIONS INFORMATION
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 9 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
currents flow in the LT8650S-1’s VIN pins, GND pins,
and the input capacitors. The loop formed by the input
capacitor should be as small as possible by placing the
capacitor adjacent to the VIN and GND pins. When using
a physically large input capacitor the resulting loop may
become too large in which case using a small case/value
capacitor placed close to the VIN and GND pins plus a larger
capacitor further away is preferred. These components,
along with the inductor and output capacitor, should be
placed on the same side of the circuit board, and their
connections should be made on that layer. Place a local,
unbroken ground plane under the application circuit on
the layer closest to the surface layer. The SW and BOOST
nodes should be as small as possible. Finally, keep the FB
and RT nodes small so that the ground traces will shield
them from the SW and BOOST nodes. The exposed pad
acts as a heat sink and is connected electrically to ground.
To keep thermal resistance low, extend the ground plane
as much as possible, and add thermal vias under and
near the LT8650S-1 to additional ground planes within
the circuit board and on the bottom side. See Figure 9 for
example PCB layout.
High Temperature Considerations
Care should be taken in the layout of the PCB to ensure
good heat sinking of the LT8650S-1. The exposed pad on
the bottom of the package must be soldered to a ground
plane. This ground should be tied to large copper layers
below with thermal vias; these layers will spread heat
dissipated by the LT8650S-1. Placing additional vias can
reduce thermal resistance further. The maximum load
current should be derated as the ambient temperature
approaches the maximum junction rating. Power dissipation within the LT8650S-1 can be estimated by calculating the total power loss from an efficiency measurement
and subtracting the inductor loss. The die temperature is
calculated by multiplying the LT8650S-1 power dissipation by the thermal resistance from junction to ambient.
The internal thermal shutdown protection of LT8650S-1
will stop switching and indicate a fault condition if junction temperature exceeds 165°C. The fault condition will
clear and switching resume when the temperature drops
back below 160°C.
Temperature rise of the LT8650S-1 is worst when operating at high load, high VIN, and high switching frequency.
If the case temperature is too high for a given application,
then either VIN, switching frequency, or load current can
be decreased to reduce the temperature to an acceptable
level. Figure 10 shows examples case temperature vs VIN,
switching frequency, and load.
The LT8650S-1’s internal power switches are capable of
safely delivering up to 6A of peak output current. However,
due to thermal limits, the package can only handle 6A loads
for short periods of time. Figure 11 shows an example of
how case temperature rise changes with the duty cycle
of a 1kHz pulsed 6A load.
Rev 0
For more information www.analog.com
25
LT8650S-1
APPLICATIONS INFORMATION
RC2
RC1
CC1
CC2
R4
R2
CFF2
CFF1
COUT1
CVCC
RT
R3
CIN1
L1
R1
CBST1
L2
CBST2
CIN2
COUT2
8650s1 F09
Figure 9. Recommended Layout
120
100
90
80
70
60
50
40
30
20
0
1
2
3
4
LOAD1 CURRENT (A)
5
70
60
50
40
30
20
0
6
8650s1 F10
Figure 10. Case Temperature Rise
0
0.2
0.4
0.6
0.8
DUTY CYCLE OF PULSED LOAD
1
8650s1 F11
CH1 = 0.5A STANDBY, 6A PULSED;
CH2 = 0A DC
CH1 = 0.5A STANDBY, 6A PULSED;
CH2 = 4A DC
CH1 = CH2 = 2A STANDBY, 6A PULSED
24VIN, LOAD2 = LOAD1
12VIN, LOAD2 = LOAD1
12VIN, LOAD2 = 4A
12VIN, LOAD2 = 0A
26
80
10
10
0
DC2407A DEMO BOARD
VIN1,2 = 12V, fSW = 2MHz
VOUT1 = 5V, VOUT2 = 3.3V
90
CASE TEMPERATURE RISE (°C)
CASE TEMPERATURE RISE (°C)
100
DC2407A DEMO BOARD
VOUT1 = 5V, VOUT2 = 3.3V, fSW = 2MHz
110
Figure 11. Case Temperature Rise vs 6A Pulsed Load
Rev 0
For more information www.analog.com
LT8650S-1
TYPICAL APPLICATIONS
5V, 3.3V, 2MHz Step-Down Converter with FCM and External Compensation
VIN1
6V TO 42V
VOUT1
5V
4A
VIN1
BST2
SW1
SW2
LT8650S-1
15k
191k
220pF
4.7µF
0.1µF 1µH
4.7pF
1M
EN/UV2
BST1
0.1µF
1µH
47µF
×2
1206
X5R
EN/UV1
4.7µF
VIN2
4.2V TO 42V
VIN2
4.7µF
FB1
FB2
VC1
VC2
SS1
SS2
15k
PG1
PG2
CLKOUT
BIAS
VOUT2
3.3V
4A
316k
10nF
10nF
100k
1M
47µF
×2
1206
X5R
220pF
100k
TEMP
RT
VCC
GND
SYNC
L: XFL5030
1µF
15k
fSW = 2MHz
8650s1 TA02
5V, 1.8V, 2MHz Step-Down Converter with Burst Mode and Internal Compensation
VIN1
5.4V TO 42V
VOUT1
5V
4A
VIN1
1µH
47µF
×2
1206
X5R
4.7pF
VIN2
EN/UV1
4.7µF
EN/UV2
BST1
BST2
SW1
SW2
0.1µF
LT8650S-1
FB1
VCC
VIN2
2.3V TO 42V
0.1µF 1µH
1M
191k
4.7µF
1M
FB2
VC1
VC2
SS1
SS2
VCC
4.7pF
47µF
×2
1206
X5R
VOUT2
1.8V
4A
806k
10nF
10nF
PG1
PG2
CLKOUT
BIAS
TEMP
RT
VCC
15k
fSW = 2MHz
GND
SYNC
1µF
L: XFL5030
8650s1 TA03
Rev 0
For more information www.analog.com
27
LT8650S-1
TYPICAL APPLICATIONS
Two Phase, 3.3V, 8A, 2MHz Step-Down Converter
BST1
VIN
4.2V TO 42V
VIN1
VIN2
EN/UV1
EN/UV2
4.7µF
×2
0.1µF
1µH
0.1µF
1µH
SW1
BST2
LT8650S-1
SW2
4.7pF
FB1
FB2
VC1
VC2
SS1
SS2
22nF
RT
15k
VCC
220pF
100k
GND SYNC
L: XFL5030
1µF
15k
VOUT
3.3V
8A
316k
PG1
PG2
BIAS
CLKOUT
TEMP
1M
47µF
×2
1206
X5R
fSW = 2MHz
8650s1 TA04
Two Phase, 6V, 8A,400kHz Step-Down Converter
BST1
VIN
7V TO 42V
0.1µF 5.6µH
VIN1
VIN2
EN/UV1
EN/UV2
10µF
×2
SW1
BST2
LT8650S-1
0.1µF 5.6µH
SW2
4.7pF
FB1
FB2
VC1
VC2
SS1
SS2
10nF
VCC
100k
fSW = 400kHz
28
154k
1nF
100k
PG1
PG2
BIAS
CLKOUT
TEMP
RT
5.11k
1M
VOUT
6V
100µF 8A
×2
1210
X5R
GND SYNC
L: XAL5030
1µF
8650s1 TA05
Rev 0
For more information www.analog.com
LT8650S-1
TYPICAL APPLICATIONS
Two Phase, 3.3V, 8A, 400kHz Step-Down Converter
BST1
VIN
4.2V TO 42V
0.1µF 3.3µH
VIN1
VIN2
EN/UV1
EN/UV2
10µF
×2
SW1
BST2
LT8650S-1
0.1µF 3.3µH
SW2
4.7pF
FB1
FB2
VC1
VC2
SS1
SS2
10nF
VCC
100k
fSW = 400kHz
316k
680pF
100k
PG1
PG2
BIAS
CLKOUT
TEMP
RT
11k
1M
VOUT
3.3V
100µF 8A
×2
1210
X5R
GND SYNC
L: XAL5030
1µF
8650s1 TA06
Rev 0
For more information www.analog.com
29
LT8650S-1
TYPICAL APPLICATIONS
Four Phase, 5V, 16A, 2MHz Step-Down Converter
BST1
VIN
6V TO 42V
VIN1
VIN2
EN/UV1
EN/UV2
4.7µF
×2
0.1µF
1µH
0.1µF
1µH
SW1
BST2
LT8650S-1
SW2
4.7pF
FB1
FB2
VC1
VC2
SS1
SS2
22nF
VCC
47µF
×2
1206
X5R
191k
220pF
100k
PG1
PG2
BIAS
CLKOUT
TEMP
RT
15k
1M
VOUT
5V
16A
GND SYNC
1µF
15k
fSW = 2MHz
BST1
VIN1
4.7µF
×2
VIN2
EN/UV1
EN/UV2
0.1µF
1µH
0.1µF
1µH
SW1
BST2
LT8650S-1
SS1
SW2
47µF
×2
1206
X5R
FB1
SS2
FB2
22nF
VC1
VC2
PG1
CLKOUT
PG2
TEMP
BIAS
VCC
RT
15k
GND SYNC
L: XFL5030
1µF
fSW = 2MHz
8650s1 TA07
30
Rev 0
For more information www.analog.com
0.25 ±0.05
PACKAGE
OUTLINE
0.70 ±0.05
6.50 ±0.05
aaa Z
2×
D
PACKAGE TOP VIEW
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license isFor
granted
implication orwww.analog.com
otherwise under any patent or patent rights of Analog Devices.
morebyinformation
4.50 ±0.05
0.20
1.10
0.20
1.33
1.2500
1.2500
SUGGESTED PCB LAYOUT
TOP VIEW
0.7500
5
0.2500
0.0000
0.2500
0.375
X
aaa Z
2.2500
1.7500
1.2500
0.7500
0.2500
0.0000
0.2500
0.7500
1.2500
1.7500
2.2500
0.375
Y
E
2×
// bbb Z
SYMBOL
A
A1
L
b
D
E
D1
E1
e
H1
H2
aaa
bbb
ccc
ddd
eee
fff
28b
eee M Z X Y
fff M Z
H1
L
NOM
0.94
0.02
0.40
0.25
4.00
6.00
2.40
4.40
0.50
0.24
0.70
DIMENSIONS
e/2
e
DETAIL C
SUBSTRATE
DETAIL A
MIN
0.85
0.01
0.30
0.22
DETAIL B
H2
MOLD
CAP
DETAIL C
A1
28×
0.10
0.10
0.10
0.10
0.15
0.08
MAX
1.03
0.03
0.50
0.28
DETAIL B
A
NOTES
(Reference LTC DWG # 05-08-1665 Rev C)
ddd Z
Z
Z
PAD “A1”
CORNER
0.7500
17
e
20
22
b
26
16
27
0.20
D1
e
0.40
0.20
PACKAGE BOTTOM VIEW
b
6
1.10
1.33
11
32
DETAIL A
PIN 1 NOTCH
0.25 × 45°
10
8
4
7 SEE NOTES
5
4
2
1
7
SEE NOTES
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
PACKAGE IN TRAY LOADING ORIENTATION
LTXXXXXX
LQFN 32(28) 0118 REV C
THE EXPOSED HEAT FEATURE IS SEGMENTED AND ARRANGED
IN A MATRIX FORMAT. IT MAY HAVE OPTIONAL CORNER RADII
ON EACH SEGMENT
6
CORNER SUPPORT PAD CHAMFER IS OPTIONAL
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE
LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER
MAY BE EITHER A MOLD OR MARKED FEATURE
5
7
METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN
SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES
4
3. PRIMARY DATUM -Z- IS SEATING PLANE
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
0.375
E1
ccc M Z X Y
ccc M Z X Y
LQFN Package
32(28)-Lead (6mm × 4mm × 0.94mm)
LT8650S-1
PACKAGE DESCRIPTION
Rev 0
31
LT8650S-1
TYPICAL APPLICATION
5V, 1.2V, 2MHz Two Stage Step-Down Converter with Output Sequencing
VIN
5.4V TO 42V
VIN1
4.7µF
CLKOUT
EN/UV1
TEMP
BST1
BST2
VIN2
VOUT1
5V
3A
47µF
×2
1206
X5R
0.1µF
0.1µF
4.7µF
L1
1µH
L2
0.33µH
LT8650S-1
SW1
4.7pF
SW2
499k
1M
191k
VCC
FB1
FB2
VC1
VC2
SS1
SS2
VCC
47µF
×3
1206
X5R
1M
10nF
10nF
BIAS
100k
4.7pF
VOUT2
1.2V
4A
PG1
100k
PG2
EN/UV2
RT
VCC
15k
GND
L1: XFL5030
L2: XEL4020
SYNC
1µF
8650s1 TA06
fSW = 2MHz
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT8650S
42V, Dual 4A, 94% Efficiency, 3MHz Synchronous Silent Switcher 2
DC/DC Converter with IQ = 6.2µA
VIN = 3V to 42V, VOUT(MIN) = 0.8V, IQ = 6.2µA, 4x6 QFN-32
Package
LT8640S
42V, 5A, 95% Efficiency, 2.2MHz Synchronous Silent Switcher 2
Step-Down DC/DC Converter with IQ = 2.5µA
VIN = 3.4V to 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA, ISD
工商网监
湘ICP备2023018690号
