LTC6226IDC#TRPBF

LTC6226/LTC6227 1nV/√Hz 420MHz GBW, 180V/µs, Low Distortion Rail-to-Rail Output Op Amps FEATURES DESCRIPTION Ultra Low Voltage Noise: 1nV/√Hz n Low Distortion: HD2/HD37V) 70 AV = –1 1 RL = 1k, 3rd 1M FREQUENCY (Hz) 0.1% Settling Time vs Output Step SETTLING TIME (ns) –50 Maxium Undistorted Output Signal vs Frequency OUTPUT VOLTAGE SWING (VP–P) –40 Distortion vs Frequency, AV = 2, 3V Supply VS = ±5V TA = 25°C AV = 1 0V 1.5V/DIV SHDN 2.25V 1V/DIV 2µs/DIV 62267 G43 Small Signal Response Output Overdriven Recovery VS = ±5V RL = 1k AV = 1 TA = 25°C INPUT 50mV/DIV 62267 G44 100ns/DIV INPUT OUTPUT VS = ±5V AV=2 RL=1kΩ TA=25°C OUTPUT 2V/DIV INPUT 1V/DIV OUTPUT 50mV/DIV 5ns/DIV 62267 G45 100ns/DIV 62267 G46 Rev 0 14 For more information www.analog.com LTC6226/LTC6227 PIN FUNCTIONS SHDN: Shutdown Pin (Active Low). Referenced to V+. When taken 2.75V below V+, the amplifier shuts down and enters low power mode, with the outputs in a high impedance state. When left floating, the amplifier is on. FB (SOIC-8 Only): Feedback Pin. Internally connected to OUT. +IN: Non-Inverting Input of Amplifier. Valid input range is from V– to V+ – 1.2V V+: Positive Supply to Amplifier. Valid range is from 2.8V to 11.75V when V– is 0V. –IN: Inverting Input of Amplifier. Valid input range is from V– to V+ – 1.2V V–: Negative Supply to Amplifier. Typically 0V. This can be made a negative voltage as long as 2.8V ≤ (V+ – V–) ≤ 11.75V OUT: Output of the Amplifier. Swings rail to rail and can typically source/sink 60mA of current. APPLICATIONS INFORMATION Circuit Description independent of transistor β. The bootstrap arrangement also enhances gain by improving output impedance. A pair of complementary common emitter stages, Q15 and Q14, enables the output to swing to either rail. The SHDN Interface block translates the SHDN signal into pwr_dn for powering down the device (by deactivating current sources I1 - I4) and putting the output in a high impedance state (by shorting the bases of Q15/Q14 to the supplies via M2 and M1). The LTC6226/LTC6227 have an input signal range that extends from the negative power supply to 1.2V below the positive power supply. Figure 1 depicts a simplified schematic of the amplifier. The input stage consists of PNP transistors Q1 and Q2. Bootstrap transistor Q13 improves DC accuracy by reducing the offset contribution of the base currents of Q11 and Q12 since it has twice their collector current thus Q11/Q12 current matching becomes V+ pwr_dn V+ V– ESDD1 pwr_dn pwr_dn M2 Q15 + R3 I1 ESDD2 I3 R4 R5 ESDD5 C2 Q12 Q11 Q13 +IN V– pwr_dn SHDN SHDN INTERFACE BLOCK D5 D7 Q1 CC OUT Q2 V+ +IN ESDD4 V– pwr_dn ESDD3 V+ Q9 Q8 I4 ESDD6 Q10 pwr_dn R1 BUFFER AND OUTPUT BIAS R2 V– M1 C1 Q14 R3 62267 F01 Figure 1. LTC6226/LTC6227 Simplified Schematic Diagram Rev 0 For more information www.analog.com 15 LTC6226/LTC6227 APPLICATIONS INFORMATION Output ESD The LTC6226 family has excellent output drive capability. The amplifiers can typically deliver more than 50mA of output drive current at a total supply of 10V, and can typically swing to within 600mV of the rail for load currents as high as 25mA. As the supply voltage to the amplifier decreases, the output current capability also decreases. Attention must be paid to keep the junction temperature of the IC below 150°C (refer to power dissipation section) when the output is in continuous short-circuit. The output of the amplifier has reverse-biased diodes connected to each supply. If the output is forced beyond either supply, extremely high currents will flow through those diodes which can result in damage to the device. Forcing the output to even 1V beyond either supply could result in several hundred milliamps of current through either diode. Thus forcing the output beyond the supplies should be avoided. The LTC6226 family has reverse biased ESD protection diodes on all inputs as shown in Figure 1. There is an additional clamp between the positive and negative supplies that further protects the device during ESD strikes. Input Protection The LTC6226/LTC6227 has a pair of back to back diodes (D5 and D7) to prevent the emitter base breakdown of the input transistors and limit the differential input to ±700mV. Unlike many other high performance amplifiers, the bases of the input pair transistors Q1 and Q2 are not connected to the pins using internal resistors to limit input current, since that would cause the noise to increase. For instance, a 100Ω resistor in series with each input would generate 1.8nV/√Hz of noise, and the total amplifier noise voltage would rise from 1nV/√Hz to 2.06nV/√Hz. Once the input differential voltage exceeds ±0.7V, current conducted though the protection diodes should be limited to ±10mA. This implies 25Ω of protection resistance per quarter volt (250mV) of overdrive beyond ±0.7V. In addition, the input and shutdown pins have reverse biased diodes connected to the supplies. The current in these diodes must be limited to less than 10mA. The amplifiers should not be used as comparators or in other open loop applications. Hot plugging of the device into a powered socket must be avoided since this can trigger the clamp resulting in larger currents flowing between the supply pins. Capacitive Loads The LTC6226/LTC6227 are optimized for high bandwidth applications, and have not been designed to directly drive capacitive loads. Hence any trace capacitance at the output should be made as small as possible. Increased capacitance at the output creates an additional pole in the open loop frequency response, worsening the phase margin. When driving capacitive loads, a resistor of 10Ω to 100Ω should be connected between the amplifier output and the capacitive load to avoid ringing or oscillation. The feedback should be taken directly from the amplifier output. Higher voltage gain configurations tend to have better capacitive drive capability than lower gain configurations due to lower closed loop bandwidth and hence higher phase margin. The graphs titled Overshoot vs Capacitive Load demonstrate the transient response of the amplifier when driving capacitive loads with various series resistors. Rev 0 16 For more information www.analog.com LTC6226/LTC6227 APPLICATIONS INFORMATION Feedback Components Power Dissipation When feedback resistors are used to set up gain, care must be taken to ensure that the pole formed by the feedback resistors and the parasitic capacitance at the inverting input does not degrade stability. For example if the amplifier is set up in a gain of +2 configuration with gain and feedback resistors of 1k, a parasitic capacitance of 7pF (device + PC board) at the amplifier’s inverting input will cause the part to oscillate, due to a pole formed at 45MHz. An additional capacitor of 7pF across the feedback resistor as shown in Figure 2 will eliminate any ringing or oscillation. In general, if the resistive feedback network results in a pole whose frequency lies within the closed loop bandwidth of the amplifier, a capacitor can be added in parallel with the feedback resistor to introduce a zero whose frequency is close to the frequency of the pole, improving stability. For high speed designs, minimizing parasitic inductance is important. The use of capacitors where the electrodes are terminated on the long side instead of the short side (for example the use of 0306 instead of 0603 components) can help in this regard. Care must be taken to ensure that the junction temperature of the die does not exceed 150°C. 7pF 1k CPAR VIN VOUT + TJ = TA + (PD • θJA). The power dissipation in the IC is a function of the supply voltage, output voltage and load resistance. For symmetric supply voltages with output load connected to ground, the worst-case power dissipation PD(MAX) occurs when the supply current is maximum and the output voltage at half of either supply voltage for a given load resistance. PD(MAX) is approximately (since IS actually changes with output load current) given by: PD(MAX) = (2 • VS • IS(MAX)) + (VS/2)2/RL Example: For an LTC6227 in a 8-lead MS package operating on ±5V supplies and driving a 250Ω load to ground, the worst-case power dissipation is approximately given by PD(MAX)/Amp = (10 • 7.4mA) + (5/2)2/250 = 99mW. If both channels are loaded identically, the total power dissipation is 198mW. At the Absolute Maximum ambient operating temperature, the junction temperature under these conditions will be: – 1k The junction temperature, TJ, is calculated from the ambient temperature, TA, power dissipation, PD, and thermal resistance, θJA: TJ = TA + (PD • θJA) = 125 + 0.198 • 35 = 132°C 62267 F02 Figure 2. 7pF Feedback Cancels Parasitic Pole Shutdown The LTC6226 and LTC6227DD have SHDN pins that can shut down the amplifier to 350µA typical supply current. The SHDN pin needs to be taken 2.75V below the positive supply to shut down. When left floating, the SHDN pin is internally pulled up to 1.2V below the positive supply and the amplifier remains on. During shutdown, the output transistors Q15 and Q14 in Figure 1 are in a high impedance state. which is less than the absolute maximum junction temperature for the LTC6227. Refer to the Pin Configuration section for thermal resistances of various packages Board Layout and Bypass Capacitors High speed and RF board layout techniques should be applied due to the very high speeds of the signals involved. For the LTC6226 SOIC-8 package option, the feedback should be taken from the FB pin rather than from the output pin, to reduce signal trace length. Stray capacitances at the –IN and +IN pins should be made as low as possible to reduce stability degradation. Rev 0 For more information www.analog.com 17 LTC6226/LTC6227 APPLICATIONS INFORMATION For single supply applications, it is recommended that high quality 0.1µF||1000pF ceramic bypass capacitors be placed directly between each V+ pin and its closest V– pin with short connections. The V– pins (including the Exposed Pad) should be tied directly to a low impedance ground plane with minimal routing. For dual (split) power supplies, it is recommended that additional high quality 0.1µF||1000pF ceramic capacitors be used to bypass V+ pins to ground and V– pins to ground, again with minimal routing. Noise Considerations The ultralow input referred voltage noise of of 1nV/√Hz is equivalent to that of an 60Ω resistor. As with all BJT input amplifiers, lowering input referred noise is achieved by increasing the collector current of the input differential pair, which increases the input referred current noise. Figure 3 shows the LTC6226 in a typical gain configuration. RS1 RF – in RS2 LTC6226 en + in 62267 F03 Figure 3. As can be seen, the input referred noise spectral density of the gain stage (eT) can be calculated by the following equations: eT2 = en2 + in2REQ2 + 4kTREQ Where REQ = RS2 + RS1||RF, k is the Boltzmann constant and T is the temperature (in Kelvin). Resistor noise dominated the input referred noise of the gain stage when REQ >> en2/4kT and REQ > 4kT/in2 With an input referred voltage noise spectral density of 1nV/Hz and an input referred current noise of 2.4pA/Hz, it is easy to see that the gain stage’s input referred noise is dominated by op amp voltage noise when REQ