OP282GS

a FEATURES High Slew Rate: 9 V/ s Wide Bandwidth: 4 MHz Low Supply Current: 250 A/Amplifier Low Offset Voltage: 3 mV Low Bias Current: 100 pA Fast Settling Time Common-Mode Range Includes V+ Unity Gain Stable APPLICATIONS Active Filters Fast Amplifiers Integrators Supply Current Monitoring Dual/Quad Low Power, High Speed JFET Operational Amplifiers OP282/OP482 PIN CONNECTIONS 8-Lead Narrow-Body SOIC 8-Lead Epoxy DIP (S Suffix) (P Suffix) OUT A 1 –IN A +IN A V– 2 3 4 8 V+ 7 OUT B OUT A 1 –IN A +IN A V– 2 3 4 OP-482 8 V+ 7 OUT B OP282 OP282 6 –IN B 5 +IN B 6 –IN B 5 +IN B 14-Lead Epoxy DIP (P Suffix) OUT A –IN A 1 2 3 4 5 6 7 14 OUT D 13 –IN D 12 +IN D 14-Lead Narrow-Body SOIC (S Suffix) OUT A –IN A +IN A V+ +IN B –IN B OUT B 1 2 3 4 5 6 7 14 OUT B 13 12 –IN D +IN D V– GENERAL DESCRIPTION +IN A V+ +IN B –IN B OUT B The OP282/OP482 dual and quad operational amplifiers feature excellent speed at exceptionally low supply currents. Slew rate exceeds 7 V/µs with supply current under 250 µA per amplifier. These unity gain stable amplifiers have a typical gain bandwidth of 4 MHz. The JFET input stage of the OP282/OP482 insures bias current is typically a few picoamps and below 500 pA over the full temperature range. Offset voltage is under 3 mV for the dual and under 4 mV for the quad. With a wide output swing, within 1.5 volts of each supply, low power consumption and high slew rate, the OP282/OP482 are ideal for battery-powered systems or power restricted applications. An input common-mode range that includes the positive supply makes the OP282/OP482 an excellent choice for highside signal conditioning. The OP282/OP482 are specified over the extended industrial temperature range. Both dual and quad amplifiers are available in plastic and ceramic DIP plus SOIC surface mount packages. OP482 11 V– 10 +IN C 9 8 –IN C OUT C OP482 11 10 +IN C 9 8 –IN C OUT C R EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 OP282/OP482–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V = S 15.0 V, TA = +25 C unless otherwise noted) Min Typ 0.2 0.2 3 1 –11 70 20 15 Max 3 4.5 4 6 100 500 50 250 +15 Units mV mV mV mV pA pA pA pA V dB V/mV V/mV µV/°C pA/°C V mA mA Ω Parameter INPUT CHARACTERISTICS Offset Voltage Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift OUTPUT CHARACTERISTICS Output Voltage Swing Short Circuit Limit Open-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier Supply Voltage Range DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Symbol VOS VOS IB IOS Conditions OP282 OP282, –40 ≤ TA ≤ +85°C OP482 OP482, –40 ≤ TA ≤ +85°C VCM = 0 V VCM = 0 V, Note 1 VCM = 0 V VCM = 0 V, Note 1 –11 V ≤ VCM ≤ +15 V, –40 ≤ TA ≤ +85°C R L = 10 kΩ RL = 10 kΩ, –40 ≤ TA ≤ +85°C CMR AVO ∆VOS/∆T ∆IB/∆T VO ISC ZOUT PSRR ISY VS SR BWP tS GBP ØO en p-p en in 90 10 8 R L = 10 kΩ Source Sink f = 1 MHz VS = ± 4.5 V to ± 18 V, –40 ≤ TA ≤ +85°C VO = 0 V, 40 ≤ TA ≤ +85°C –13.5 3 –8 ± 13.9 13.5 10 –12 200 ± 4.5 7 25 210 316 250 ± 18 µV/V µA V V/µs kHz µs MHz Degrees µV p-p nV/√Hz pA/√Hz R L = 10 kΩ 1% Distortion To 0.01% 9 125 1.6 4 55 1.3 36 0.01 0.1 Hz to 10 Hz f = 1 kHz NOTE 1 The input bias and offset currents are tested at TA = TJ = +85 °C. Bias and offset currents are guaranteed but not tested at –40 °C. Specifications subject to change without notice. WAFER TEST LIMITS (@ V = S 15.0 V, TA = +25 C unless otherwise noted) Symbol VOS VOS IB IOS CMRR PSRR AVO VO ISY Conditions OP282 OP482 VCM = 0 V VCM = 0 V –11 V ≤ VCM ≤ +15 V V = ± 4.5 V to ± 18 V R L = 10 kΩ R L = 10 kΩ V O = 0 V, R L = ∞ Limit 3 4 100 50 –11, +15 70 316 20 ± 13.5 250 Units mV max mV max pA max pA max V min/max dB min µV/V V/mV min V min µA max Parameter Offset Voltage Offset Voltage Input Bias Current Input Offset Current Input Voltage Range 1 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Range Supply Current/Amplifier NOTES Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 1 Guaranteed by CMR test. Specifications subject to change without notice. – 2– REV. B OP282/OP482 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Differential Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . 36 V Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range OP282A, OP482A . . . . . . . . . . . . . . . . . . –55°C to +125°C OP282G, OP482G . . . . . . . . . . . . . . . . . . . –40°C to +85°C Junction Temperature Range P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C Lead Temperature Range (Soldering, 60 sec) . . . . . . +300°C Package Type 8-Pin Plastic DIP (P) 8-Pin SOIC (S) 14-Pin Plastic DIP (P) 14-Pin SOIC (S) 2 JA JC ABSOLUTE MAXIMUM RATINGS DICE CHARACTERISTICS Units °C/W °C/W °C/W °C/W OP282 Die Size 0.063 0.060 Inch, 3,780 Sq. Mils 103 158 83 120 43 43 39 36 NOTES 1 For supply voltages less than ± 18 V, the absolute maximum input voltage is equal to the supply voltage. 2 θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket for cerdip, P-DIP; θJA is specified for device soldered in circuit board for SOIC package. ORDERING GUIDE Model OP282GP OP282GS OP482GP OP482GS Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 8-Pin Plastic DIP 8-Pin SOIC 14-Pin Plastic DIP 14-Pin SOIC Package Option N-8 SO-8 N-14 SO-14 OP482 Die Size 0.070 0.098 Inch, 6,860 Sq. Mils REV. B –3– OP282/OP482 APPLICATIONS INFORMATION PHASE INVERSION The OP282 and OP482 are single and dual JFET op amps that have been optimized for high speed at low power. This combination makes these amplifiers excellent choices for battery powered or low power applications requiring above average performance. Applications benefiting from this performance combination include telecom, geophysical exploration, portable medical equipment and navigational instrumentation. HIGH SIDE SIGNAL CONDITIONING There are many applications that require the sensing of signals near the positive rail. OP282s and OP482s have been tested and guaranteed over a common-mode range (–11 V ≤ VCM ≤ +15 V) that includes the positive supply. One application where this is commonly used is in the sensing of power supply currents. This enables it to be used in current sensing applications such as the partial circuit shown in Figure 1. In this circuit, the voltage drop across a low value resistor, such as the 0.1 Ω shown here, is amplified and compared to 7.5 volts. The output can then be used for current limiting. +15V 0.1 Ω 500k 100k 100k Most JFET-input amplifiers will invert the phase of the input signal if either input exceeds the input common-mode range. For the OP282 and OP482 negative signals in excess of approximately 14 volts will cause phase inversion. The cause of this effect is saturation of the input stage leading to the forwardbiasing of a drain-gate diode. A simple fix for this in noninverting applications is to place a resistor in series with the noninverting input. This limits the amount of current through the forwardbiased diode and prevents the shutting down of the output stage. For the OP282/OP482, a value of 200 kΩ has been found to work. However, this adds a significant amount of noise. 15 10 5 V IN 0 -5 -10 RL -15 -15 -10 -5 0 V OUT 5 10 15 + 100k 1/2 OP282 Figure 2. OP282 Phase Reversal ACTIVE FILTERS The OP282 and OP482’s wide bandwidth and high slew rates make either an excellent choice for many filter applications. Figure 1. Phase Inversion There are many types of active filter configurations, but the four most popular configurations are Butterworth, elliptical, Bessel, and Chebyshev. Each type has a response that is optimized for a given characteristic as shown in Table I. PROGRAMMABLE STATE-VARIABLE FILTER Table I. Type Butterworth Chebyshev Elliptical Bessel (Thompson) Selectivity Moderate Good Best Poor Overshoot Good Moderate Poor Best Phase Nonlinear Linear Amplitude (Pass Band) Max Flat Equal Ripple Equal Ripple Amplitude (Stop Band) Equal Ripple –4– REV. B OP282/OP482 The circuit shown in Figure 3 can be used to accurately program the “Q,” the cutoff frequency fC, and the gain of a two pole state-variable filter. OP482s have been used in this design because of their high bandwidths, low power and low noise. This circuit takes only three packages to build because of the quad configuration of the op amps and DACs. The DACs shown are all used in the voltage mode so all values are dependent only on the accuracy of the DAC and not on the absolute values of the DAC’s resistive ladders. This make this circuit unusually accurate for a programmable filter. Adjusting DAC 1 changes the signal amplitude across R1; therefore, the DAC attenuation times R1 determines the amount of signal current that charges the integrating capacitor, C1. This cutoff frequency can now be expressed as: fc =  D1  1   2πR1C1  256  where D1 is the digital code for the DAC. Gain of this circuit is set by adjusting D3. The gain equation is: Gain = R4  D 3    R5  256  DAC 2 is used to set the “Q” of the circuit. Adjusting this DAC controls the amount of feedback from the bandpass node to the input summing node. Note that the digital value of the DAC is in the numerator, therefore zero code is not a valid operating point. Q= R2  256    R3  D2  R7 2k 1/4 DAC8408 VIN R5 2k R4 2k 1/4 DAC8408 R1 2k C1 1000pF + 1/4 DAC8408 R1 2k C1 1000pF 1/4 OP482 + 1/4 OP482 + 1/4 OP482 + 1/4 OP482 + 1/4 OP482 + LOW HIGH PASS 1/4 PASS OP482 R6 2k R3 2k R2 1k 1/4 DAC8408 BANDPASS 1/4 OP482 + 1/4 OP482 + Figure 3. REV. B –5– OP282/OP482 OP282/OP482 SPICE MACRO MODEL Figure 4 shows the OP282 SPICE macro model. The model for the OP482 is similar to that of the OP282, but there are some 99 I1 minor changes in the circuit values. Contact ADI for a copy of the latest SPICE model diskette for both listings. V2 8 4 9 D1 INJ1 2 R2 IOS 1 IN+ CIN 3 EOS R1 5 C2 R3 R4 V3 50 C4 13 11 R6 E2 R7 R8 12 G2 C5 R9 G3 C6 R19 G11 C13 R22 14 19 20 E13 R21 21 C14 6 EREF D2 10 98 J2 G1 7 R5 C3 98 99 D5 ISY G19 R25 23 R23 G15 C15 98 D4 26 27 R26 G17 D7 G18 D8 28 G20 R28 24 V5 VOUT D3 25 V4 D6 R27 29 L5 30 50 Figure 4. –6– REV. B OP282/OP482 OP282 SPICE MACRO MODEL * Node assignments * noninverting input * inverting input * positive supply * negative supply * output * .SUBCKT OP282 1 2 99 50 30 * * INPUT STAGE & POLE AT 15 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 3871.3 R4 6 50 3871.3 CIN 1 2 5E-12 C2 5 6 1.37E-12 I1 99 4 0.1E-3 IOS 1 2 5E-13 EOS 7 1 POLY(1) 21 24 200E-6 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 24 01 * * GAIN STAGE & POLE AT 124 HZ * R5 9 98 1.16E8 C3 9 98 1.11E-11 G1 98 9 56 2.58E-4 V2 99 8 1.2 V3 10 50 1.2 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 4 MHZ * R6 11 12 1E6 R7 12 98 1 C4 11 12 39.8E-15 E2 11 98 9 24 1E6 * * POLE AT 15 MHZ * R8 13 98 1E6 C5 13 98 10.6E-15 G2 98 13 12 24 1E-6 * * POLE AT 15 MHZ * R9 14 98 1E6 C6 14 98 10.6E-15 G3 98 14 13 24 1E-6 * * POLE AT 15 MHZ * R19 19 98 1E6 C13 19 98 10.6E-15 G11 98 19 14 24 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 11 KHZ * R21 20 21 1E6 R22 21 98 1 C14 20 21 14.38E-12 E13 98 20 3 24 31.62 * * POLE AT 15 MHZ * R23 23 98 1E6 C15 23 98 10.6E-15 G15 98 23 19 24 1E-6 * * OUTPUT STAGE * R25 24 99 5E6 R26 24 50 5E6 ISY 99 50 107E-6 R27 29 99 700 R28 29 50 700 L5 29 30 1E-8 G17 27 50 23 29 1.43E-3 G18 28 50 29 23 1.43E-3 G19 29 99 99 23 1.43E-3 G20 50 29 23 50 1.43E-3 V4 25 29 2.8 V5 29 26 3.5 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA = 3.34E-4 VTO = –2.000 IS = 3E-12) .MODEL DX D(IS = 1E-15) .MODEL DY D(IS = 1E-15 BV = 50) .ENDS OP282 REV. B –7– OP282/OP482 80 TA = +25°C VS = ±15V 0 35 30 OPEN-LOOP GAIN – V/MV 70 60 45 VS = ±15V RL= 10k OVERSHOOT – % VS = ±15V 60 50 40 30 20 10 0 RL = 2kΩ L VIN = 100mV p-p AVCL = +1 NEGATIVE EDGE OPEN-LOOP GAIN – dB 40 90 PHASE – Degrees 25 20 15 10 5 AVCL = +1 POSITIVE EDGE 20 135 0 180 1k 10k 100k 1M 10M 100M FREQUENCY – Hz 0 25 50 75 –75 –50 –25 TEMPERATURE – °C 100 125 0 100 200 300 400 LOAD CAPACITANCE – pF 500 Figure 5. Open-Loop Gain, Phase vs. Frequency 60 50 CLOSED-LOOP GAIN – dB Figure 8. Open-Loop Gain (V/mV) Figure 11. Small Signal Overshoot vs. Load Capacitance 1000 25 TA = +25°C VS = ±15V – SR 20 SLEW RATE – V/µs INPUT BIAS CURRENT – pA VS = ±15V VCM = 0 100 AVCL= +100 40 30 AVCL = +10 20 10 AVCL = +1 0 15 VS= ±15V RL= 10k L CL= 50pF 10 10 + SR 5 1.0 –10 –20 1k 0.1 10k 100k 1M 10M 100M –75 FREQUENCY – Hz –50 –25 0 25 50 75 TEMPERATURE –°C 100 125 25 50 75 –50 –25 0 TEMPERATURE – °C 100 125 Figure 6. Closed-Loop Gain vs. Frequency 60 VS = ±15V RL = 10k 55 4.5 50 Figure 9. OP282/OP482 Slew Rate vs. Temperature 80 GAIN BANDWIDTH PRODUCT – MH Z Figure 12. OP282 Input Bias Current vs. Temperature 1000 70 60 50 40 30 20 10 0 10 100 1k FREQUENCY – Hz VOLTAGE NOISE DENSITY – nV/ INPUT BIAS CURRENT – pA PHASE MARGIN – Degrees VS = ±15V T = +25°C A VS = ±15V TA = +25°C 100 ØM 50 GBW 4.0 Hz 10 45 3.5 1 40 0 –75 –50 –25 25 50 75 TEMPERATURE – °C 3.0 100 125 10k 0.1 –15 –10 –5 5 10 0 COMMON - MODE VOLTAGE – V 15 Figure 7. OP482 Phase Margin and Gain Bandwidth Product vs. Temperature Figure 10. Voltage Noise Density vs. Frequency Figure 13. OP282 Input Bias Current vs. Common-Mode Voltage –8– REV. B OP282/OP482 1.15 RELATIVE SUPPLY CURRENT – ISY 20 OUTPUT VOLTAGE SWING – Volts 600 TA = +25°C RL = 10k Ω 1.10 TA = +25°C 1.05 15 10 500 TA = +25°C VS = ±15V AVCL = 1000 IMPEDANCE – Ω 5 0 –5 –10 –15 –20 400 1.00 300 0.95 200 AVCL = 100 AVCL= +10 AVCL= 1 0.90 100 0.85 0 ±10 ±5 ±15 SUPPLY VOLTAGE – Volts ±20 0 ±5 ±10 ±15 ±20 0 100 1k 10k 100k 1M SUPPLY VOLTAGE – Volts FREQUENCY – Hz Figure 14. Relative Supply Current vs. Supply Voltage 1.20 Figure 17. Output Voltage Swing vs. Supply Voltage 16 Figure 20. OP482 Closed-Loop Output Impedance vs. Frequency 100 VS = ±15V ∆V = 100mV TA = +25°C ABSOLUTE OUTPUT VOLTAGE – Volts RELATIVE SUPPLY CURRENT – ISY 1.15 1.10 1.05 1.00 0.95 0.90 0.85 VSUP = ±15 14 12 10 8 6 4 TA = +25°C VS = ±15V 80 + PSRR PSRR – dB POSITIVE SWING 60 – PSRR 40 NEGATIVE SWING 20 0 2 0 0.80 0 –75 –50 –25 25 50 75 TEMPERATURE – °C 100 125 100 1k LOAD RESISTANCE – Ω 10k –20 100 1k 10k 100k 1M FREQUENCY – Hz Figure 15. Relative Supply Current vs. Temperature 20 Figure 18. Maximum Output Voltage vs. Load Resistance 30 Figure 21. OP282 Power Supply Rejection Ratio (PSRR) vs. Frequency 100 MAXIMUM OUTPUT SWING – Volts SHORT CIRCUIT CURRENT – mA VS = ±15V SINK 15 25 TA = +25°C VS = ±15V AVCL = +1 RL = 10k Ω 80 20 60 VS = ±15V VCM = 100mV TA = +25°C 10 15 CMRR – dB 10k 100k 1M 40 SOURCE 5 10 20 5 0 0 0 –75 –50 –25 25 50 75 TEMPERATURE – °C 100 125 1k –20 100 1k 10k 100k 1M FREQUENCY – Hz FREQUENCY – Hz Figure 16. OP282/OP482 Short Circuit Current vs. Temperature Figure 19. Maximum Output Swing vs. Frequency Figure 22. OP282 Common-Mode Rejection Ratio (CMRR) vs. Frequency REV. B –9– OP282/OP482 280 320 700 600 500 VS = ±15V -40°C ≤ TA ≤ +125°C 300 × OP482 1200 OP AMPS 240 200 VS = ±15V TA= +25°C 315 × OP282 (630 OP AMPS ) 280 240 200 UNITS UNITS 160 120 160 120 UNITS 0 4 8 12 16 20 TCVOS – µV/°C 24 28 32 400 300 200 100 0 0 4 8 12 16 20 24 28 32 TCVOS – µV/°C 80 80 40 0 0 400 800 1200 1600 2000 40 0 -2000 -1600 -1200 -800 -400 VOS – µV Figure 23. VOS Distribution "P" Package 280 Figure 25. OP282 TCVOS (µ V/°C) Distribution "P" Package 320 Figure 27. OP482 TCVOS Distribution "Z" Package 700 600 500 VS = ±15V 240 200 VS = ±15V TA = +25°C 320 × OP282 (640 OP AMPS) 280 240 200 -40°C ≤ TA ≤ +85°C 300 × OP482 1200 OP AMPS UNITS UNITS 160 120 120 UNITS 160 400 300 200 100 0 80 80 40 40 0 0 400 800 1200 1600 2000 0 –2000 –1600 –1200 –800 –400 0 4 8 VOS – µV 12 16 20 TCVOS – µV/°C 24 28 32 0 4 8 12 16 20 24 28 32 TCVOS – µV/°C Figure 24. VOS Distribution "Z" Package 700 600 500 Figure 26. OP282 TCVOS (µ V/°C) Distribution "Z" Package 700 TA = +25°C VS = ±15V 300 OP482 1200 OP AMPS Figure 28. TCVOS Distribution "P" Package 600 500 400 300 200 100 0 TA = +25°C VS = ±15V 300 OP482 1200 OP AMPS UNITS 300 200 100 0 –2000 –1600 –1200 –800 –400 0 400 800 1200 1600 2000 UNITS 400 –2000 –1600 –1200 –800 –400 0 400 800 1200 1600 2000 V OS – µV VOS – µV Figure 29. OP482 VOS Distribution “Z” Package Figure 30. OP482 VOS Distribution “P” Package –10– REV. B OP282/OP482 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Narrow-Body SOIC (S Suffix) 8-Lead Epoxy DIP (P Suffix) 14-Lead Narrow-Body SOIC (S Suffix) 14-Lead Epoxy DIP (P Suffix) 20-Position Chip Carrier (RC Suffix) REV. B –11– –12– C1597–24–11/91 REV. B PRINTED IN U.S.A.