AT91SAM7L64

Features • Incorporates the ARM7TDMI® ARM® Thumb® Processor – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash – 128 Kbytes (AT91SAM7L128), Organized in 512 Pages of 256 Bytes Single Plane – 64 Kbytes (AT91SAM7L64), Organized In 256 Pages of 256 Bytes Single Plane – Single Cycle Access at Up to 15 MHz in Worst Case Conditions – 128-bit Read Access – Page Programming Time: 4.6 ms, Including Page Auto Erase, Full Erase Time: 10 ms – 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit – Fast Flash Programming Interface for High Volume Production Internal High-speed SRAM, Single-cycle Access at Maximum Speed – 6 Kbytes • 2 Kbytes Directly on Main Supply That Can Be Used as Backup SRAM • 4 Kbytes in the Core Memory Controller (MC) – Enhanced Embedded Flash Controller, Abort Status and Misalignment Detection Enhanced Embedded Flash Controller (EEFC) – Interface of the Flash Block with the 32-bit Internal Bus – Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory Interface Reset Controller (RSTC) – Based on Zero-power Power-on Reset and Fully Programmble Brownout Detector – Provides External Reset Signal Shaping and Reset Source Status Clock Generator (CKGR) – Low-power 32 kHz RC Oscillator, 32 kHz On-chip Oscillator, 2 MHz Fast RC Oscillator and one PLL Supply Controller (SUPC) – Minimizes Device Power Consumption – Manages the Different Supplies On Chip – Supports Multiple Wake-up Sources Power Management Controller (PMC) – Software Power Optimization Capabilities, Including Active and Four Low Power Modes: • Idle Mode: No Processor Clock • Wait Mode: No Processor Clock, Voltage Regulator Output at Minimum • Backup Mode: Voltage Regulator and Processor Switched Off • Off (Power Down) Mode: Entire Chip Shut Down Except for Force Wake Up Pin (FWUP) that Re-activates the Device. 100 nA Current Consumption. In Active Mode, Dynamic Power Consumption = EXTERNAL RESET LENGTH 60 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 13.3.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. • PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. • EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. 61 6257A–ATARM–20-Feb-08 Figure 13-5. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. Processor Startup 1 cycle = 2 cycles proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) Any XXX 0x3 = Software Reset SRCMP in RSTC_SR 13.3.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. • If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. 62 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Figure 13-6. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 2 cycles proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 Any XXX 0x2 = Watchdog Reset NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 13.3.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • General Reset • Backup Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed below: • When in User Reset: – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. – A software reset is impossible, since the processor reset is being activated. • When in Software Reset: – A watchdog event has priority over the current state. – The NRST has no effect. • When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. 13.3.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. 63 6257A–ATARM–20-Feb-08 • SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. • NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. • URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 13-7). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 13-7. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization NRST NRSTL 2 cycle resynchronization URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 64 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 13.4 Reset Controller (RSTC) User Interface Register Mapping Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read-write Reset 0x0000_0000 0x0000_0000 Table 13-1. Offset 0x00 0x04 0x08 65 6257A–ATARM–20-Feb-08 13.4.1 Name: Reset Controller Control Register RSTC_CR Write-only 30 29 28 KEY 27 26 25 24 Access Type: 31 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 – 20 – 12 – 4 – 19 – 11 – 3 EXTRST 18 – 10 – 2 PERRST 17 – 9 16 – 8 – 0 PROCRST 1 – • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 66 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 13.4.2 Name: Reset Controller Status Register RSTC_SR Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 25 – 17 SRCMP 9 RSTTYP 1 – 24 – 16 NRSTL 8 Access Type: 31 – 23 – 15 – 7 – 2 – 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. • RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. RSTTYP 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Reset Type General Reset Backup Reset Watchdog Reset Software Reset User Reset Comments First power-up Reset (Power-on Reset or NRSTB asserted) Return from Backup mode Watchdog fault occurred Processor reset required by the software NRST pin detected low • NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy. 67 6257A–ATARM–20-Feb-08 13.4.3 Name: Reset Controller Mode Register RSTC_MR Read-write 30 29 28 KEY 27 26 25 24 Access Type: 31 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 20 – 12 – 4 URSTIEN 19 – 11 18 – 10 ERSTL 17 – 9 16 – 8 3 – 2 – 1 – 0 URSTEN • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. • URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 68 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 14. Real-time Clock (RTC) 14.1 Overview The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator. Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/year/century. 14.2 Block Diagram Figure 14-1. RTC Block Diagram Crystal Oscillator: SLCK 32768 Divider Time Date Bus Interface Bus Interface Entry Control Interrupt Control RTC Interrupt 14.3 14.3.1 Product Dependencies Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. Interrupt The RTC Interrupt is connected to interrupt source 1 (IRQ1) of the advanced interrupt controller. This interrupt line is due to the OR-wiring of the system peripheral interrupt lines (System Timer, Real Time Clock, Power Management Controller, Memory Controller, etc.). When a system interrupt occurs, the service routine must first determine the cause of the interrupt. This is done by reading the status registers of the above system peripherals successively. 14.3.2 69 6257A–ATARM–20-Feb-08 14.4 Functional Description The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. The valid year range is 1900 to 2099, a two-hundred-year Gregorian calendar achieving full Y2K compliance. The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years, including year 2000). This is correct up to the year 2099. After hardware reset, the calendar is initialized to Thursday, January 1, 1998. 14.4.1 Reference Clock The reference clock is Slow Clock (SLCK). It can be driven by the Atmel cell OSC55 or OSC56 (or an equivalent cell) and an external 32.768 kHz crystal. During low power modes of the processor (idle mode), the oscillator runs and power consumption is critical. The crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy. 14.4.2 Timing The RTC is updated in real time at one-second intervals in normal mode for the counters of seconds, at one-minute intervals for the counter of minutes and so on. Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required. 14.4.3 Alarm The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition: • If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second. • If only the “seconds” field is enabled, then an alarm is generated every minute. Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days. 14.4.4 Error Checking Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is done for the alarm. The following checks are performed: 70 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 1. Century (check if it is in range 19 - 20) 2. Year (BCD entry check) 3. Date (check range 01 - 31) 4. Month (check if it is in BCD range 01 - 12, check validity regarding “date”) 5. Day (check range 1 - 7) 6. Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is not set if RTC is set in 24-hour mode; in 12-hour mode check range 01 - 12) 7. Minute (check BCD and range 00 - 59) 8. Second (check BCD and range 00 - 59) Note: If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value can be programmed and the returned value on RTC_TIME will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIME register) to determine the range to be checked. 14.4.5 Updating Time/Calendar To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the Control Register. Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month, date, day). Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status Register. Once the bit reads 1, it is mandatory to clear this flag by writing the corresponding bit in RTC_SCCR. The user can now write to the appropriate Time and Calendar register. Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control When entering programming mode of the calendar fields, the time fields remain enabled. When entering the programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the calendar logic circuity (downstream for low-power considerations). It is highly recommended to prepare all the fields to be updated before entering programming mode. In successive update operations, the user must wait at least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these bits again. This is done by waiting for the SEC flag in the Status Register before setting UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared. 71 6257A–ATARM–20-Feb-08 Figure 14-2. Update Sequence Begin Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR Polling or IRQ (if enabled) ACKUPD =1? No Yes Clear ACKUPD bit in RTC_SCCR Update Time andor Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR End 72 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 14.5 Real-time Clock (RTC) User Interface Register Mapping Register Control Register Mode Register Time Register Calendar Register Time Alarm Register Calendar Alarm Register Status Register Status Clear Command Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Valid Entry Register Reserved Register Name RTC_CR RTC_MR RTC_TIMR RTC_CALR RTC_TIMALR RTC_CALALR RTC_SR RTC_SCCR RTC_IER RTC_IDR RTC_IMR RTC_VER – Access Read-write Read-write Read-write Read-write Read-write Read-write Read-only Write-only Write-only Write-only Read-only Read-only – Reset 0x0 0x0 0x0 0x01819819 0x0 0x01010000 0x0 ------0x0 0x0 – Table 14-1. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0xFC 73 6257A–ATARM–20-Feb-08 14.5.1 Name: RTC Control Register RTC_CR Access Type: Read-write 31 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 CALEVSEL 8 – 7 – 6 – 5 – 4 – 3 – 2 1 TIMEVSEL 0 – – – – – – UPDCAL UPDTIM • UPDTIM: Update Request Time Register 0 = No effect. 1 = Stops the RTC time counting. Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the Status Register. • UPDCAL: Update Request Calendar Register 0 = No effect. 1 = Stops the RTC calendar counting. Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set. • TIMEVSEL: Time Event Selection The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL. 0 = Minute change. 1 = Hour change. 2 = Every day at midnight. 3 = Every day at noon. • CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL. 0 = Week change (every Monday at time 00:00:00). 1 = Month change (every 01 of each month at time 00:00:00). 2, 3 = Year change (every January 1 at time 00:00:00). 74 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 14.5.2 Name: RTC Mode Register RTC_MR Access Type: Read-write 31 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – – – – – HRMOD • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. All non-significant bits read zero. 75 6257A–ATARM–20-Feb-08 14.5.3 Name: RTC Time Register RTC_TIMR Access Type: Read-write 31 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 AMPM 14 13 12 11 HOUR 10 9 8 – 7 6 5 4 MIN 3 2 1 0 – SEC • SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • HOUR: Current Hour The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode. 0 = AM. 1 = PM. All non-significant bits read zero. 76 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 14.5.4 Name: RTC Calendar Register RTC_CALR Access Type: Read-write 31 30 29 28 27 26 25 24 – 23 – 22 21 20 19 DATE 18 17 16 DAY 15 14 13 12 11 MONTH 10 9 8 YEAR 7 6 5 4 3 2 1 0 – CENT • CENT: Current Century The range that can be set is 19 - 20 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MONTH: Current Month The range that can be set is 01 - 12 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • DAY: Current Day in Current Week The range that can be set is 1 - 7 (BCD). The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. • DATE: Current Day in Current Month The range that can be set is 01 - 31 (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. 77 6257A–ATARM–20-Feb-08 14.5.5 Name: RTC Time Alarm Register RTC_TIMALR Access Type: Read-write 31 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 HOUREN 15 AMPM 14 13 12 11 HOUR 10 9 8 MINEN 7 6 5 4 MIN 3 2 1 0 SECEN SEC • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. • SECEN: Second Alarm Enable 0 = The second-matching alarm is disabled. 1 = The second-matching alarm is enabled. • MIN: Minute Alarm This field is the alarm field corresponding to the BCD-coded minute counter. • MINEN: Minute Alarm Enable 0 = The minute-matching alarm is disabled. 1 = The minute-matching alarm is enabled. • HOUR: Hour Alarm This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled. 1 = The hour-matching alarm is enabled. 78 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 14.5.6 Name: RTC Calendar Alarm Register RTC_CALALR Access Type: Read-write 31 30 29 28 27 26 25 24 DATEEN 23 – 22 21 20 19 DATE 18 17 16 MTHEN 15 – 14 – 13 12 11 MONTH 10 9 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – – – – – – • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. • MTHEN: Month Alarm Enable 0 = The month-matching alarm is disabled. 1 = The month-matching alarm is enabled. • DATE: Date Alarm This field is the alarm field corresponding to the BCD-coded date counter. • DATEEN: Date Alarm Enable 0 = The date-matching alarm is disabled. 1 = The date-matching alarm is enabled. 79 6257A–ATARM–20-Feb-08 14.5.7 Name: RTC Status Register RTC_SR Access Type: Read-only 31 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update 0 = Time and calendar registers cannot be updated. 1 = Time and calendar registers can be updated. • ALARM: Alarm Flag 0 = No alarm matching condition occurred. 1 = An alarm matching condition has occurred. • SEC: Second Event 0 = No second event has occurred since the last clear. 1 = At least one second event has occurred since the last clear. • TIMEV: Time Event 0 = No time event has occurred since the last clear. 1 = At least one time event has occurred since the last clear. The time event is selected in the TIMEVSEL field in RTC_CTRL (Control Register) and can be any one of the following events: minute change, hour change, noon, midnight (day change). • CALEV: Calendar Event 0 = No calendar event has occurred since the last clear. 1 = At least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. 80 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 14.5.8 Name: RTC Status Clear Command Register RTC_SCCR Access Type: Write-only 31 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • SECCLR: Second Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • TIMCLR: Time Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • CALCLR: Calendar Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). 81 6257A–ATARM–20-Feb-08 14.5.9 Name: RTC Interrupt Enable Register RTC_IER Access Type: Write-only 31 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0 = No effect. 1 = The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0 = No effect. 1 = The alarm interrupt is enabled. • SECEN: Second Event Interrupt Enable 0 = No effect. 1 = The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable 0 = No effect. 1 = The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable 0 = No effect. • 1 = The selected calendar event interrupt is enabled. 82 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 14.5.10 Name: RTC Interrupt Disable Register RTC_IDR Access Type: Write-only 31 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0 = No effect. 1 = The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0 = No effect. 1 = The alarm interrupt is disabled. • SECDIS: Second Event Interrupt Disable 0 = No effect. 1 = The second periodic interrupt is disabled. • TIMDIS: Time Event Interrupt Disable 0 = No effect. 1 = The selected time event interrupt is disabled. • CALDIS: Calendar Event Interrupt Disable 0 = No effect. 1 = The selected calendar event interrupt is disabled. 83 6257A–ATARM–20-Feb-08 14.5.11 Name: RTC Interrupt Mask Register RTC_IMR Access Type:Read-only 31 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is disabled. 1 = The acknowledge for update interrupt is enabled. • ALR: Alarm Interrupt Mask 0 = The alarm interrupt is disabled. 1 = The alarm interrupt is enabled. • SEC: Second Event Interrupt Mask 0 = The second periodic interrupt is disabled. 1 = The second periodic interrupt is enabled. • TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled. 1 = The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled. 1 = The selected calendar event interrupt is enabled. 84 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 14.6 Name: RTC Valid Entry Register RTC_VER Access Type: Read-only 31 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0 = No invalid data has been detected in RTC_TIMR (Time Register). 1 = RTC_TIMR has contained invalid data since it was last programmed. • NVCAL: Non-valid Calendar 0 = No invalid data has been detected in RTC_CALR (Calendar Register). 1 = RTC_CALR has contained invalid data since it was last programmed. • NVTIMALR: Non-valid Time Alarm 0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register). 1 = RTC_TIMALR has contained invalid data since it was last programmed. • NVCALALR: Non-valid Calendar Alarm 0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register). 1 = RTC_CALALR has contained invalid data since it was last programmed. 85 6257A–ATARM–20-Feb-08 86 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 15. Periodic Interval Timer (PIT) 15.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 Block Diagram Figure 15-1. Periodic Interval Timer PIT_MR PIV =? PIT_MR PITIEN set 0 PIT_SR PITS reset pit_irq 0 0 1 0 1 12-bit Adder read PIT_PIVR MCK 20-bit Counter Prescaler MCK/16 CPIV PIT_PIVR PICNT CPIV PIT_PIIR PICNT 87 6257A–ATARM–20-Feb-08 15.3 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 15-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. 88 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Figure 15-2. Enabling/Disabling PIT with PITEN APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN APB cycle CPIV PICNT PITS (PIT_SR) APB Interface 0 1 0 PIV - 1 PIV 1 0 0 1 read PIT_PIVR 89 6257A–ATARM–20-Feb-08 15.4 Periodic Interval Timer (PIT) User Interface Register Mapping Register Mode Register Status Register Periodic Interval Value Register Periodic Interval Image Register Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR Access Read-write Read-only Read-only Read-only Reset 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 Table 15-1. Offset 0x00 0x04 0x08 0x0C 90 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 15.4.1 Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type: 31 – 23 – 15 Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 PIV 27 – 19 26 – 18 PIV 11 10 9 8 25 PITIEN 17 24 PITEN 16 7 6 5 4 PIV 3 2 1 0 • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). • PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. 91 6257A–ATARM–20-Feb-08 15.4.2 Periodic Interval Timer Status Register Register Name: PIT_SR Access Type: 31 – 23 – 15 – 7 – Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 PITS • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 92 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 15.4.3 Periodic Interval Timer Value Register Register Name: PIT_PIVR Access Type: 31 Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 93 6257A–ATARM–20-Feb-08 15.4.4 Periodic Interval Timer Image Register Register Name: PIT_PIIR Access Type: 31 Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 94 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 16. Watchdog Timer (WDT) 16.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 16.2 Block Diagram Figure 16-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDT_CR WDRSTT reload 1 0 WDV 12-bit Down Counter WDT_MR WDD Current Value reload 1/128 SLCK 32 kHz) is connected to XIN, then the device will switch on the external clock. Else, XIN input is not considered. An higher frequency on XIN speeds up the programmer handshake. 167 6257A–ATARM–20-Feb-08 Table 20-17. Reset TAP Controller and Go to Select-DR-Scan TDI X X X X X X Xt TMS 1 1 1 1 1 0 1 Test-Logic Reset Run-Test/Idle Select-DR-Scan TAP Controller State 20.3.3 Read/Write Handshake The read/write handshake is done by carrying out read/write operations on two registers of the device that are accessible through the JTAG: • Debug Comms Control Register: DCCR • Debug Comms Data Register: DCDR Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data field, a 5-bit address field and a read/write bit. The data to be written is scanned into the 32-bit data field with the address of the register to the 5-bit address field and 1 to the read/write bit. A register is read by scanning its address into the address field and 0 into the read/write bit, going through the UPDATE-DR TAP state, then scanning out the data. Refer to the ARM7TDMI reference manuel for more information on Comm channel operations. Figure 20-7. TAP 8-bit DR Register TDI r/w 4 Address 5 0 31 Data 32 0 TDO Address Decoder Debug Comms Control Register Debug Comms Data Register A read or write takes place when the TAP controller enters UPDATE-DR state. Refer to the IEEE 1149.1 for more details on JTAG operations. • The address of the Debug Comms Control Register is 0x04. • The address of the Debug Comms Data Register is 0x05. The Debug Comms Control Register is read-only and allows synchronized handshaking between the processor and the debugger. – Bit 1 (W): Denotes whether the programmer can read a data through the Debug Comms Data Register. If the device is busy W = 0, then the programmer must poll until W = 1. 168 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary – Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms Data Register. If R = 1, data previously placed there through the scan chain has not been collected by the device and so the programmer must wait. The write handshake is done by polling the Debug Comms Control Register until the R bit is cleared. Once cleared, data can be written to the Debug Comms Data Register. The read handshake is done by polling the Debug Comms Control Register until the W bit is set. Once set, data can be read in the Debug Comms Data Register. 20.3.4 Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 20-3 on page 159. Commands are run by the programmer through the serial interface that is reading and writing the Debug Comms Registers. Flash Read Command This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at any valid address in the memory plane. This address must be word-aligned. The address is automatically incremented. Table 20-18. Read Command Read/Write Write Write Read Read ... Read DR Data (Number of Words to Read) ’ • Send a file (S): Send a file to a specified address – Address: Address in hexadecimal – Output: ‘>’. Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. • Receive a file (R): Receive data into a file from a specified address – Address: Address in hexadecimal – NbOfBytes: Number of bytes in hexadecimal to receive – Output: ‘>’ • Go (G): Jump to a specified address and execute the code – Address: Address to jump in hexadecimal – Output: ‘>’ • Get Version (V): Return the SAM-BA boot version – Output: ‘>’ 21.4.1 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the 175 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. 21.4.2 Xmodem Protocol The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: in which: – = 01 hex – = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) – = 1’s complement of the blk#. – = 2 bytes CRC16 Figure 21-3 shows a transmission using this protocol. Figure 21-3. Xmodem Transfer Example Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK Device 176 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 21.5 In-Application Programming (IAP) Feature The IAP feature is a function located in ROM that can be called by any software application. When called, this function sends the desired FLASH command to the EEFC and waits for the FLASH to be ready (looping while the FRDY bit is not set in the MC_FSR register). Since this function is executed from ROM, this allows FLASH programming (like sector write) to be done by code running in FLASH. The IAP function entry point is retrieved by reading the SWI vector in ROM (0x400008). This funtion takes one argument in parameter: the command to be sent to the EEFC. This function returns the value of the MC_FSR register. IAP software code example: (unsigned int) (*IAP_Function)(unsigned long); void main (void) { unsigned long FlashSectorNum = 200; unsigned long flash_cmd = 0; unsigned long flash_status = 0; /* Initialize the function pointer (retrieve function address from SWI vector) */ IAP_Function = ((unsigned long) (*)(unsigned long)) 0x400008; /* Send your data to the sector */ /* build the command to send to EFC */ flash_cmd = (0x5A 1MHz After Startup Time 2 18 50 Typ 1.6 2 Max 1.85 2.65 3 1.5 1.5 +10 55 5 30 1 Unit V MHz Frequency Supply Dependency % Frequency Temperature Dependency Duty Cycle tST IOSC Startup Time Current Consumption Standby Consumption % % µs µA µA 533 6257A–ATARM–20-Feb-08 35.4.3 XTAL Oscillator Characteristics Table 35-15. XTAL Oscillator Characteristics Symbol Freq Parameter Operating Frequency Supply Voltage Duty Cycle Rs < 50KΩ Startup Time Rs < 100KΩ (1) Conditions Normal mode with crystal VDDIO1 Domain Min Typ Max 32.768 Unit KHz V % 1.8 40 CL = 12.5pF CL = 6pF CL = 12.5pF CL = 6pF CL = 12.5pF CL = 6pF CL = 12.5pF CL = 6pF 650 450 900 650 50 3.6 60 900 300 1200 500 1400 1200 1600 1400 5 0.1 ms Rs < 50KΩ Current consumption Rs < 100KΩ (1) nA IDDST PON Rf CLEXT CL Notes: Standby Current Consumption Drive level Internal resistor Maximum external capacitor on XIN and XOUT Internal Equivalent Load Capacitance 1. RS is the series resitor.. Standby mode @ 3.6V nA µW MΩ between XIN and XOUT 10 20 pF pF Integrated Load Capacitance (XIN and XOUT in series) 2.0 2.5 3.0 AT91SAM7L CL XIN XOUT CLEXT CLEXT 35.4.4 Crystal Characteristics Table 35-16. Crystal Characteristics Symbol ESR CM CSHUNT Parameter Equivalent Series Resistor Rs Motional capacitance Shunt capacitance Conditions Crystal @ 32.768KHz Crystal @ 32.768KHz Crystal @ 32.768KHz 0.6 0.6 Min Typ 50 Max 100 3 2 Unit KΩ fF pF 534 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 35.4.5 XIN Clock Characteristics Table 35-17. XIN Clock Electrical Characteristics (In bypass mode) Symbol 1/(tCPXIN) 1/(tCPXIN) tCPXIN tCPXIN tCHXIN tCHXIN tCLXIN tCLXIN tCLCH tCHCL CIN RIN VXIN_IL VXIN_IH Note: Parameter XIN Clock Frequency XIN Clock Frequency XIN Clock Period XIN Clock Period XIN Clock High Half-period XIN Clock High Half-period XIN Clock Low Half-period XIN Clock Low Half-period Rise Time Fall Time XIN Input Capacitance XIN Pull-down Resistor VXIN Input Low-level Voltage VXIN Input High-level Voltage 1. These characteristics apply only in FFPI mode 2. These characteristics apply only when the XTAL Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBYPASS = 1 in the CKGR_MOR register, see the Clock Generator Main Oscillator Register. 3 -0.3 0.8 x VVDDIO1 Conditions (1) (2) (1) (2) (1) (2) (1) (2) Min Max 10 44 Units MHz kHz ns ns µs µs ns µs ns ns 100 44 22 11 50 11 400 400 6 5 0.2 x VVDDIO1 VVDDIO1+0.3 pF MΩ V V tCPXIN VXIN_IH VXIN_IL tCPXIN tCLCH tCHXIN tCHCL tCPXIN 535 6257A–ATARM–20-Feb-08 35.4.6 External Clock CLKIN Characteristics Table 35-18. External Clock CLKIN Characteristics (VDDCORE set at 1.80V) Symbol 1/(tCPCLKIN) tCPCLKIN tCHCLKIN tCLCLKIN Parameter CLKIN Clock Frequency CLKIN Clock Period CLKIN Clock High Half-period CLKIN Clock Low Half-period 31.0 14.5 14.3 Min Max 32 Units MHz ns ns ns Table 35-19. External Clock CLKIN Characteristics (VDDCORE set at 1.75V) Symbol 1/(tCPCLKIN) tCPCLKIN tCHCLKIN tCLCLKIN Parameter CLKIN Clock Frequency CLKIN Clock Period CLKIN Clock High Half-period CLKIN Clock Low Half-period 32.4 15.2 15.0 Min Max 30.8 Units MHz ns ns ns Table 35-20. Externa Clock CLKIN Characteristics (VDDCORE set at 1.65V) Symbol 1/(tCPCLKIN) tCPCLKIN tCHCLKIN tCLCLKIN Parameter CLKIN Clock Frequency CLKIN Clock Period CLKIN Clock High Half-period CLKIN Clock Low Half-period 35.7 16.7 16.5 Min Max 28 Units MHz ns ns ns Table 35-21. External Clock CLKIN Characteristics (VDDCORE set at 1.55V) Symbol 1/(tCPCLKIN) tCPCLKIN tCHCLKIN tCLCLKIN Parameter CLKIN Clock Frequency CLKIN Clock Period CLKIN Clock High Half-period CLKIN Clock Low Half-period 40.0 18.7 18.5 Min Max 25 Units MHz ns ns ns 536 AT91SAM7L128/64 Preliminary 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 35.5 PLL Characteristics Table 35-22. Phase Lock Loop Characteristics Symbol Vdd FOUT FIN Parameter Supply Voltage Output Frequency Input Frequency Connected to SCLK Active mode @ 20MHz @1.8V Active mode @ 30MHz @1.8V Active mode @ 40MHz @1.8V Standby mode Note: Startup time depends on PLL RC filter. A calculation tool is provided by Atmel. Conditions Supplied by VDDCORE Min 1.60 18 20 30 30 445 490 535 0.005 47 44 505 555 605 0.5 Typ Max Unit V MHz KHz µA µA IPLL Current Consumption 35.6 ADC Characteristics Table 35-23. Channel Conversion Time and ADC Clock Parameter ADC Clock Frequency ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Throughput Rate Notes: ADC Clock = 6MHz ADC Clock = 10MHz ADC Clock = 6MHz ADC Clock = 10MHz Conditions 10-bit resolution mode 8-bit resolution mode Return from Idle Mode 500 1.67 1 460(1) 660(2) Min Typ Max 6 10 15 Units MHz MHz µs ns µs kSPS 1. Corresponds to 13 clock cycles at 6 MHz: 3 clock cycles for track and hold acquisition time and 10 clock cycles for conversion. 2. Corresponds to 15 clock cycles at 10 MHz: 5 clock cycles for track and hold acquisition time and 10 clock cycles for conversion Table 35-24. External Voltage Reference Input Parameter ADVREF Input Voltage Range ADVREF Average Current Current Consumption on VDDCORE ADC Clock = 6MHz Conditions Min 1.65 Typ 1.8 Max VDDCORE 250 2.2 Units V µA mA The user can drive ADC input with impedance up to: • ZOUT ≤ (SHTIM -440) x 20 in 8-bit resolution mode • ZOUT ≤ (SHTIM -550) x 16.6 in 10-bit resolution mode with SHTIM (Sample and Hold Time register) expressed in ns and ZOUT expressed in ohms. 537 6257A–ATARM–20-Feb-08 Table 35-25. Analog Inputs Parameter Input Voltage Range Input Leakage Current Input Capacitance 6.5 Min 0 Typ Max VADVREF ±0.5 8.5 µA pF Units Table 35-26. Transfer Characteristics Parameter Resolution Integral Non-linearity Differential Non-linearity Offset Error Gain Error Absolute accuracy No missing code Conditions Min Typ 10 ±2 ±1 ±3 ±2 ±4.2 Max Units Bit LSB LSB LSB LSB LSB 35.7 Regulated Charge Pump Characteristics Table 35-27. Regulated Charge Pump Characteristics Symbol VVDDINLCD VVDD3V6 Parameter Charge Pump Supply Voltage Output Voltage IO = 4 mA max Active, No load, with clock, CL=4.7µF,ESR=1Ω Onto VDDIO1 =1.8V IVDDINLCD Current consumption Onto VDDINLCD = 3.6V Onto VDDIO1 = 1.8V Onto VDDINLCD = 3.6V TSTART Startup Time External charge capacitor External charge capacitor External storage capacitor Between CAPP1 and CAPM1 (Tolerance +/- 10%) Between CAPP2 and CAPM2 (Tolerance +/- 10%) On VDD3V6 (Tolerance +/- 10%,ESR =