HCPL-314J-500E

HCPL-314J 0.4 Amp Output Current IGBT Gate Drive Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The HCPL-314J family of devices consists of an AlGaAs LED optically coupled to an integrated circuit with a power output stage. These optocouplers are ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving small or medium power IGBTs. For IGBTs with higher ratings the HCPL-3150(0.5A) or HCPL-3120 (2.0A) optocouplers can be used. • 0.4 A minimum peak output current • High speed response: 0.7 µs max. propagation delay over temp. range • Ultra high CMR: min. 25 kV/µs at VCM = 1.5 kV • Bootstrappable supply current: max. 3 mA • Wide operating temp. range: -40°C to 100°C • Wide VCC operating range: 10 V to 30 V over temp. range • Available in DIP8 (single) and SO16 (dual) package • Safety approvals: UL recognized, 5000 Vrms for 1 minute. CSA approval. IEC/EN/DIN EN 60747-5-5 approval VIORM=1414 Vpeak Functional Diagram N/C 1 16 VCC ANODE 2 15 VO CATHODE 3 14 VEE ANODE 6 11 VCC CATHODE 7 10 VO N/C 8 9 VEE SHIELD SHIELD HCPL-314J Truth Table LED  VO OFF LOW ON HIGH Applications • • • • • • Isolated IGBT/power MOSFET gate drive AC and brushless dc motor drives Inverters for appliances Industrial inverters Switch Mode Power Supplies (SMPS) Uninterruptable Power Supplies (UPS) Selection Guide Package Type Part Number SO16 HCPL-314J Number of Channels 2 A 0.1 µF bypass capacitor must be connected between pins VCC and VEE. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this datasheet are not to be used in military or aerospace applications or environments. Ordering Information HCPL-314J is UL Recognized with 5000 Vrms for 1 minute per UL1577. Option Part number RoHS Compliant Non RoHS Compliant -000E No option -500E #500 HCPL-314J Package Surface Mount Tape & Reel X SO-16 X X IEC/EN/DIN EN 60747-5-5 Quantity X 45 per tube X 850 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-314J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/ DIN EN 60747-5-5 Safety Approval in RoHS compliant. Example 2: HCPL-314J to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘. Package Outline Drawing 16-Lead Surface Mount Package 0.457 (0.018) 16 15 14 LAND PATTERN RECOMMENDATION 1.270 (0.050) 11 10 0.64 (0.025) 9 TYPE NUMBER DATE CODE A XXXX YYWW EEE AVAGO LEAD-FREE 7.493 ± 0.254 (0.295 ± 0.010) PIN 1 DOT 11.63 (0.458) LOT ID 2.16 (0.085) 1 2 3 6 7 8 10.312 ± 0.254 (0.406 ± 0.10) 8.763 ± 0.254 (0.345 ± 0.010) 9° 0.457 (0.018) Dimensions in Millimeters (Inches) 3.505 ± 0.127 (0.138 ± 0.005) 0-8° 0.64 (0.025) MIN. 10.363 ± 0.254 (0.408 ± 0.010) ALL LEADS TO BE COPLANAR ± 0.05 (0.002) 0.203 ± 0.076 (0.008 ± 0.003) STANDOFF Floating lead protrusion is 0.25 mm (10 mils) Max. Note: Initial and continued variation in color of the white mold compound is normal and does not affect performance or reliability of the device 2 Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The HCPL-314J has been approved by the following organizations: IEC/EN/DIN EN 60747-5-5 Approval under: DIN EN 60747-5-5 (VDE 0884-5):2011-11 EN 60747-5-5:2011 Approval under UL 1577, component recognition program up to VISO = 5000 VRMS. File E55361. UL Approval under CSA Component Acceptance Notice #5, File CA 88324. CSA IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Description Symbol Characteristic Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000Vrms I - IV I - IV I - IV I - III Climatic Classification 55/100/21 Pollution Degree (DIN VDE 0110/1.89) Unit 2 Maximum Working Insulation Voltage VIORM 1414 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 2652 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC VPR 2262 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 8000 Vpeak Safety-limiting values - maximum values allowed in the event of a failure. Case Temperature Input Current** Output Power** TS IS,INPUT PS, OUTPUT 175 400 1200 °C mA mW Insulation Resistance at TS, VIO = 500 V RS >109 Ω OUTPUT POWER – PS, INPUT CURRENT – IS * Refer to IEC/EN/DIN EN 60747-5-5 Optoisolator Safety Standard section of the Avago Regulatory Guide to Isolation Circuits, AV02-2041EN for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figure for dependence of PS and IS on ambient temperature. 3 800 PS (mW) IS (mA) 700 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 TS – CASE TEMPERATURE – °C Insulation and Safety Related Specifications Parameter Symbol HCPL-314J Units Conditions Minimum External Air Gap (Clearance) L(101) 8.3 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8.3 mm Measured from input terminals to output terminals, shortest distance path along body. 0.5 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. >175 V DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -55 125 °C Note Operating Temperature TA -40 100 °C Average Input Current IF(AVG) 25 mA Peak Transient Input Current (5 V 9, 15 Threshold Input Voltage High to Low VFHL 0.8 Input Forward Voltage VF 1.2 IF = 10 mA 16 Temperature Coefficient of Input Forward Voltage ∆VF/∆TA Input Reverse Breakdown Voltage BVR Input Capacitance CIN 3 VCC-1.8 15 V 1.5 1.8 V -1.2 mV/°C 10 V IR = 100 µA 70 pF f = 1 MHz, VF = 0 V Switching Specifications (AC) Over recommended operating conditions unless otherwise specified. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High Output Level tPLH 0.1 0.2 0.7 µs 10, 11, 12, 13, 14 Propagation Delay Time to Low Output Level tPHL 0.1 0.3 0.7 µs Propagation Delay Difference Between Any Two Parts or Channels PDD -0.5 0.5 µs Rg = 47 Ω, Cg = 3 nF, f = 10 kHz, Duty Cycle =50%, IF = 8 mA, VCC = 30 V Rise Time tR 50 ns Fall Time tF 50 ns Output High Level Common Mode Transient Immunity |CMH| 25 35 kV/µs TA = 25°C, VCM = 1.5 kV 18 11, 12 Output Low Level Common Mode Transient Immunity |CML| 25 35 kV/µs 18 11, 13 5 14, 17 10 Package Characteristics For each channel unless otherwise specified. Parameter Symbol Min. Units Test Conditions Input-Output Momentary Withstand Voltage VISO 5000 Typ. Max. Vrms 8,9 Output-Output Momentary Withstand Voltage VO-O 1500 Vrms TA=25°C, RH 6.0 V). 13. Common mode transient immunity in a low state is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e. Vo < 1.0 V). 14. This load condition approximates the gate load of a 1200 V/25 A IGBT. 15. For each channel. The power supply current increases when operating frequency and Qg of the driven IGBT increases. 16. Device considered a two terminal device: Channel one output side pins shorted together, and channel two output side pins shorted together. 6 -1.0 -1.5 -2.0 -25 0 25 50 75 100 125 0.34 0.32 0.30 -50 TA – TEMPERATURE – °C Figure 1. VOH vs. Temperature. IOL – OUTPUT LOW CURRENT – A 0.41 0.40 -25 0 25 50 75 100 125 Figure 4. VOL vs. Temperature. 75 100 125 0.450 0.445 -25 0 25 50 75 100 125 0.6 0.4 ICCL ICCH 0.2 -25 0 25 50 75 100 125 TA – TEMPERATURE – °C Figure 7. ICC vs. Temperature. ICC – SUPPLY CURRENT – mA 0.8 -3 -4 -5 -6 0.4 0.6 IOH – OUTPUT HIGH CURRENT – A 20 15 10 5 0 0.8 0.6 0.4 ICCL ICCH 0.2 15 20 25 VCC – SUPPLY VOLTAGE – V Figure 8. ICC vs. VCC. 100 200 300 400 500 600 700 0 Figure 6. VOL vs. IOL. 1.0 0 10 0.2 0 IOL – OUTPUT LOW CURRENT – mA 1.2 1.0 -2 TA – TEMPERATURE – °C Figure 5. IOL vs. Temperature. 1.2 VOH -1 25 0.455 0.440 -50 0 Figure 3. VOH vs. IOH. 0.460 1.4 ICC – SUPPLY CURRENT – mA 50 0.465 TA – TEMPERATURE – °C 7 25 0.470 0.42 0 -50 0 Figure 2. IOH vs. Temperature. 0.43 0.39 -50 -25 TA – TEMPERATURE – °C 0.44 VOL – OUTPUT LOW VOLTAGE – V 0.36 VOL – OUTPUT LOW VOLTAGE – V -2.5 -50 0.38 30 IFLH – LOW TO HIGH CURRENT THRESHOLD – mA -0.5 (VOH-VCC) – OUTPUT HIGH VOLTAGE DROP – V 0.40 IOH – OUTPUT HIGH CURRENT – A (VOH-VCC) – HIGH OUTPUT VOLTAGE DROP – V 0 3.5 3.0 2.5 2.0 1.5 -50 -25 0 25 50 75 100 125 TA – TEMPERATURE – °C Figure 9. IFLH vs. Temperature. 300 200 100 0 10 TPLH TPHL 15 20 25 300 200 100 0 30 VCC – SUPPLY VOLTAGE – V 15 18 350 TPLH TPHL 300 250 0 50 100 150 200 Figure 13. Propagation Delay vs. Rg. 20 15 10 5 1.4 1.6 100 TPLH TPHL 1.8 VF – FORWARD VOLTAGE – V Figure 16. Input Current vs. Forward Voltage. 0 25 50 75 100 125 Figure 12. Propagation Delay vs. Temperature. 300 200 100 0 -25 35 TPLH TPHL 0 20 40 60 80 Cg – LOAD CAPACITANCE – nF Figure 14. Propagation Delay vs. Cg. 25 0 1.2 200 TA – TEMPERATURE – °C VO – OUTPUT VOLTAGE – V TP – PROPAGATION DELAY – ns TP – PROPAGATION DELAY – ns 12 300 0 -50 400 Rg – SERIES LOAD RESISTANCE – Ω IF – FORWARD CURRENT – mA 9 Figure 11. Propagation Delay vs. IF. 400 8 6 400 IF – FORWARD LED CURRENT – mA Figure 10. Propagation Delay vs. VCC. 200 500 TP – PROPAGATION DELAY – ns 400 TP – PROPAGATION DELAY – ns TP – PROPAGATION DELAY – ns 400 100 30 25 20 15 10 5 0 -5 0 1 2 3 4 5 IF – FORWARD LED CURRENT – mA Figure 15. Transfer Characteristics. 6 1 8 0.1 µF IF = 7 to 16 mA + 10 KHz – 500 Ω 50% DUTY CYCLE 2 + – 7 IF VCC = 15 to 30 V tr tf VO 3 6 90% 47 Ω 50% VOUT 3 nF 4 10% 5 tPLH tPHL Figure 17. Propagation Delay Test Circuit and Waveforms. VCM IF 5V + – 1 δt 0.1 µF A B δV 8 2 VO 6 4 5 VCC = 30 V VO – Figure 18. CMR Test Circuit and Waveforms. 9 VOH SWITCH AT A: IF = 10 mA SWITCH AT B: IF = 0 mA + ∆t ∆t + – VO VCM = 1500 V VCM 0V 7 3 = VOL Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL-314J has a very low maximum VOL specification of 1.0 V. Minimizing Rg and the lead inductance from the HCPL-314J to the IGBT gate and emitter (possibly by mounting the HCPL-314J on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 19. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL-314J input as this can result in unwanted coupling of transient signals into HCPL-314J +5 V CONTROL INPUT the input of HCPL-314J and degrade performance. (If the IGBT drain must be routed near the HCPL-314J input, then the LED should be reverse biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-314J.) An external clamp diode may be connected between pins 14 & 15 and pins 9 & 10 (as shown in Figure 19) for the protection of HCPL-314J in the case of IGBTs switching inductive load. 270 Ω 1 0.1 µF 2 74XX OPEN COLLECTOR 16 3 + – 15 FLOATING SUPPLY VCC = 18 V Rg VOL 14 GND 1 +5 V CONTROL INPUT 3-PHASE AC 6 11 0.1 µF 270 Ω 74XX OPEN COLLECTOR 7 10 8 9 GND 1 Figure 19. Recommended LED Drive and Application Circuit for HCPL-314J. 10 + HVDC + – VCC = 18 V Rg - HVDC Step 1: Calculate Rg minimum from the IOL peak specification. The IGBT and Rg in Figure 24 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-314J. V – VOL Rg ≥ CC     IOLPEAK 24 V – 5 V      0.6A   =   = 32 Ω The VOL value of 5 V in the previous equation is the VOL at the peak current of 0.6A. (See Figure 6). Step 2: Check the HCPL-314J power dissipation and increase Rg if necessary. The HCPL-314J total power dissipation (PT ) is equal to the sum of the emitter power (PE) and the output power (PO). PT = PE + PO PE = IF • VF • Duty Cycle PO = PO(BIAS) + PO(SWITCHING) = ICC • VCC + ESW (Rg,Qg)• f = (ICCBIAS + KICC • Qg • f) • VCC + ESW (Rg,Qg) • f where KICC • Qg • f is the increase in ICC due to switching and KICC is a constant of 0.001 mA/(nC*kHz). For the circuit in Figure 19 with IF (worst case) = 10 mA, Rg = 32 Ω, Max Duty Cycle = 80%, Qg = 100 nC, f = 20 kHz and TAMAX = 85°C: PE = 10 mA • 1.8 V • 0.8 = 14 mW PO = (3 mA + (0.001 mA/(nC • kHz)) • 20 kHz • 100 nC) • 24 V + 0.4 µJ • 20 kHz = 128 mW < 260 mW (PO(MAX) @ 85°C) The value of 3 mA for ICC in the previous equation is the max. ICC over entire operating temperature range. Since PO for this case is less than PO(MAX), Rg = 32 Ω is alright for the power dissipation. Esw – ENERGY PER SWITCHING CYCLE – µJ Selecting the Gate Resistor (Rg) 4.0 Qg = 50 nC Qg = 100 nC Qg = 200 nC Qg = 400 nC 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 20 40 60 80 100 Rg – GATE RESISTANCE – Ω Figure 20. Energy Dissipated in the HCPL-314J and for Each IGBT Switching Cycle. LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 21. The HCPL-314J improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins 5-8 as shown in Figure 22. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 19), can achieve 10 kV/µs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. 11 1 CLEDP 2 8 1 7 2 6 3 5 4 CLEDO1 8 CLEDP 7 CLEDO2 3 CLEDN 4 1 2 + VSAT – 5 SHIELD Figure 22. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers. Figure 21. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers. +5 V 6 CLEDN 8 0.1 µF CLEDP 7 + – VCC = 18 V ILEDP 3 6 CLEDN 4 5 SHIELD Rg ••• ••• * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING –dVCM/dt. + – VCM Figure 23. Equivalent Circuit for Figure 17 During Common Mode Transient. 1 8 +5 V 2 Q1 1 8 +5 V 3 CLEDP CLEDN 7 2 6 3 5 4 CLEDP CLEDN 7 6 ILEDN 4 SHIELD Figure 24. Not Recommended Open Collector Drive Circuit. 12 SHIELD 5 Figure 25. Recommended LED Drive Circuit for Ultra-High CMR IPM Dead Time and Propagation Delay Specifications. CMR with the LED On (CMRH) IPM Dead Time and Propagation Delay Specifications A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 8 mA provides adequate margin over the maximum IFLH of 5 mA to achieve 10 kV/µs CMR. The HCPL-314J includes a Propagation Delay Difference (PDD) specification intended to help designers minimize “dead time” in their power inverter designs. Dead time is the time high and low side power transistors are off. Any overlap in Ql and Q2 conduction will result in large currents flowing through the power devices from the high-voltage to the low-voltage motor rails. To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 26. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDD max, which is specified to be 500 ns over the operating temperature range of -40° to 100°C. CMR with the LED Off (CMRL) A high CMR LED drive circuit must keep the LED off (VF ≤ VF(OFF)) during common mode transients. For example, during a -dVCM/dt transient in Figure 23, the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF) the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure 24, can not keep the LED off during a +dVCM/dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMR1 performance. The alternative drive circuit which like the recommended application circuit (Figure 19), does achieve ultra high CMR performance by shunting the LED in the off state. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specification as shown in Figure 27. The maximum dead time for the HCPL-314J is 1 µs (= 0.5 µs - (-0.5 µs)) over the operating temperature range of - 40°C to 100°C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. 13 ILED1 VOUT1 Q1 ON Q1 OFF Q2 ON VOUT2 ILED2 Q2 OFF tPHL MAX tPLH MIN PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 26. Minimum LED Skew for Zero Dead Time. ILED1 VOUT1 Q1 ON Q1 OFF Q2 ON VOUT2 Q2 OFF ILED2 tPHL MIN tPHL MAX tPLH MIN tPLH MAX (tPHL-tPLH) MAX PDD* MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN) = (tPHL MAX - tPLH MIN) – (tPHL MIN - tPLH MAX) = PDD* MAX – PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 27. Waveforms for Dead Time. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved. Obsoletes 5989-2943EN AV02-0169EN - March 9, 2015