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CDCL1810A
SLLSEL1 – NOVEMBER 2014
CDCL1810A 1.8V, 10 Output, High-Performance Clock Distributor
1 Features
3 Description
•
•
The CDCL1810A is a high-performance clock
distributor. The programmable dividers, P0 and P1,
give a high flexibility to the ratio of the output
frequency to the input frequency: FOUT = FIN/P, where
P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80.
1
•
•
•
•
•
•
•
•
•
•
•
Single 1.8 V Supply
High-Performance Clock Distributor with 10
Outputs
Low Input-to-Output Additive Jitter: as low as 10fs
RMS
Low-Voltage Differential Signaling (LVDS) Input,
100Ω Differential On-Chip Termination, up to 650
MHz Frequency
Differential Current Mode Logic (CML) Outputs,
50Ω Single-Ended On-Chip Termination, up to
650 MHz Frequency
Two Groups of Five Outputs Each with
Independent Frequency Division Ratios
Output Frequency Derived with Divide Ratios of 1,
2, 4, 5, 8, 10, 16, 20, 32, 40, and 80
Meets ANSI TIA/EIA-644-A-2001 LVDS Standard
Requirements
Power Consumption: 410 mW Typical
Output Enable Control for Each Output
SDA/SCL Device Management Interface
48-pin VQFN (RGZ) Package
Industrial Temperature Range: –40°C to +85°C
•
With careful observation of the input voltage swing
and common-mode voltage limits, the CDCL1810A
can support a single-ended clock input as outlined in
Pin Configuration and Functions.
All device settings are programmable through the
SDA/SCL, serial two-wire interface. The serial
interface is 1.8V tolerant only.
The device operates in a 1.8V supply environment
and is characterized for operation from –40°C to
+85°C. The CDCL1810A is available in a 48-pin QFN
(RGZ) package.
Device Information(1)
PART NUMBER
CDCL1810A
PACKAGE
VQFN (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
The CDCL1810A supports one differential LVDS
clock input and a total of 10 differential CML outputs.
The CML outputs are compatible with LVDS receivers
if they are ac-coupled.
Clock Distribution for High-Speed SERDES
Distribution of SERDES Reference Clocks for
1G/10G Ethernet, 1X/2X/4X/10X Fibre Channel,
PCI Express, Serial ATA, SONET, CPRI, OBSAI,
and so forth
Up to 1-to-10 Clock Buffering and Fan-out
4 Simplified Schematic
DIVIDER
5 Differential
CML Outputs
Up to 650MHz
DIVIDER
5 Differential
CML Outputs
Up to 650MHz
Differential
LVDS Input
Up to 650MHz
SDA/SCL
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCL1810A
SLLSEL1 – NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Device Comparison Tables...................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
6
8.1
8.2
8.3
8.4
8.5
8.6
8.7
6
6
6
6
7
7
Absolute Maximum Ratings .....................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
DC Electrical Characteristics ....................................
AC Electrical Characteristics....................................
AC Electrical Characteristics for the SDA/SCL
Interface ....................................................................
8.8 Typical Characteristics ..............................................
9
9.1
9.2
9.3
9.4
9.5
9.6
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
10
10
11
13
13
15
10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
11 Power Supply Recommendations ..................... 19
12 Layout................................................................... 19
12.1 Layout Guidelines ................................................. 19
12.2 Layout Example .................................................... 20
13 Device and Documentation Support ................. 22
13.1 Trademarks ........................................................... 22
13.2 Electrostatic Discharge Caution ............................ 22
13.3 Glossary ................................................................ 22
8
9
14 Mechanical, Packaging, and Orderable
Information ........................................................... 22
Detailed Description ............................................ 10
5 Revision History
2
DATE
REVISION
NOTES
November 2014
*
Initial release.
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6 Device Comparison Tables
Table 1. TA Device Comparison
TA
–40°C to +85°C
–40°C to +85°C
PACKAGED DEVICES
FEATURES
CDCL1810ARGZT
48-pin VQFN (RGZ) Package,
small tape and reel
CDCL1810ARGZR
48-pin VQFN (RGZ) Package,
tape and reel
Table 2. Device Feature Comparison
FEATURE
Divider Synchronization after power up and after each
programming access. During Synchronization all outputs
are disabled.
Output Group Phase Adjustment
CDCL1810
CDCL1810A
Yes
No
Yes
No
Device Revision ID
b’011’
b’100’
1:10 Clock Fanout
Yes
Yes
Outputs grouped into two divider banks
Yes
Yes
Individual Output enabled/disable with I2C
Yes
Yes
Continuous and independent operation of outputs which
are not programmed, while configuring and programming
other outputs.
No
Yes
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7 Pin Configuration and Functions
NC
NC
AVDD
YP9
YN9
VDD
YP8
YN8
VDD
ADD1
46
44
43
42
41
40
39
38
37
AVDD
47
45
NC
48
48-Pin
RGZ Package
(Top View)
NC
1
36
ADD0
AVDD
2
35
VDD
CLKP
3
34
YN7
CLKN
4
33
YP7
AVDD
5
32
VDD
YP0
6
31
YN6
CDCL1810A
24
SDA
SCL
25
23
12
VDD
VSS
22
VDD
YN4
26
21
11
YP4
VDD
20
YP5
VDD
27
19
10
YN3
YN1
18
YN5
YP3
28
17
9
VDD
YP1
YN2
VDD
15
29
16
8
YP2
VDD
14
YP6
VDD
30
13
7
NC
YN0
NOTE: Exposed thermal pad must be soldered to VSS.
The CDCL1810A is available in a 48-pin VQFN (RGZ) package with a pin pitch of 0,5mm. The exposed thermal
pad serves both thermal and electrical grounding purposes.
NOTE
The device must be soldered to ground (VSS) using as many ground vias as possible. The
device performance will be severely impacted if the exposed thermal pad is not grounded
appropriately.
4
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Pin Functions
PIN
NAME
NUMBER
TYPE
8, 11, 14, 17, 20, 23,
26, 29, 32, 35, 38, 41
Power
1.8V digital power supply.
2, 5, 44, 47
Power
1.8V analog power supply.
VSS
Exposed thermal pad
and pin 12
Power
Ground reference.
NC
1, 13, 45, 46, 48
I
Not connected; leave open.
3, 4
I
Differential LVDS input. Single-ended 1.8-V input can be dc-coupled to pin 3 with pin 4
either tied to pin 3 (recommended) or left open.
6, 7
9, 10
15, 16
18, 19
21, 22
27, 28
30, 31
33, 34
40, 39
43, 42
O
10 differential CML outputs.
SCL
24
I
SCL serial clock pin. SCL tolerated 1.8V on the input only. Open drain. Always connect
to a pull-up resistor.
SDA
25
I/O
37, 36
I
VDD
AVDD
CLKP, CLKN
YP0, YN0
YP1, YN1
YP2, YN2
YP3, YN3
YP4, YN4
YP5, YN5
YP6, YN6
YP7, YN7
YP8, YN8
YP9, YN9
ADD1, ADD0
DESCRIPTION
SDA bidirectional serial data pin. SDA tolerates 1.8V on the input only.Open drain.
Always connect to a pull-up resistor.
Configurable least significant bits (ADD[1:0]) of the SDA/SCL device address. The fixed
most significant bits (ADD[6:2]) of the 7-bit device address are 11010.
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SLLSEL1 – NOVEMBER 2014
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8 Specifications
8.1 Absolute Maximum Ratings (1)
Over operating free-air temperature range (unless otherwise noted).
VDD, AVDD
Supply voltage (2)
(2)
VLVDS
Voltage range at LVDS input pins
VI
Voltage range at all non-LVDS input pins (2)
TJ
Junction temperature
(1)
(2)
MIN
MAX
UNIT
–0.3
2.5
V
–0.3
VDD+0.6
V
–0.3
VDD+0.6
V
+125
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
condition is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
8.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
UNIT
–65
+150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
500
V
JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
NOM
MAX
VDD
Digital supply voltage
1.7
1.8
1.9
UNIT
V
AVDD
Analog supply voltage
1.7
1.8
1.9
V
TA
Ambient temperature (no airflow, no heatsink)
–40
+85
°C
TJ
Junction temperature
+105
°C
8.4 Thermal Information
CDCL1810A
THERMAL METRIC (1)
RGZ
UNIT
48 PINS
28.3, Airflow = 0 LFM
RθJA
Junction-to-ambient thermal resistance (2).
RθJC(top)
Junction-to-case (top) thermal resistance
20.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.3
(1)
(2)
6
22.4, Airflow = 50 LFM
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
No heatsink; power uniformly distributed; 36 ground vias (6 x 6 array) tied to the thermal exposed pad; 4-layer high-K board.
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8.5 DC Electrical Characteristics
Over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVDD
Total current from digital 1.8V supply
All outputs enabled; VDD = VDD,typ
650MHz LVDS input
IAVDD
Total current from analog 1.8V supply
All outputs enabled; AVDD = VDD,typ
650MHz LVDS input
VIL,CMOS
Low level CMOS input voltage
VDD = 1.8V
–0.2
0.6
VIH,CMOS
High level CMOS input voltage
VDD = 1.8V
VDD –0.6
VDD
V
IIL,CMOS
Low level CMOS input current
VDD = VDD,max, VIL = 0.0V
–120
μA
IIH,CMOS
High level CMOS input current
VDD = VDD,max, VIH = 1.9V
65
μA
VOL,SDA
Low level CMOS output voltage for the
SDA pin
Sink current = 3 mA
0.2VDD
V
IOL,CMOS
Low level CMOS output current
8.6
212
mA
16
mA
0
8
V
mA
AC Electrical Characteristics
Over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
132
Ω
1375
mV
ZD,IN
Differential input impedance for the LVDS
input terminals
VCM,IN
Common-mode voltage, LVDS input
VS,IN
Single-ended LVDS input voltage swing
100
600
VD,IN
Differential LVDS input voltage swing
200
1200
tR,OUT,
tF,OUT
Output signal rise/fall time
VCM,OUT
Common-mode voltage, CML outputs
VS,OUT
Single-ended CML output voltage swing
VD,OUT
Differential CML output voltage swing
FIN
Clock input frequency
650
FOUT
Clock output frequency
650
90
1125
20%–80%
1200
100
ps
VDD – 0.31
VDD – 0.23
VDD – 0.19
ac-coupled
180
230
280
measured in a 50-Ω scope;
The CML output incorporates
50-Ω resistors to VDD
360
460
560
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mVPP
V
mVPP
MHz
7
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AC Electrical Characteristics (continued)
Over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADDITIVE CLOCK OUTPUT JITTER
10 Hz to 1 MHz offset
180
1 MHz to 5 MHz offset
348
12 kHz to 5 MHz offset
388
10 Hz to 1 MHz offset
175
1 MHz to 5 MHz offset
347
12 kHz to 5 MHz offset
388
10 Hz to 1 MHz offset
41
1 MHz to 20 MHz offset
36
12 kHz to 20 MHz offset
42
10 Hz to 1 MHz offset
48
1 MHz to 20 MHz offset
33
12 kHz to 20 MHz offset
39
Input-to-output delay
FIN = 30.72MHz,
FOUT = 30.72MHz
YP[9:0] outputs
0.7
Clock output skew
FIN = 30.72MHz,
FOUT = 30.72MHz
YP[9:0] outputs relative to
YP[0]
FIN = 30.72MHz, FOUT = 30.72MHz
VD,IN = 200mVPP
FIN = 30.72MHz, FOUT = 30.72MHz
VD,IN = 1200mVPP
JOUT
FIN = 650MHz, FOUT = 650MHz
VD,IN = 200mVPP
FIN = 650MHz, FOUT = 650MHz
VD,IN = 1200mVPP
TP
TSOUT
8.7
–64
fs RMS
fs RMS
fs RMS
fs RMS
ns
64
ps
AC Electrical Characteristics for the SDA/SCL Interface (1)
PARAMETER
MIN
TYP
MAX
UNIT
400
kHz
fSCL
SCL frequency
th(START)
START hold time
0.6
μs
tw(SCLL)
SCL low-pulse duration
1.3
μs
tw(SCLH)
SCL high-pulse duration
0.6
μs
tsu(START)
START setup time
0.6
μs
th(SDATA)
SDA hold time
0
μs
tsu(DATA)
SDA setup time
tr(SDATA)
SCL / SDA input rise time
tf(SDATA)
SCL / SDA input fall time
tsu(STOP)
STOP setup time
0.6
μs
tBUS
bus free time
1.3
μs
(1)
8
μs
0.6
0.3
μs
0.3
μs
See Figure 7 for the timing behavior.
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8.8 Typical Characteristics
Typical operating conditions are at VDD = 1.8V and TA = +25°C, VD,IN = 200mVPP (unless otherwise noted).
300
Differential Output Voltage - mV
Differential Output Voltage - mV
300
200
100
0
-100
-200
-300
0
20
40
60
t - Time - ns
80
100
200
100
0
-100
-200
-300
0
Figure 1. Transient Performance:
FIN = 30.72 MHz, FOUT = 30.72 MHz
1
2
3
t - Time - ns
4
Figure 2. Transient Performance:
FIN = 650 MHz, FOUT = 650 MHz
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9
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9 Detailed Description
9.1 Overview
The CDCL1810A is a high performance fanout clock buffer that features two banks of independent integer
dividers ranging from 1 to 80. CDCL1810A is designed in a way that individual outputs can be configured -- or
reconfigured -- without impacting operation of other outputs.
9.2 Functional Block Diagram
DIVIDER
5 Differential
CML Outputs
Up to 650MHz
DIVIDER
5 Differential
CML Outputs
Up to 650MHz
Differential
LVDS Input
Up to 650MHz
SDA/SCL
Figure 3. CDCL1810A Simplified Schematic
VDD
Divider
P1
YP[9:5]
CML
CML
YN[9:5]
CLKP
LVDS
CLKN
Divider
P0
YP[4:0]
CML
CML
YN[4:0]
Divider Setting
SDA/SCL
SDA/SCL
Control
See Note 1
VSS
Note 1: Outputs can be disabled to floating. When outputs are left floating, internal 50 Ω termination to VDD pulls both
YN and YP to VDD.
Figure 4. Functional Block Diagram
10
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9.3 Feature Description
9.3.1 Output Enable/Disable
The CDCL1810A does not have an output synchronization feature like the CDCL1810. The CDCL1810A ensures
that all outputs stay enabled during any device communication like output enable/disable. Divider changes will
apply immediately at the outputs. This may cause a glitch and may result in different phase offsets between both
dividers.
Figure 5. Device Status Flow Chart
9.3.2 SDA/SCL Interface
This section describes the SDA/SCL interface of the CDCL1810A device. The CDCL1810A operates as a slave
device of the industry standard 2-pin SDA/SCL bus. It operates in the fast-mode at a bit-rate of up to 400 kbit/s
and supports 7-bit addressing compatible with the popular 2-pin serial interface standard.
9.3.2.1 SDA/SCL Bus Slave Device Address
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
ADD1
ADD0
0/1
The device address is made up of the fixed internal address, 11010 (A6:A2), and configurable external pins
ADD1 (A1) and ADD0 (A0). Four different devices with addresses 1101000, 1101001, 1101010 and 1101011,
can be addressed via the same SDA/SCL bus interface. The least significant bit of the address byte designates a
write or read operation.
R/W Bit:
0 = write to CDCL1810A device
1 = read from CDCL1810A device
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Feature Description (continued)
9.3.2.2 SDA/SCL Connections Recommendations
The serial interface inputs don’t have glitch suppression circuit. So, any noises or glitches at serial input lines
may cause programming error. The serial interface lines should be routed in such a way that the lines would
have minimum noise impact from the surroundings.
Figure 6 is recommended to improve the interconnections.
RP
SCL
CF
Master
CDCL1810A
(Slave)
RP
SDA
Figure 6. Serial Interface Connections
Lower RP resistor value (around 1 kΩ) should be chosen so that signals will have faster rise time. A capacitor
can be connected to SCL line to ground which will act as a filter.
An I2C level translator will help to overcome the noises issue.
12
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9.4 Device Functional Modes
The device is designed to operate from an input voltage supply of 1.8 V. In the default power on reset, all device
outputs are enabled and the dividers P0 and P1 are set to 1.
9.5 Programming
9.5.1 SDA/SCL Interface
This section describes the SDA/SCL interface of the DCDL1810A device. The CDCL1810A operates as a slave
device of the industry standard 2-pin SDA/SCL bus. It operates in the fast-mode at a bit-rate of up to 400 kb/s
and supports 7-bit addressing compatible with the popular 2-pin serial interface standard. The device address is
made up of the fixed internal address, 11010 (A6:A2), and configurable external pins ADD1 (A1) and ADD0 (A0).
Four different devices with addresses 1101000, 1101001, 1101010, and 1101011, can be addressed via the
same SDA/SCL bus interface. The least significant bit of the address byte designates a write or read operation.
R/W bit:
0 = write to CDCL1810 device.
1 = read from CDCL1810 device.
9.5.2 Command Code Definition
Table 3. Command Code Definition
BIT
C7
(C6:C0)
DESCRIPTION
1 = Byte Write / Read or Word Write / Read operation
Byte Offset for Byte Write / Read and Word Write / Read operation.
Table 4. SDA/SCL Bus Slave Device Address
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
ADD1
ADD0
0/1
Table 5. Command Code for Byte Write / Read Operation
HEX CODE
C7
C6
C5
C4
C3
C2
C1
C0
byte 0
80h
1
0
0
0
0
0
0
0
byte 1
81h
1
0
0
0
0
0
0
1
byte 2
82h
1
0
0
0
0
0
1
0
byte 3
83h
1
0
0
0
0
0
1
1
byte 4
84h
1
0
0
0
0
1
0
0
byte 5
85h
1
0
0
0
0
1
0
1
byte 6
86h
1
0
0
0
0
1
1
0
Table 6. Command Code for Word Write / Read Operation
HEX CODE
C7
C6
C5
C4
C3
C2
C1
C0
word 0: byte 0 and byte 1
80h
1
0
0
0
0
0
0
0
word 1: byte 1 and byte 2
81h
1
0
0
0
0
0
0
1
word 2: byte 2 and byte 3
82h
1
0
0
0
0
0
1
0
word 3: byte 3 and byte 4
83h
1
0
0
0
0
0
1
1
word 4: byte 4 and byte 5
84h
1
0
0
0
0
1
0
0
word 5: byte 5 and byte 6
85h
1
0
0
0
0
1
0
1
word 6: byte 6 and byte 7
86h
1
0
0
0
0
1
1
0
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9.5.3 SDA/SCL Timing Characteristics
S
P
tw(SCLL)
Bit 6
Bit 7 (MSB)
tw(SCLH)
A
Bit 0 (LSB)
tr(SM)
P
tf(SM)
VIH(SM)
SCL
VIL(SM)
tSU(START)
th(SDATA)
tSU(SDATA)
th(START)
t(BUS)
tSU(STOP)
tf(SM)
tr(SM)
VIH(SM)
SDA
VIL(SM)
Figure 7. Timing Diagram for the SDA/SCL Serial Control Interface
9.5.4 SDA/SCL Programming Sequence
1
7
S
Slave Address
1
1
Wr A
S
Start condition
Sr
Repeated start condition
Rd
Read (bit value = 1)
Wr
Write (bit value = 0)
A
Acknowledge (bit value = 0)
N
Not acknowledge (bit value = 1)
P
Stop condition
8
Data Byte
1
1
A
P
Master to Slave transmission
Slave to Master transmission
Figure 8. Legend for Programming Sequence
Table 7. Byte Write Programming Sequence
1
7
1
1
8
1
8
1
1
S
Slave Address
Wr
A
Command Code
A
Data Byte
A
P
Table 8. Byte Read Programming Sequence
1
S
7
1
Wr
Slave Address
1
8
1
1
7
1
1
8
1
1
A
Command
Code
A
S
Slave Address
Rd
A
Data Byte
N
P
Table 9. Word Write Programming Sequence:
1
7
1
1
8
1
8
1
8
1
1
S
Slave Address
Wr
A
Command Code
A
Data Byte Low
A
Data Byte High
A
P
Table 10. Word Read Programming Sequence:
14
1
7
S
Slave
Address
1
Wr
1
8
A
Command
Code
1
A
1
7
1
1
8
1
8
1
1
S
Slave
Address
Rd
A
Data Byte
A
Data Byte
N
P
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9.6 Register Maps
9.6.1 SDA/SCL Bus Configuration Command Bitmap
9.6.1.1 Byte 0:
BIT
BIT NAME
DESCRIPTION/FUNCTION
TYPE
POWER UP
CONDITION
7
MANF[7]
Manufacturer reserved
R
6
MANF[6]
Manufacturer reserved
R
5
REV[2]
Device revision
R
1
4
REV[1]
Device revision
R
0
3
REV[0]
Device revision
R
0
2
MANF[2]
Manufacturer reserved
R
1
MANF[1]
Manufacturer reserved
R
0
MANF[0]
Manufacturer reserved
R
REFERENCE
TO
9.6.1.2 Byte 1:
BIT
BIT NAME
DESCRIPTION/FUNCTION
TYPE
POWER UP
CONDITION
7
RES
Reserved
R/W
0
6
RES
Reserved
R/W
0
5
RES
Reserved
R/W
1
4
RES
Reserved
R/W
0
3
RES
Reserved
R/W
0
2
RES
Reserved
R/W
0
1
RES
Reserved
R/W
0
0
RES
Reserved
R/W
0
TYPE
POWER UP
CONDITION
REFERENCE
TO
9.6.1.3 Byte 2:
BIT
BIT NAME
DESCRIPTION/FUNCTION
REFERENCE
TO
7
RES
Reserved
R/W
0
6
RES
Reserved
R/W
0
5
ENP1
Post-divider P1 enable; if 0 output YP[9:5] and YN[9:5] are
disabled
R/W
1
4
RES
Reserved
R/W
1
3
SELP1[3]
Divide ratio select for post-divider P1
R/W
0
Table 11
2
SELP1[2]
Divide ratio select for post-divider P1
R/W
0
Table 11
1
SELP1[1]
Divide ratio select for post-divider P1
R/W
0
Table 11
0
SELP1[0]
Divide ratio select for post-divider P1
R/W
0
Table 11
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9.6.1.4 Byte 3:
BIT
BIT NAME
DESCRIPTION/FUNCTION
TYPE
POWER UP
CONDITION
7
RES
Reserved
R/W
0
6
RES
Reserved
R/W
0
5
RES
Reserved
R/W
0
4
RES
Reserved
R/W
0
3
RES
Reserved
R/W
0
2
RES
Reserved
R/W
0
1
RES
Reserved
R/W
0
0
RES
Reserved
R/W
0
TYPE
POWER UP
CONDITION
REFERENCE
TO
9.6.1.5 Byte 4:
BIT
BIT NAME
DESCRIPTION/FUNCTION
REFERENCE
TO
7
RES
Reserved
R/W
0
6
RES
Reserved
R/W
0
5
ENP0
Post-divider P0 enable. If 0, output YP[4:0] and YN[4:0] are
disabled
R/W
1
4
RES
Reserved
R/W
1
3
SELP0[3]
Divide ratio select for post-divider P0
R/W
0
Table 11
2
SELP0[2]
Divide ratio select for post-divider P0
R/W
0
Table 11
1
SELP0[1]
Divide ratio select for post-divider P0
R/W
0
Table 11
0
SELP0[0]
Divide ratio select for post-divider P0
R/W
0
Table 11
TYPE
POWER UP
CONDITION
REFERENCE
TO
R/W
1
R
1
9.6.1.6 Byte 5:
BIT
16
BIT NAME
DESCRIPTION/FUNCTION
7
EN
Chip enable; if 0 chip is in Iddq mode
6
RES
Reserved
5
ENDRV9
YP[9], YN[9] enable; if 0 output is disabled
R/W
1
4
ENDRV8
YP[8], YN[8] enable; if 0 output is disabled
R/W
1
3
ENDRV7
YP[7], YN[7] enable; if 0 output is disabled
R/W
1
2
ENDRV6
YP[6], YN[6] enable; if 0 output is disabled
R/W
1
1
ENDRV5
YP[5], YN[5] enable; if 0 output is disabled
R/W
1
0
ENDRV4
YP[4], YN[4] enable; if 0 output is disabled
R/W
1
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9.6.1.7 Byte 6:
BIT
BIT NAME
DESCRIPTION/FUNCTION
TYPE
POWER UP
CONDITION
7
ENDRV3
YP[3], YN[3] enable; if 0 output is disabled
R/W
1
6
ENDRV2
YP[2], YN[2] enable; if 0 output is disabled
R/W
1
5
ENDRV1
YP[1], YN[1] enable; if 0 output is disabled
R/W
1
4
ENDRV0
YP[0], YN[0] enable; if 0 output is disabled
R/W
1
3
RES
Reserved
R/W
0
2
RES
Reserved
R/W
0
1
RES
Reserved
R/W
0
0
RES
Reserved
R/W
0
REFERENCE
TO
Table 11. Divide Ratio Settings for Post-Divider P0 or P1
DIVIDE
RATIO
SELP1[3] or
SELP0[3]
SELP1[2] or
SELP0[2]
SELP1[1] or
SELP0[1]
SELP1[0] or
SELP0[0]
NOTES
1
0
0
0
0
Default
2
0
0
0
1
4
0
0
1
0
5
0
0
1
1
8
0
1
0
0
10
0
1
0
1
16
0
1
1
0
20
0
1
1
1
32
1
0
0
0
40
1
0
0
1
80
1
0
1
0
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The CDCL1810 is a high-performance buffer that can generate 10 copies of CML clock outputs from a LVDS
input. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the
input frequency.
10.1.1 Clock Distribution for Multiple TI Keystone DSPs
TI Keystone DSP
TI Keystone DSP
SYSCLK
ARMCLK
Clock Generator
E.g.: CDCM6208
RP1CLK
SYSCLK
ARMCLK
RP1CLK
100MHz
100MHz
100MHz
PCIeCLK
USBClk
DDRACLK
DDRBCLK
CDCL1810A
100MHz
PCIeCLK
USBClk
DDRACLK
100MHz
DDRBCLK
I2C
Figure 9. CDCL1810A Application Drawing
10.1.1.1 Design Requirements
A typical application example is multi DSP chip environment. The CDCL1810A is used to buffer the common
clocks to the DSP.
10.1.1.2 Detailed Design Procedure
The CDCL1810A does not support output group phase alignment if a divider gets reprogrammed. Both clock
groups might be out of phase by multiple input clock cycles. This is especially of concern if both dividers are
greater than 1 (see Figure 10).
Continuous operation of output clocks is ensured, while enabling/disabling of outputs in the CDCL1810A. (see
Figure 11).
18
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Application Information (continued)
10.1.1.3 Application Curves
Y[4:0], div by 2
Y[9:5], div by 6
Figure 10. Output Group Divider Change
Y0
Y1
Enable
Figure 11. Individual Output Disable/Enable
11 Power Supply Recommendations
The device is designed to operate from an input voltage supply of 1.8 V for analog supply (AVDD) and core
supply (VDD). Both AVDD and VDD can be supplied by a single source.
12 Layout
12.1 Layout Guidelines
•
•
•
•
Keep the connections between the bypass capacitors and the power supply on the device as short as
possible.
Ground the other side of the capacitor using a low impedance connection to the ground plane.
If the capacitors are mounted on the back side, 0402 components can be employed; however, soldering to
the Thermal Dissipation Pad can be difficult.
For component side mounting, use 0201 body size capacitors to facilitate signal routing.
NOTE
The device must be soldered to ground (VSS) using as many ground vias as possible. The
device performance will be severely impacted if the exposed thermal pad is not grounded
appropriately.
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12.2 Layout Example
Figure 12. Layout Example: Signal Layer (TOP)
20
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Layout Example (continued)
Figure 13. Layout Example: Bottom Layer with Decoupling Capacitors
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13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCL1810ARGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CDCL
1810A
CDCL1810ARGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CDCL
1810A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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