DLP4710FQL

DLP4710 DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 DLP4710 0.47 1080p DMD 1 Features 3 Description • The DLP4710 digital micromirror device (DMD) is a digitally controlled micro-opto-electromechanical system (MOEMS) spatial light modulator (SLM). When coupled to an appropriate optical system, the DLP4710LC DMD displays a very crisp and high quality image or video. The device is a component of the chipset comprising the DLP4710 DMD, DLPC3479 controller and DLPA3000/DLPA3005 PMIC/LED drivers. The compact physical size of the DLP4710LC coupled with the controller and the PMIC/LED driver provides a complete system solution that enables small form factor, low power, and high resolution HD displays. • • • 0.47-Inch (11.93-mm) diagonal micromirror array – 1920 × 1080 array of aluminum micrometersized mirrors, in an orthogonal layout – Micromirror pitch: 5.4 μm – Micromirror tilt (relative to flat surface): ±17° – Bottom illumination for optimal efficiency and optical engine size – Polarization independent aluminum micromirror surface 32-Bit SubLVDS input data bus Dedicated DLP3439 display controller Dedicated DLPA3000 or DLPA3005 PMIC/LED drivers for reliable operation Visit the getting started with TI DLP®Pico™ display technology page to learn how to get started with the DLP4710. 2 Applications • • • • • • Smart full HD projector Mobile accessory full HD projector Screenless display Interactive display Low latency gaming display Head mounted display The DLP4710 ecosystem includes established resources to help the user accelerate the design cycle, which include production ready optical modules, optical modules manufactures, and design houses. Device Information PACKAGE(1) PART NUMBER DLP4710 (1) FQL (100) BODY SIZE (NOM) 24.50-mm × 11-mm For all available packages, see the orderable addendum at the end of the data sheet. DLP Pico Analog Device VOFFSET VBIAS VRESET DLP Pico Processor DLP Pico Processor 600 MHz SubLVDS DDR Interface 120 MHz SDR Interface D_BP(0:7) D_BP(0:7) D_AP(0:7) D_AN(0:7) DLP DMD DCLK_AP DCLK_AN DCLK_BP DCLK_BN Digital Micromirror Device LS_WDATA LS_CLK LS_RDATA LS_RDATA_B 600 MHz SubLVDS DDR Interface 120 MHz SDR Interface DMD_DEN_ARSTZ Slave Master VDDI VDD VSS (System signal routing omitted for clarity) 0.47 1080p Chipset An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 8 6.1 Absolute Maximum Ratings ....................................... 8 6.2 Storage Conditions..................................................... 8 6.3 ESD Ratings............................................................... 9 6.4 Recommended Operating Conditions.........................9 6.5 Thermal Information.................................................. 11 6.6 Electrical Characteristics...........................................11 6.7 Timing Requirements................................................ 12 6.8 Switching Characteristics .........................................17 6.9 System Mounting Interface Loads............................ 17 6.10 Physical Characteristics of the Micromirror Array... 18 6.11 Micromirror Array Optical Characteristics............... 20 6.12 Window Characteristics.......................................... 21 6.13 Chipset Component Usage Specification............... 21 6.14 Software Requirements.......................................... 22 7 Detailed Description......................................................23 7.1 Overview................................................................... 23 7.2 Functional Block Diagram......................................... 24 7.3 Feature Description...................................................25 7.4 Device Functional Modes..........................................25 7.5 Optical Interface and System Image Quality Considerations............................................................ 25 7.6 Micromirror Array Temperature Calculation.............. 26 7.7 Micromirror Landed-On/Landed-Off Duty Cycle ...... 27 8 Application and Implementation.................................. 31 8.1 Application Information............................................. 31 8.2 Typical Application.................................................... 31 9 Power Supply Recommendations................................33 9.1 DMD Power Supply Power-Up Procedure................ 33 9.2 DMD Power Supply Power-Down Procedure........... 33 9.3 Power Supply Sequencing Requirements................ 34 10 Layout...........................................................................36 10.1 Layout Guidelines................................................... 36 10.2 Layout Example...................................................... 36 11 Device and Documentation Support..........................37 11.1 Device Support........................................................37 11.2 Related Links.......................................................... 37 11.3 Receiving Notification of Documentation Updates.. 38 11.4 Support Resources................................................. 38 11.5 Trademarks............................................................. 38 11.6 Electrostatic Discharge Caution.............................. 38 11.7 Glossary.................................................................. 38 12 Mechanical, Packaging, and Orderable Information.................................................................... 39 4 Revision History Changes from Revision A (November 2021) to Revision B (May 2022) Page • Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 8 • Updated Micromirror Array Optical Characteristics ......................................................................................... 20 • Added Third-Party Products Disclaimer ...........................................................................................................37 Changes from Revision * (November 2018) to Revision A (November 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated |TDELTA| MAX from 30°C to 15°C..........................................................................................................9 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 5 Pin Configuration and Functions L J K G H E F C D A B 1 2 3 4 5 6 25 26 27 28 29 30 31 Figure 5-1. FQL Package. 100-Pin LGA. Bottom View. Table 5-1. Connector Pins PIN(1) NAME NO. TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH(2) (mm) DATA INPUTS D_AN(0) G3 I SubLVDS Double Data, Negative 5.01 D_AN(1) F4 I SubLVDS Double Data, Negative 2.03 D_AN(2) E3 I SubLVDS Double Data, Negative 2.41 D_AN(3) E6 I SubLVDS Double Data, Negative 4.71 D_AN(4) J5 I SubLVDS Double Data, Negative 3.23 D_AN(5) L5 I SubLVDS Double Data, Negative 3.87 D_AN(6) G5 I SubLVDS Double Data, Negative 6.32 D_AN(7) L3 I SubLVDS Double Data, Negative 1.84 D_AP(0) H3 I SubLVDS Double Data, Positive 5.01 D_AP(1) G4 I SubLVDS Double Data, Positive 2.03 D_AP(2) E4 I SubLVDS Double Data, Positive 2.41 D_AP(3) E5 I SubLVDS Double Data, Positive 4.71 D_AP(4) J6 I SubLVDS Double Data, Positive 3.23 D_AP(5) L6 I SubLVDS Double Data, Positive 3.87 D_AP(6) G6 I SubLVDS Double Data, Positive 6.32 D_AP(7) L4 I SubLVDS Double Data, Positive 1.84 D_BN(0) G27 I SubLVDS Double Data, Negative 2.51 D_BN(1) E26 I SubLVDS Double Data, Negative 4.43 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 3 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 Table 5-1. Connector Pins (continued) PIN(1) NAME NO. TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH(2) (mm) D_BN(2) D28 I SubLVDS Double Data, Negative 2.76 D_BN(3) D26 I SubLVDS Double Data, Negative 5.47 D_BN(4) L25 I SubLVDS Double Data, Negative 4.85 D_BN(5) K25 I SubLVDS Double Data, Negative 4.10 D_BN(6) L28 I SubLVDS Double Data, Negative 2.53 D_BN(7) K27 I SubLVDS Double Data, Negative 2.76 D_BP(0) F27 I SubLVDS Double Data, Positive 2.51 D_BP(1) E27 I SubLVDS Double Data, Positive 4.43 D_BP(2) D27 I SubLVDS Double Data, Positive 2.76 D_BP(3) D25 I SubLVDS Double Data, Positive 5.47 D_BP(4) L26 I SubLVDS Double Data, Positive 4.85 D_BP(5) J25 I SubLVDS Double Data, Positive 4.10 D_BP(6) K28 I SubLVDS Double Data, Positive 2.53 D_BP(7) J27 I SubLVDS Double Data, Positive 2.76 DCLK_AN J3 I SubLVDS Double Clock, Negative 3.77 DCLK_AP K3 I SubLVDS Double Clock, Positive 3.77 DCLK_BN H26 I SubLVDS Double Clock, Negative 2.98 DCLK_BP H27 I SubLVDS Double Clock, Positive 2.98 LS_WDATA D3 I LPSDR (1) Single Write data for low speed interface. 1.20 LS_CLK C3 I LPSDR Single Clock for low-speed interface 1.20 Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. 4.19 CONTROL INPUTS DMD_DEN_ARSTZ B6 I LPSDR LS_RDATA_A C6 O LPSDR Single Read data for low-speed interface 3.93 LS_RDATA_B C4 O LPSDR Single Read data for low-speed interface 2.57 VBIAS B27 Power 24.51 VBIAS B4 Power Supply voltage for positive bias level at micromirrors VOFFSET B2 Power 49.56 VOFFSET C29 Power Supply voltage for HVCMOS core logic. Supply voltage for stepped high level at micromirror address electrodes. Supply voltage for offset level at micromirrors. VRESET B28 Power B3 Power Supply voltage for negative reset level at micromirrors. 24.82 VRESET POWER 4 (3) Submit Document Feedback 24.51 49.56 24.82 Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 Table 5-1. Connector Pins (continued) PIN(1) NAME NO. TYPE VDD C2 Power VDD D2 Power VDD D29 Power VDD E2 Power VDD E29 Power VDD H2 Power VDD H28 Power VDD H29 Power VDD J2 Power VDD J28 Power VDD J29 Power VDD K2 Power VDD K29 Power VDD L2 Power VDD L29 Power VDDI E28 Power VDDI F2 Power VDDI F28 Power VDDI F29 Power VDDI F3 Power VDDI G2 Power VDDI G28 Power VDDI G29 Power SIGNAL DATA RATE PACKAGE NET LENGTH(2) (mm) DESCRIPTION Supply voltage for LVCMOS core logic. Supply voltage for LPSDR inputs. Supply voltage for normal high level at micromirror address electrodes. Supply voltage for SubLVDS receivers. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 5 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 Table 5-1. Connector Pins (continued) PIN(1) NAME TYPE VSS B25 Ground VSS B26 Ground VSS B29 Ground VSS B5 Ground VSS C25 Ground VSS C26 Ground VSS C27 Ground VSS C28 Ground VSS C5 Ground VSS D4 Ground VSS D5 Ground VSS D6 Ground VSS E25 Ground VSS F25 Ground VSS F26 Ground VSS F5 Ground VSS F6 Ground VSS G25 Ground VSS G26 Ground VSS H25 Ground VSS H4 Ground VSS H5 Ground VSS H6 Ground VSS J26 Ground VSS J4 Ground VSS K26 Ground VSS K4 Ground VSS K5 Ground VSS K6 Ground VSS L27 Ground (1) (2) (3) 6 NO. SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH(2) (mm) Common return. Ground for all power. Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B. Net trace lengths inside the package: Relative dielectric constant for the FQL ceramic package is 9.8. Propagation speed = 11.8 / sqrt (9.8) = 3.769 inches/ns. Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm. The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 Table 5-2. Test Pads NUMBER SYSTEM BOARD A1 Do not connect A5 Do not connect A6 Do not connect A25 Do not connect A26 Do not connect A27 Do not connect A28 Do not connect A29 Do not connect A30 Do not connect A31 Do not connect B30 Do not connect B31 Do not connect C30 Do not connect C31 Do not connect D1 Do not connect E1 Do not connect Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 7 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 6 Specifications 6.1 Absolute Maximum Ratings see (1) Supply voltage Input voltage Input pins Clock frequency MIN MAX UNIT VDD Supply voltage for LVCMOS core logic(2) Supply voltage for LPSDR low speed interface –0.5 2.3 V VDDI Supply voltage for SubLVDS receivers(2) –0.5 2.3 V VOFFSET Supply voltage for HVCMOS and micromirror –0.5 11 V VBIAS Supply voltage for micromirror electrode(2) –0.5 19 V electrode(2) –15 VRESET Supply voltage for micromirror 0.5 V | VDDI–VDD | Supply voltage delta (absolute value)(4) 0.3 V | VBIAS– VOFFSET | Supply voltage delta (absolute value)(5) 11 V | VBIAS– VRESET | Supply voltage delta (absolute value)(6) 34 V Input voltage for other inputs LPSDR(2) –0.5 VDD + 0.5 V Input voltage for other inputs SubLVDS(2) (7) –0.5 VDDI + 0.5 V | VID | SubLVDS input differential voltage (absolute value)(7) 810 mV IID SubLVDS input differential current 10 mA ƒclock Clock frequency for low speed interface LS_CLK 130 MHz ƒclock Clock frequency for high speed interface DCLK 620 MHz –20 90 °C –40 90 °C TARRAY and TWINDOW Environmental (1) (2) (3) (4) (5) (6) (7) (8) (9) electrode(2) (3) Temperature – operational (8) Temperature – non-operational(8) TDP Dew Point Temperature - operating and non-operating (noncondensing) 81 °C |TDELTA| Absolute Temperature delta between any point on the window edge and the ceramic test point TP1(9) 30 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required. VOFFSET supply transients must fall within specified voltages. Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw. Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw. Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw. This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors. The highest temperature of the active array (as calculated by the Section 7.6) or of any point along the Window Edge as defined in Figure 7-1. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be used. Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used. 6.2 Storage Conditions applicable for the DMD as a component or non-operational in a system 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 TDMD DMD storage temperature MAX UNIT –40 85 °C 24 °C 36 °C 6 Months (non-condensing)(1) TDP-AVG Average dew point temperature, TDP-ELR Elevated dew point temperature range, (non-condensing)(2) CTELR Cumulative time in elevated dew point temperature range (1) (2) MIN 28 The average over time (including storage and operating) that the device is not in the elevated dew point temperature range. Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR. 6.3 ESD Ratings V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) VALUE UNIT ±2000 V JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. 6.4 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted)(1) (2) (3) SUPPLY VOLTAGE MIN NOM MAX UNIT RANGE(4) VDD Supply voltage for LVCMOS core logic Supply voltage for LPSDR low-speed interface 1.7 1.8 1.95 V VDDI Supply voltage for SubLVDS receivers 1.7 1.8 1.95 V VOFFSET Supply voltage for HVCMOS and micromirror VBIAS Supply voltage for mirror electrode VRESET Supply voltage for micromirror electrode |VDDI–VDD| Supply voltage delta (absolute value)(6) electrode(5) 9.5 10 10.5 V 17.5 18 18.5 V –14.5 –14 –13.5 V 0.3 V |VBIAS–VOFFSET| Supply voltage delta (absolute value)(7) 10.5 V |VBIAS–VRESET| Supply voltage delta (absolute value)(8) 33 V 120 MHz 300 540 MHz 44% 56% CLOCK FREQUENCY ƒclock Clock frequency for low speed interface LS_CLK(9) ƒclock DCLK(10) Clock frequency for high speed interface Duty cycle distortion DCLK 108 SUBLVDS INTERFACE(10) | VID | SubLVDS input differential voltage (absolute value) Figure 6-8, Figure 6-9 150 250 350 mV VCM Common mode voltage Figure 6-8, Figure 6-9 700 900 1100 mV VSUBLVDS SubLVDS voltage Figure 6-8, Figure 6-9 575 1225 mV ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω ZIN Internal differential termination resistance Figure 6-10 80 100 120 Ω 100-Ω differential PCB trace 6.35 152.4 0 40 to 70(13) Array Temperature - short-term operational, 25 hr max(12) (15) –20 -10 Array Temperature - short-term operational, 500 hr max(12) (15) –10 0 Array Temperature – short-term operational, 500 hr max(12) (15) 70 75 mm ENVIRONMENTAL Array Temperature – long-term operational(11) (12) (13) (14) TARRAY °C |TDELTA| Absolute Temperature difference between any point on the window edge and the ceramic test point TP1 (16) 15 °C TWINDOW Window Temperature – operational(11) (17) 90 °C 24 °C TDP-AVG Average dew point temperature (non-condensing)(18) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 9 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 MIN TDP-ELR Elevated dew point temperature range (non-condensing)(19) CTELR Cumulative time in elevated dew point temperature range ILLUV Illumination wavelengths < 420 nm (11) ILLVIS Illumination wavelengths between 420 nm and 700 nm ILLIR Illumination wavelengths > 700 nm ILLθ (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) MAX UNIT 36 °C 6 Months 0.68 mW/cm2 Thermally limited 10 mW/cm2 angle(20) 55 degrees The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required. Section 6.4 are applicable after the DMD is installed in the final product. The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Section 6.4. No level of performance is implied when operating the device above or below the Section 6.4 limits. All voltage values are with respect to the ground pins (VSS). VOFFSET supply transients must fall within specified max voltages. To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit. LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands. Refer to the SubLVDS timing requirements in Section 6.7. Simultaneous exposure of the DMD to the maximum Section 6.4 for temperature and UV illumination will reduce device lifetime. The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 7-1 and the Package Thermal Resistance using Section 7.6. Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Section 7.7 for a definition of micromirror landed duty cycle. Long-term is defined as the usable life of the device Short-term is the total cumulative time over the useful life of the device. Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used. Window temperature is the highest temperature on the window edge shown in Figure 7-1. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be used. The average over time (including storage and operating) that the device is not in the elevated dew point temperature range. Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR. The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime. Max Recommended Array Temperature – Operational (°C) (20) Illumination marginal ray NOM 28 80 70 60 50 40 30 0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50 100/0 95/5 90/10 85/15 80/20 75/25 70/30 65/35 Micromirror Landed Duty Cycle 60/40 55/45 D001 Figure 6-1. Max Recommended Array Temperature – Derating Curve 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 6.5 Thermal Information DLP4710LC THERMAL METRIC(1) FQL (LGA) UNIT 100 PINS Thermal resistance (1) Active area to test point 1 (TP1)(1) 1.1 °C/W The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of maintaining the package within the temperature range specified in the Section 6.4. The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device. 6.6 Electrical Characteristics Over operating free-air temperature range (unless otherwise noted)(1) PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT CURRENT IDD Supply current: VDD(3) (4) IDDI Supply current: VDDI(3) (4) IOFFSET Supply current: VOFFSET(5) (6) IBIAS Supply current: VBIAS(5) (6) IRESET Supply current: VRESET(6) VDD = 1.95 V 260 VDD = 1.8 V 180 VDDI = 1.95 V 62 VDDI = = 1.8 V 40 VOFFSET = 10.5 V 7.4 VOFFSET = 10 V 6.3 VBIAS = 18.5 V 1.1 VBIAS = 18 V 0.9 VRESET = –14.5 V 5.4 VRESET = –14 V 4.4 mA mA mA mA mA POWER(7) PDD (4) Supply power dissipation: VDD(3) VDD = 1.95 V VDD = 1.8 V 324 507 PDDI Supply power dissipation: VDDI(3) VDDI = 1.95 V (4) VDD = 1.8 V 72 POFFSET Supply power dissipation: VOFFSET(5) (6) VOFFSET = 10.5 V PBIAS Supply power dissipation: VBIAS(5) (6) VBIAS = 18.5 V PRESET Supply power dissipation: VRESET(6) VRESET = –14.5 V PTOTAL Supply power dissipation: Total 120.9 77.7 VOFFSET = 10 V 63 20.35 VBIAS = 18 V 16.2 78.3 VRESET = –14 V 61.6 536.8 804.25 mW mW mW mW mW mW LPSDR INPUT(8) VIH(DC) DC input high voltage(9) VIL(DC) DC input low voltage(9) voltage(9) VIH(AC) AC input high VIL(AC) AC input low voltage(9) ∆VT Hysteresis ( VT+ – VT– ) Figure 6-10 IIL Low–level input current VDD = 1.95 V; VI = 0 V IIH High–level input current VDD = 1.95 V; VI = 1.95 V LPSDR VOH 0.7 × VDD VDD + 0.3 V –0.3 0.3 × VDD V 0.8 × VDD VDD + 0.3 V –0.3 0.2 × VDD V 0.1 × VDD 0.4 × VDD –100 V nA 100 nA OUTPUT(10) DC output high voltage IOH = –2 mA 0.8 × VDD V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 11 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 PARAMETER VOL TEST CONDITIONS(2) MIN TYP MAX UNIT DC output low voltage IOL = 2 mA 0.2 × VDD V Input capacitance LPSDR ƒ = 1 MHz 10 pF CAPACITANCE CIN Input capacitance SubLVDS ƒ = 1 MHz 20 pF COUT Output capacitance ƒ = 1 MHz 10 pF CRESET Reset group capacitance ƒ = 1 MHz; (1080 × 240) micromirrors 450 pF 400 (1) (2) (3) (4) (5) (6) (7) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted. All voltage values are with respect to the ground pins (VSS). To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit. Supply power dissipation based on non–compressed commands and data. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Supply power dissipation based on 3 global resets in 200 µs. The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required. (8) LPSDR specifications are for pins LS_CLK and LS_WDATA. (9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B. (10) LPSDR specification is for pin LS_RDATA. 6.7 Timing Requirements Device electrical characteristics are over Section 6.4 unless otherwise noted. MIN NOM MAX UNIT 1 3 V/ns (70% to 20%) × VDD, Figure 6-3 1 3 V/ns (20% to 80%) × VDD, Figure 6-3 0.25 (80% to 20%) × VDD, Figure 6-3 0.25 LPSDR Rise slew rate(1) tr rate(1) tƒ Fall slew tr Rise slew rate(2) rate(2) (30% to 80%) × VDD, Figure 6-3 V/ns tƒ Fall slew tc Cycle time LS_CLK, Figure 6-2 7.7 V/ns tW(H) Pulse duration LS_CLK high 50% to 50% reference points, Figure 6-2 3.1 ns tW(L) Pulse duration LS_CLK low 50% to 50% reference points, Figure 6-2 3.1 ns tsu Setup time LS_WDATA valid before LS_CLK ↑, Figure 6-2 1.5 ns th Hold time LS_WDATA valid after LS_CLK ↑, Figure 6-2 1.5 ns tWINDOW Window time(1) (3) Setup time + Hold time, Figure 6-2 3.0 ns tDERATING Window time derating(1) (3) For each 0.25 V/ns reduction in slew rate below 1 V/ns, Figure 6-5 tr Rise slew rate 20% to 80% reference points, Figure 6-4 0.7 1 V/ns tƒ Fall slew rate 80% to 20% reference points, Figure 6-4 0.7 1 V/ns tc Cycle time DCLK, Figure 6-6 1.79 1.85 tW(H) Pulse duration DCLK high 50% to 50% reference points, Figure 6-6 0.79 ns tW(L) Pulse duration DCLK low 50% to 50% reference points, Figure 6-6 0.79 ns tsu Setup time D(0:7) valid before DCLK ↑ or DCLK ↓, Figure 6-6 8.3 0.35 ns ns SubLVDS 12 Submit Document Feedback ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 MIN th Hold time D(0:7) valid after DCLK ↑ or DCLK ↓, Figure 6-6 tWINDOW Window time Setup time + Hold time, Figure 6-6, Figure 6-7 tLVDS- Power-up receiver(4) ENABLE+REFGEN (1) (2) (3) (4) NOM MAX 3.0 UNIT ns 2000 ns Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3. Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-3 . Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns. Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding. tc tw(H) LS_CLK 50% tw(L) 50% 50% th tsu LS_ WDATA 50% 50% twindow Low-speed interface is LPSDR and adheres to the Section 6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B. Figure 6-2. LPSDR Switching Parameters LS_CLK, LS_WDATA DMD_DEN_ARSTZ 1.0 * VDD 1.0 * VDD 0.8 * VDD 0.7 * VDD VIH(AC) VIH(DC) 0.3 * VDD 0.2 * VDD VIL(DC) VIL(AC) 0.8 * VDD 0.2 * VDD 0.0 * VDD 0.0 * VDD tr tf tr tf Figure 6-3. LPSDR Input Rise and Fall Slew Rate Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 13 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 VDCLK_P , VDCLK_N VD_P(0:7) , VD_N(0:7) 1.0 * VID 0.8 * VID VCM 0.2 * VID 0.0 * VID tr tf Figure 6-4. SubLVDS Input Rise and Fall Slew Rate VIH MIN LS_CLK Midpoint VIL MAX tSU tH VIH MIN LS_WDATA Midpoint VIL MAX tWINDOW VIH MIN Midpoint LS_CLK VIL MAX tDERATING tSU tH VIH MIN Midpoint LS_WDATA VIL MAX tWINDOW Figure 6-5. Window Time Derating Concept 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 tc tw(L) DCLK _ P DCLK _ N tw(H) 50% 50% 50% th tsu D_P (0:7) D_N(0:7) 50% 50% twindow Figure 6-6. SubLVDS Switching Parameters High Speed Training Scan Window tc DCLK _ P DCLK _ N ¼ tc ¼ tc D_P (0:7) D_N(0:7) Note: Refer to Section 7.3.3 for details. Figure 6-7. High-Speed Training Scan Window (VIP + V IN) / 2 DCLK _P , D_P(0:7) SubLVDS Receiver VID DCLK _N , D_N(0:7) VCM VIP VIN Figure 6-8. SubLVDS Voltage Parameters Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 15 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 1.225V V SubLVDS max = V CM max + | 1/2 * V ID max | VCM VID VSubLVDS min = VCM min – | 1/2 * VID max | 0.575V Figure 6-9. SubLVDS Waveform Parameters DCLK _P , D_P(0:7) ESD Internal Termination SubLVDS Receiver DCLK _N , D_N(0:7) ESD Figure 6-10. SubLVDS Equivalent Input Circuit Not to Scale VIH VT+ Δ VT VT- VIL LS_CLK LS_WDATA Figure 6-11. LPSDR Input Hysteresis LS_CLK LS_WDATA Stop Start tPD LS_RDATA Acknowledge Figure 6-12. LPSDR Read Out 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 Timing specification reference point Device pin output under test Tester channel CL See Timing for more information. Figure 6-13. Test Load Circuit for Output Propagation Measurement 6.8 Switching Characteristics Over operating free-air temperature range (unless otherwise noted).(1) PARAMETER tPD TEST CONDITIONS Output propagation, Clock to Q, rising edge of LS_CLK input to LS_RDATA output. (figure 12 xref) MIN CL = 45 pF MAX 15 Slew rate, LS_RDATA UNIT ns 0.5 Output duty cycle distortion, LS_RDATA (1) TYP V/ns 40% 60% Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted. 6.9 System Mounting Interface Loads PARAMETER MIN Thermal interface area (see Figure 6-14) Maximum system mounting interface Clamping and electrical interface area (see load to be applied to the: Figure 6-14) NOM MAX UNIT 62 N 110 N Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 17 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 Datum 'A' area (3 places) Datum 'E' area (1 place) Thermal Interface Area Clamping and Electrical Interface Area Figure 6-14. System Interface Loads 6.10 Physical Characteristics of the Micromirror Array PARAMETER ε (1) 18 VALUE UNIT Number of active columns See Figure 6-15 1920 micromirrors Number of active rows See Figure 6-15 1080 micromirrors Micromirror (pixel) pitch See Figure 6-16 5.4 µm Micromirror active array width Micromirror pitch × number of active columns; see Figure 6-15 10.368 mm Micromirror active array height Micromirror pitch × number of active rows; see Figure 6-15 5.832 mm Micromirror active border Pond of micromirror (POM)(1) 20 micromirrors/side The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM. These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to tilt toward OFF. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 Width . Mirror 1079 Mirror 1078 Mirror 1077 Mirror 1076 1920 × 1080 mirrors Height Mirror 3 Mirror 2 Mirror 1 Mirror 1919 Mirror 1918 Illumination Mirror 1917 Mirror 1916 Mirror 3 Mirror 2 Mirror 1 Mirror 0 Mirror 0 Figure 6-15. Micromirror Array Physical Characteristics H° H° H° H° Figure 6-16. Mirror (Pixel) Pitch Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 19 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 6.11 Micromirror Array Optical Characteristics PARAMETER Micromirror tilt angle TEST CONDITIONS DMD landed Micromirror tilt angle tolerance(2) (3) (4) (5) Micromirror tilt direction (6) (7) 180 270 Typical performance (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) 20 degree degree 3 10 Gray 10 Screen (12) 0 Bright pixel(s) in the POM (13) Gray 10 Screen (12) 1 Dark pixel(s) in the active area (14) White Screen 4 Adjacent pixel(s) (15) Any Screen 0 Unstable pixel(s) in active area (16) Any Screen 0 (11) (1) (2) (3) (4) 1 UNIT degree 1.4 Landed OFF state Typical performance MAX 17 Landed ON state Micromirror switching time(9) Image performance(10) NOM –1.4 Micromirror crossover time(8) Bright pixel(s) in active area MIN state(1) µs micromirrors Measured relative to the plane formed by the overall micromirror array. Additional variation exists between the micromirror array and the package datums. Represents the landed tilt angle variation relative to the nominal landed tilt angle. Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different devices. For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in colorimetry variations, system efficiency variations, or system contrast variations. When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON state direction. A binary value of 0 results in a micromirror landing in the OFF state direction. See Figure 6-17. Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° reference which is aligned with the +X Cartesian axis. The time required for a micromirror to nominally transition from one landed state to the opposite landed state. The minimum time between successive transitions of a micromirror. Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions: Test set degamma shall be linear Test set brightness and contrast shall be set to nominal The diagonal size of the projected image shall be a minimum of 20 inches The projections screen shall be 1X gain The projected image shall be inspected from a 38 inch minimum viewing distance The image shall be in focus during all image quality tests Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels Gray 10 screen definition: All areas of the screen are colored with the following settings: Red = 10/255 Green = 10/255 Blue = 10/255 POM definition: Rectangular border of off-state mirrors surrounding the active area Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable pixel appears to be flickering asynchronously with the image Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 Off-state light path (1079, 1919) Off-state landed edge (0, 0) Tilted axis of pixel rotation On-state landed edge Incident illumination light path Figure 6-17. Landed Pixel Orientation and Tilt 6.12 Window Characteristics PARAMETER(1) MIN Window material designation Window refractive index Window MAX UNIT Corning Eagle XG at wavelength 546.1 nm 1.5119 aperture(2) See (2) Illumination overfill(3) See (3) Window transmittance, single-pass through both surfaces and glass Minimum within the wavelength range 420 to 680 nm. Applies to all angles 0° to 30° AOI. 97% Window Transmittance, single-pass through both surfaces and glass Average over the wavelength range 420 to 680 nm. Applies to all angles 30° to 45° AOI. 97% (1) (2) (3) NOM See Optical Interface and System Image Quality Considerations for more information. See the package mechanical characteristics for details regarding the size and location of the window aperture. The active area of the DLP4710LC device is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the average flux level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light on the outside of the active array may cause system performance degradation. SPACER 6.13 Chipset Component Usage Specification The DLP4710 is a component of one or more TI ®DLP chipsets. Reliable function and operation of the DLP4710 requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DLP DMD. Note TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 21 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 6.14 Software Requirements Note The DLP4710 DMD has mandatory software requirements. Refer to Software Requirements for TI TRP Digital Micromirror Devices application report for additional information. Failure to use the specified software will result in failure at power up. ®DLP ™Pico 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 7 Detailed Description 7.1 Overview The DLP4710LC device is a 0.47 inch diagonal spatial light modulator of aluminum micromirrors. Pixel array size is 1920 columns by 1080 rows in a square grid pixel arrangement. The electrical interface is Sub Low Voltage Differential Signaling (SubLVDS) data. DLP4710LC device is part of the chipset comprising the DLP4710LC DMD, DLPC3479 controller, and DLPA3000 or DLPA3005 PMIC/LED driver. To ensure reliable operation, the DLP4710LC DMD must always be used with either the DLPC3479 controller and the DLPA3000 or DLPA3005 PMIC/LED drivers. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 23 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 7.2 Functional Block Diagram 24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 Note Simplified for clarity. 7.3 Feature Description 7.3.1 Power Interface The power management IC, DLPA3000/DLPA3005, contains three regulated DC supplies for the DMD reset circuitry: VBIAS, VRESET and VOFFSET, as well as the 2 regulated DC supplies for the DLPC3479 controller. 7.3.2 Low-Speed Interface The Low Speed Interface handles instructions that configure the DMD and control reset operation. LS_CLK is the low–speed clock, and LS_WDATA is the low speed data input. 7.3.3 High-Speed Interface The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed DDR transfer and compression techniques to save power and time. The high-speed interface is composed of differential SubLVDS receivers for inputs, with a dedicated clock. 7.3.4 Timing The data sheet provides timing test results at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be considered. Figure 6-13 shows an equivalent test load circuit for the output under test. Timing reference loads are not intended as a precise representation of any particular system environment or depiction of the actual load presented by a production test. TI recommends that system designers use IBIS or other simulation tools to correlate the timing reference load to a system environment. The load capacitance value stated is intended for characterization and measurement of AC timing signals only. This load capacitance value does not indicate the maximum load the device is capable of driving. 7.4 Device Functional Modes DMD functional modes are controlled by the DLPC3479 controller. See the DLPC3479 controller data sheet or contact a TI applications engineer. 7.5 Optical Interface and System Image Quality Considerations Note TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously. 7.5.1 Optical Interface and System Image Quality TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters. Optimizing system optical performance and image quality strongly relate to optical system design parameter trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical performance is contingent on compliance to the optical system operating conditions described in the following sections. 7.5.1.1 Numerical Aperture and Stray Light Control The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area is typically the same. Ensure this angle does not exceed the nominal device micromirror tilt angle unless appropriate apertures are added in the illumination or projection pupils to block out flat-state and stray light from the projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any other light path, including undesirable flat–state specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 25 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts in the display border and/or active area may occur. 7.5.1.2 Pupil Match The optical and image quality specifications assume that the exit pupil of the illumination optics is nominally centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display border and/or active area. These artifacts may require additional system apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle. 7.5.1.3 Illumination Overfill The active area of the device is surrounded by an aperture on the inside DMD window surface that masks structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window aperture opening and other surface anomalies that may be visible on the screen. Be sure to design an illumination optical system that limits light flux incident anywhere on the window aperture from exceeding approximately 10% of the average flux level in the active area. Depending on the particular optical architecture, overfill light may require further reduction below the suggested 10% level in order to be acceptable. 7.6 Micromirror Array Temperature Calculation 2X 12.89 TP2 Off-state Light TP4 TP5 2X 5.50 TP3 Window Edge (4 surfaces) TP4 Illumination Direction TP3 (TP2) TP5 TP1 12.70 TP1 2.00 Figure 7-1. DMD Thermal Test Points Micromirror array temperature can be computed analytically from measurement points on the outside of the package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat load. The relationship between micromirror array temperature and the reference ceramic temperature is provided by the following equations: 26 TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC) (1) QARRAY = QELECTRICAL + QILLUMINATION (2) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 QILLUMINATION = (CL2W × SL) (3) where • TARRAY = Computed DMD array temperature (°C) • TCERAMIC = Measured ceramic temperature (°C), TP1 location in Figure 7-1 • RARRAY–TO–CERAMIC = DMD package thermal resistance from array to outside ceramic (°C/W) specified in Section 6.5 • QARRAY = Total DMD power; electrical plus absorbed (calculated) (W) • QELECTRICAL = Nominal DMD electrical power dissipation (W) • CL2W = Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified below • SL = Measured ANSI screen lumens (lm) The electrical power dissipation of the DMD varies and depends on the voltages, data rates and operating frequencies. Use a nominal electrical power dissipation of 0.25 W to calculate array temperature. Absorbed optical power from the illumination source varies and depends on the operating state of the micromirrors and the intensity of the light source. Equations shown above are valid for a 1-chip DMD system with total projection efficiency through the projection lens from DMD to the screen of 87%. The conversion constant CL2W is based on the DMD micromirror array characteristics. The conversion constant assumes a spectral efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and 16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00266 W/lm. The following is a sample calculation for typical projection application: TCERAMIC = 55°C (measured) SL = 1500 lm (measured) QELECTRICAL = 0.25 W CL2W = 0.00266 W/lm QARRAY = 0.25 W + (0.00266 W/lm × 1500 lm) = 4.24 W TARRAY = 55°C + (4.24 W × 1.1°C/W) = 59.66°C 7.7 Micromirror Landed-On/Landed-Off Duty Cycle 7.7.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a percentage) that an individual micromirror is landed in the ON state versus the amount of time the same micromirror is landed in the OFF state. As an example, a landed duty cycle of 75/25 indicates that the referenced pixel is in the ON state 75% of the time (and in the OFF state 25% of the time), whereas 25/75 indicates that the pixel is in the OFF state 75% of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time. When assessing landed duty cycle, the time spent switching from the current state to the opposite state is considered negligible and is thus ignored. Because a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages) nominally add to 100.In practice, image processing algorithms in the DLP chipset can result a total of less that 100. 7.7.2 Landed Duty Cycle and Useful Life of the DMD Knowing the long-term average landed duty cycle (of the end product or application) is important because subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed duty cycle for a prolonged period of time can reduce the DMD’s usable life. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 27 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 It is the symmetry or asymmetry of the landed duty cycle that is relevant. The symmetry of the landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly asymmetrical. 7.7.3 Landed Duty Cycle and Operational DMD Temperature Operational DMD temperature and landed duty cycle interact to affect the usable life of the DMD. This interaction can be used to reduce the impact that an asymmetrical landed duty cycle has on the useable life of the DMD. Figure 6-1 describes this relationship. The importance of this curve is that: • • • All points along this curve represent the same usable life. All points above this curve represent lower usable life (and the further away from the curve, the lower the usable life). All points below this curve represent higher usable life (and the further away from the curve, the higher the usable life). In practice, this curve specifies the maximum operating DMD temperature that the DMD should be operated at for a give long-term average landed duty cycle. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application During a given period of time, the landed duty cycle of a given pixel depends on the image content being displayed by that pixel. In the simplest case for example, when the system displays pure-white on a given pixel for a given time period, that pixel operates very close to a 100/0 landed duty cycle during that time period. Likewise, when the system displays pure-black, the pixel operates very close to a 0/100 landed duty cycle. Between the two extremes (ignoring for the moment color and any image processing that may be applied to an incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in Table 7-1. Table 7-1. Grayscale Value and Landed Duty Cycle Grayscale Value Nominal Landed Duty Cycle 0% 0/100 10% 10/90 20% 20/80 30% 30/70 40% 40/60 50% 50/50 60% 60/40 70% 70/30 80% 80/20 90% 90/10 100% 100/0 To account for color rendition (and continuing to ignore image processing for this example) requires knowing both the color intensity (from 0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color cycle time for each primary color, where color cycle time describes the total percentage of the frame time that a given primary must be displayed in order to achieve the desired white point. During a given period of time, the nominal landed duty cycle of a given pixel can be calculated as shown in Equation 4: 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% × Blue_Scale_Value) (4) where • • • Red_Cycle_% represents the percentage of the frame time that red displays to achieve the desired white point Green_Cycle_% represents the percentage of the frame time that green displays to achieve the desired white point Blue_Cycle_% represents the percentage of the frame time that blue displays to achieve the desired white point For example, assume that the ratio of red, green and blue color cycle times are as listed in Table 7-2 (in order to achieve the desired white point) then the resulting nominal landed duty cycle for various combinations of red, green, blue color intensities are as shown in Table 7-3. Table 7-2. Example Landed Duty Cycle for Full-Color Pixels Red Cycle Percentage Green Cycle Percentage Blue Cycle Percentage 50% 20% 30% Table 7-3. Color Intensity Combinations Red Scale Value Green Scale Value Blue Scale Value Nominal Landed Duty Cycle 0% 0% 0% 0/100 100% 0% 0% 50/50 0% 100% 0% 20/80 0% 0% 100% 30/70 12% 0% 0% 6/94 0% 35% 0% 7/93 0% 0% 60% 18/82 100% 100% 0% 70/30 0% 100% 100% 50/50 100% 0% 100% 80/20 12% 35% 0% 13/87 0% 35% 60% 25/75 12% 0% 60% 24/76 100% 100% 100% 100/0 The last factor to consider when estimating the landed duty cycle is any applied image processing. In the DLPC34xx controller family, the two functions which influence the actual landed duty cycle are Gamma and IntelliBright™, and bitplane sequencing rules. Gamma is a power function of the form Output_Level = A × Input_LevelGamma, where A is a scaling factor that is typically set to 1. In the DLPC34xx controller family, gamma is applied to the incoming image data on a pixel-by-pixel basis. A typical gamma factor is 2.2, which transforms the incoming data as shown in Figure 7-2. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 29 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 100 90 Output Level (%) 80 Gamma = 2.2 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 Input Level (%) 70 80 90 100 D002 Figure 7-2. Example of Gamma = 2.2 As shown in Figure 7-2, when the gray scale value of a given input pixel is 40% (before gamma is applied), then gray scale value is 13% after gamma is applied. Because gamma has a direct impact on the displayed gray scale level of a pixel, it also has a direct impact on the landed duty cycle of a pixel. The IntelliBright algorithms content adaptive illumination control (CAIC) and local area brightness boost (LABB) also apply transform functions on the gray scale level of each pixel. But while amount of gamma applied to every pixel (of every frame) is constant (the exponent, gamma, is constant), CAIC and LABB are both adaptive functions that can apply a different amounts of either boost or compression to every pixel of every frame. Consideration must also be given to any image processing which occurs before the DLPC3439 or DLPC3479 controller. 30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 8 Application and Implementation 8.1 Application Information The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two directions, with the primary direction being into a projection or collection optic. Each application is derived primarily from the optical architecture of the system and the format of the data coming into the dual DLPC3479 controllers. The new high tilt pixel in the bottom-illuminated DMD increases brightness performance and enables a smaller system footprint for thickness constrained applications. Applications of interest include DMD power-up and power-down sequencing is strictly controlled by the DLPA3000/DLPA3005. Refer to Power Supply Recommendations for power-up and power-down specifications. To ensure reliable operation, the DLP4710LC DMD must always be used with two DLPC3479 controllers and a DLPA3000 or DLPA3005 PMIC/LED driver. 8.2 Typical Application A pico-projector that can be used as an accessory to a smartphone, tablet or a laptop is a common application when using a DLP4710LC DMD and two DLPC3479 devices. The two DLPC3479 devices in the pico-projector receive images from a multimedia front end within the product as shown in Figure 8-1. PROJ_ON Microcontroller Front End MSP430 Tiva PROJ_ON SPI Flash GPIO_8 (Normal Park) VCC_FLSH SPI(4) RESETZ INTZ LED_SEL(2) SPI_1 PARKZ SPI_0 HOST_IRQ Focus stepper motor VLED DLPC3479 eDRAM I2C Current Sense Illuminator 1.8 V 1.1 V for DLPC3479 VSPI 1.8 V for DMD and DLPC3479 VCC_INTF BIAS, RST, OFS 3 SYSPWR TRIG_IN 3DR 1.8 V VIO 1.1 V VCORE Monochrome (1) Illumination DLPA3000 TSTPT_4 TRIG_OUT1 GPIO_7 TRIG_OUT2 Sub-LVDS DATA (18) CTRL GPIO5 I2C_1 Image Sync GPIO6 I2C I2C_0 Illumination Optics DLP4710LC sd DMD RESETZ INTZ VCC_FLSH Oscillator DLPC3479 eDRAM SPI Flash SPI_0 VCC_INTF Included in DLP® Chip Set Non-DLP components 1.8 V 1.1 V VIO VCORE LS RDATA Sub-LVDS DATA (18) Figure 8-1. Typical Application Diagram 8.2.1 Design Requirements A pico-projector is created by using a DLP chip set comprised of a DLP4710 DMD, two DLPC3439 controllers and a DLPA3000/DLPA3005 PMIC/LED driver. The DLPC3439 controllers do the digital image processing, the DLPA3000/DLPA3005 provides the needed analog functions for the projector, and the DLP4710 DMD is the display device for producing the projected image. In addition to the three DLP chips in the chip set, other chips are needed. At a minimum a Flash part is needed to store the software and firmware to control each DLPC3439 controller. The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These are often contained in three separate packages, but sometimes more than one color of LED die may be in the same package to reduce the overall size of the pico-projector. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 31 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 For connecting the DLPC3439 controllers to the multimedia front end for receiving images, a 24-bit parallel interface is used. An I2C interface should be connected to the multimedia front end for sending commands to one of the DLPC3439 controllers for configuring the DLPC3439 controller for different features. 8.2.2 Detailed Design Procedure For connecting the two DLPC3439 controllers, the DLPA3000/DLPA3005, and the DLP4710 DMD, see the reference design schematic. When a circuit board layout is created from this schematic a very small circuit board is possible. An example small board layout is included in the reference design data base. Layout guidelines should be followed to achieve a reliable projector. The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical OEM who specializes in designing optics for DLP projectors. 8.2.3 Application Curve As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white screen lumens changes with LED currents is as shown in Figure 8-2. For the LED currents shown, it’s assumed that the same current amplitude is applied to the red, green, and blue LEDs. Figure 8-2. Luminance vs Current 32 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 9 Power Supply Recommendations The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required. DMD power-up and power-down sequencing is strictly controlled by the DLPA3000/DLPA3005 devices. Note For reliable operation of the DMD, the following power supply sequencing requirements must be followed. Failure to adhere to the prescribed power-up and power-down procedures may affect device reliability. VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-up and power-down operations. Failure to meet any of the below requirements will result in a significant reduction in the DMD’s reliability and lifetime. Refer to Figure 23. VSS must also be connected. VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-up and power-down operations. Failure to meet any of the below requirements will result in a significant reduction in the DMD’s reliability and lifetime. Refer to Figure 23. VSS must also be connected. 9.1 DMD Power Supply Power-Up Procedure • • • • • During the power-up sequence, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET voltages are applied to the DMD. During the power-up sequence, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be within the specified limit shown in Section 6.4. Refer to Table 9-1 for the power-up sequence, delay requirements. During the power-up sequence, there is no requirement for the relative timing of VRESET with respect to VBIAS and VOFFSET. Power supply slew rates during the power-up sequence are flexible, provided that the transient voltage levels follow the requirements specified in Section 6.1, in Section 6.4, and in Section 9.3. During the power-up sequence, LPSDR input pins must not be driven high until after VDD/VDDI have settled at operating voltages listed in Section 6.4. 9.2 DMD Power Supply Power-Down Procedure • • • • • The power-down sequence is the reverse order of the previous power-up sequence. During the power-down sequence, VDD and VDDI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground. During the power-down sequence, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be within the specified limit shown in Section 6.4. During the power-down sequence, there is no requirement for the relative timing of VRESET with respect to VBIAS and VOFFSET. Power supply slew rates during the power-down sequence, are flexible, provided that the transient voltage levels follow the requirements specified in Section 6.1, inSection 6.4, and in Section 9.3. During the power-down sequence, LPSDR input pins must be less than VDD/VDDI specified in Section 6.4. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 33 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 9.3 Power Supply Sequencing Requirements DLP Display Controller and PMIC control start of DMD operation DRAWING NOT TO SCALE. DETAILS OMITTED FOR CLARITY. DLP Display Controller and PMIC disable VBIAS, VOFFSET and VRESET Mirror Park Sequence Note 4 Power Off VDD / VDDI VDD / VDDI VDD / VDDI VSS VSS VOFFSET VOFFSET 9'' ” 92))6(7 < 6 V VOFFSET VBIAS < 4 V VSS Note 2 Note 3 Note 1 Note 2 VSS ûV < Specification Limit 9'' ” 9%,$6 < 6 V ûV < Specification Limit VBIAS ûV < Specification Limit VBIAS VBIAS VOFFSET < 4 V VSS VSS VRESET < 0.5 V VSS VSS VRESET > - 4 V VRESET VRESET VRESET VDD VDD DMD_DEN_ARSTZ VSS INITIALIZATION LS_CLK LS_WDATA VSS VDD VDD VSS VSS VID VID D_P(0:7), D_N(0:7) DCLK_P, DCLK_N VSS VSS A. B. C. D. DLP controller and PMIC controls start of DMD operation Mirror park sequence starts Mirror park sequence ends. DLP controller and PMIC disables VBIAS, VOFFSET, and VRESET. Power off. E. F. Refer to Table 9-1 and Figure 9-2 for critical power-up sequence delay requirements. When system power is interrupted, the ASIC driver initiates hardware the power-down sequence, that disables VBIAS, VRESET and VOFFSET after the micromirror park sequence is complete. Software the power-down sequence, disables VBIAS, VRESET, and VOFFSET after the micromirror park sequence through software control. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in Section 6.4. Drawing is not to scale and details are omitted for clarity. G. H. Figure 9-1. Power Supply Sequencing Requirements (Power Up and Power Down) 34 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 Table 9-1. Power-Up Sequence Delay Requirement PARAMETER MIN MAX 2 UNIT tDELAY Delay requirement from VOFFSET power up to VBIAS power up ms VOFFSET Supply voltage level during power–up sequence delay (see Figure 9-2) 6 V VBIAS Supply voltage level during power–up sequence delay (see Figure 9-2) 6 V 12 V VOFFSET 8V VDD ≤ VOFFSET < 6 V 4V VSS tDELAY 0V VBIAS 20 V 16 V 12 V 8V VDD ≤ VBIAS < 6 V 4V VSS A. 0V Refer to Table 9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay. Figure 9-2. Power-Up Sequence Delay Requirement Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 35 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 10 Layout 10.1 Layout Guidelines There are no specific layout guidelines for the DMD as typically DMD is connected using a board to board connector to a flex cable. Flex cable provides the interface of data and Ctrl signals between the DLPC3439 controller and the DLP4710 DMD. For detailed layout guidelines refer to the layout design files. Some layout guideline for the flex cable interface with DMD are: • • • • • • Match lengths for the LS_WDATA and LS_CLK signals. Minimize vias, layer changes, and turns for the HS bus signals. Refer Figure 10-1. Minimum of two 220-nF decoupling capacitor close to VBIAS. Capacitor C3 and C10 in Figure 10-1. Minimum of two 220-nF decoupling capacitor close to VRST. Capacitor C1 and C9 in Figure 10-1. Minimum of two 220-nF decoupling capacitor close to VOFS. Capacitor C2 and C8 in Figure 10-1. Minimum of four 220-nF decoupling capacitor close to VDDI and VDD. Capacitor C4, C5, C6 and C7 in Figure 10-1. 10.2 Layout Example Figure 10-1. Power Supply Connections 36 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Device Nomenclature DLP4710A FQL Package Type Device Descriptor Figure 11-1. Part Number Description 11.1.3 Device Markings The device marking includes the legible character string GHJJJJK DLP4710AFQL. GHJJJJK is the lot trace code. DLP4710AFQL is the device marking. Two-dimensional matrix code DMD part number and lot trace code Lot Trace Code GHJJJJK DLP4710AFQL Part Marking Figure 11-2. DMD Marking Locations 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 11-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY DLP4710 Click here Click here Click here Click here Click here DLPC3439 Click here Click here Click here Click here Click here DLPA3000 Click here Click here Click here Click here Click here DLPA3005 Click here Click here Click here Click here Click here Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 37 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.5 Trademarks Pico™, IntelliBright™, and TI E2E™ are trademarks of Texas Instruments. DLP® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary TI Glossary 38 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 DLP4710 www.ti.com DLPS125B – NOVEMBER 2018 – REVISED MAY 2022 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4710 39 PACKAGE OPTION ADDENDUM www.ti.com 11-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) DLP4710AFQL ACTIVE CLGA FQL 100 80 RoHS & Green NI/AU N / A for Pkg Type 0 to 70 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of