DRV595DAP

DRV595 www.ti.com SLOS808A – DECEMBER 2012 – REVISED MARCH 2013 15V/±4A High-Efficiency PWM Power Driver Check for Samples: DRV595 FEATURES • 1 • • • • 2 • • • ±4 A Output Current Wide Supply Voltage Range: 4.5 V – 26 V High Efficiency Generates Less Heat Multiple Switching Frequencies – Master/Slave Synchronization – Up to 1.2 MHz Switching Frequency Feedback Power Stage Architecture with High PSRR Reduces PSU Requirements Single Power Supply Reduces Component Count Integrated Self-Protection Circuits Including Over-Voltage, Under-Voltage, OverTemperature, and Short Circuit with Error Reporting • Thermally Enhanced Package – DAP (32-pin HTSSOP Pad-down) –40°C to 85°C Ambient Temperature Range APPLICATIONS • • • • • Power Line Communications (PLC) Driver Thermoelectric Cooler (TEC) Driver Laser Diode Biasing Motor Driver Servo Amplifier DESCRIPTION The DRV595 is a high-efficiency, high-current power driver ideal for driving a wide variety of loads in systems powered from 4.5V to 26V. PWM operation and low output stage on-resistance significantly decrease power dissipation in the amplifier. The DRV595 advanced oscillator/PLL circuit employs multiple switching frequency options; this is achieved together with a Master/Slave option, making it possible to synchronize multiple devices. The DRV595 is fully protected against faults with short-circuit, thermal, over-voltage, and under-voltage protection. Faults are reported back to the processor to prevent devices from being damaged during overload conditions. SIMPLIFIED APPLICATION CIRCUIT MODSEL SDZ Shutdown Control FAULTZ IN+ Control Voltage PVCC VCC BSP OUTP IN- VCC GVDD GND LOAD GAIN/SLV DRV595 GND HI-Z Hi-Z FS2 VCC SYNC OUTN FS1 BSN FS0 PVCC SYNC AVCC VCC 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated DRV595 SLOS808A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SYSTEM BLOCK DIAGRAM GVDD SDZ Hi-Z PVCC BSP PVCC TTL Buffer Modulation Select Gain Control OUTP_FB Gate Drive GAIN OUTP + OUTP_FB – IN+ IN– Gain Control + + – – + – + – GND PWM Logic – GVDD OUTPN_FB Gate Drive SC Detect SYNC Ramp Generator FS Biases and References BSN OUTN_ FB + FAULTZ GAIN/SLV PVCC PVCC Startup Protection Logic OUTN GND Thermal Detect UVLO/OVLO AVDD AVCC LDO Regulator GVDD GVDD PVCC PVCC GND Thermal Pad 2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DRV595 DRV595 www.ti.com SLOS808A – DECEMBER 2012 – REVISED MARCH 2013 PINOUT CONFIGURATION DRV595 32-PIN HTSSOP Package (DAP) (Top View) MODSEL 1 32 PVCC SDZ 2 31 PVCC FAULTZ 3 30 BSP IN+ 4 29 OUTP IN– 5 28 GND GVDD 6 27 OUTP GVDD 7 26 BSP GAIN/SLV 8 GND GND 9 Thermal PAD 25 24 BSN GND 10 Bottom 23 OUTN GND 11 22 GND Hi-Z FS2 12 21 OUTN 13 20 BSN FS1 14 19 PVCC FS0 15 18 PVCC SYNC 16 17 AVCC Pin Functions PIN NO. NAME TYPE DESCRIPTION 1 MODSEL I Mode selection logic input (LOW = BD mode, HIGH = 1SPW mode). TTL logic levels with compliance to AVCC. 2 SDZ I Shutdown logic input (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC. 3 FAULTZ 4 IN+ I Positive differential input. Biased at 3 V. 5 IN– I Negative differential input. Biased at 3 V. 6, 7 8 GVDD DO PO General fault reporting. Open drain. See Table 3 FAULTZ = High, normal operation FAULTZ = Low, fault condition Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1 µF X7R ceramic decoupling capacitor and the GAIN/SLV resistor divider. GAIN/SLV I Selects Gain and selects between Master and Slave mode depending on pin voltage divider. 9, 10, 11 GND G Ground 12 Hi-Z I Input for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC. 13 FS2 I Frequency Selection input, used to select oscillator frequencies from 400kHz to 1200kHz. 14 FS1 I Frequency Selection input, used to select oscillator frequencies from 400kHz to 1200kHz. 15 FS0 I Frequency Selection input, used to select oscillator frequencies from 400kHz to 1200kHz. 16 SYNC DIO Clock input/output for synchronizing multiple devices. Direction determined by GAIN/SLV terminal. 17 AVCC P Analog Supply, can be connected to PVCC for single power supply operation. 18, 19 PVCC P Power supply 20, 24 BSN BST Boot strap for negative output, connect to 220 nF X5R, or better ceramic cap to OUTN 21 OUTN PO Negative output 22 GND 23 OUTN 25 GND G 26, 30 BSP BST G PO Ground Negative output Ground Boot strap for positive output, connect to 220 nF X5R, or better ceramic cap to OUTP Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DRV595 3 DRV595 SLOS808A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com Pin Functions (continued) PIN NO. NAME TYPE DESCRIPTION 27 OUTP PO 28 GND G 29 OUTP PO Positive output 31, 32 PVCC P Power supply Thermal Pad or PowerPAD ™ G Connect to GND for best system performance. If not connected to GND, leave floating. 33 Positive output Ground ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT PVCC, AVCC –0.3 to 30 V IN+, IN– –0.3 to 6.3 V GAIN / SLV, SYNC –0.3 to GVDD+0.3 V SDZ, MODSEL –0.3 to PVCC+0.3 V 10 V/msec Operating free-air temperature, TA –40 to 85 °C Operating junction temperature range, TJ –40 to 150 °C Storage temperature range, Tstg –40 to 125 °C ±2 kV ±500 V Supply voltage, VCC Input voltage, VI Slew rate, maximum (2) FS0, FS1, FS2, HI-Z, SDZ, MODSEL Electrostatic discharge: Human body model, ESD Electrostatic discharge: Charged device model, ESD (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 100 kΩ series resistor is needed if maximum slew rate is exceeded. THERMAL INFORMATION DRV595 THERMAL METRIC (1) DAP 2 Layer PCB (2) UNITS 32 PINS θJA Junction-to-ambient thermal resistance 22 ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 4.8 (1) (2) 4 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. For the PCB layout please see the DRV595EVM user guide. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DRV595 DRV595 www.ti.com SLOS808A – DECEMBER 2012 – REVISED MARCH 2013 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX VCC Supply voltage PVCC, AVCC VIH High-level input voltage FS0, FS1, FS2, Hi-Z, SDZ, SYNC, MODSEL VIL Low-level input voltage FS0, FS1, FS2, Hi-Z, SDZ, SYNC, MODSEL 0.8 V VOL Low-level output voltage FAULTZ, RPULL-UP = 100 kΩ, PVCC = 26 V 0.8 V IIH High-level input current FS0, FS1, FS2, Hi-Z, SDZ, MODSEL (VI = 2 V, VCC = 18 V) 50 µA RL Minimum load Impedance Output filter: L = 10 µH, C = 3.3 µF Output-filter Inductance Minimum output filter inductance under short-circuit condition Lo 4.5 UNIT 26 V 2 V 1.6 Ω 1 µH ELECTRICAL CHARACTERISTICS TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 5 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS | VOS | Output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB | IIH | High-level input current VCC = 24 V, VI = VCC ICC Quiescent supply current ICC(SD) Quiescent supply current in shutdown mode rDS(on) Drain-source on-state resistance, measured pin to pin G G Gain (MSTR) Gain (SLV) MIN 1.5 15 mV 50 µA 30 SDZ = 2 V, No load or filter, PVCC = 24 V 50 SDZ = 0.8 V, No load or filter, PVCC = 12 V 150°C Low Output high impedance Latched Under Voltage on PVCC PVCC < 4.5V – Output high impedance Self-clearing Over Voltage on PVCC PVCC > 27V – Output high impedance Self-clearing SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE The DRV595 has protection from over current conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FAULTZ pin as a low state. The amplifier outputs are switched to a high impedance state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SDZ pin through the low state. If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the shortcircuit protection latch. > 1.4sec SDZ mP Hi-Z DRV595 FAULTZ SDZ Hi-Z FAULTZ Figure 15. Timing Requirement for SDZ THERMAL PROTECTION Thermal protection on the DRV595 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal trip point, the device enters into the shutdown state and the outputs are disabled. This is a latched fault. Thermal protection faults are reported on the FAULTZ terminal as a low state. If automatic recovery from the thermal protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the thermal protection latch. DRV595 MODULATION SCHEME The DRV595 has the option of running in either BD modulation or 1SPW modulation; this is set by the MODSEL pin. MODSEL = GND: BD-modulation 14 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DRV595 DRV595 www.ti.com SLOS808A – DECEMBER 2012 – REVISED MARCH 2013 This is a modulation scheme that allows for smaller ripple current through the TEC load. Each output switches from 0 volts to the supply voltage. With no input, OUTP and OUTN are in phase with each other so that there is little or no current in the load. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0V throughout most of the switching period, reducing the switching current, which reduces any I2R losses in the load. OUTP OUTN No Output OUTP–OUTN 0V Load Current OUTP OUTN OUTP–OUTN Positive Output PVCC 0V Load Current 0A OUTP OUTN Negative Output OUTP–OUTN 0V –PVCC 0A Load Current Figure 16. BD Mode Modulation Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DRV595 15 DRV595 SLOS808A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com MODSEL = HIGH: 1SPW-modulation The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty in ripple current and more attention required in the output filter selection. In 1SPW mode the outputs operate at ~15% modulation during idle conditions. When an input signal is applied one output decreases and one increases. The decreasing output signal quickly rails to GND at which point all the modulation takes place through the rising output. The result is that often only one output is switching. Efficiency is improved in this mode due to the reduction of switching losses. The resulting output signal at each half output has a discontinuity each time the output rails to GND. This can cause ringing in the output filter unless care is taken in the selection of the filter components and type of filter used. OUTP OUTN No Output OUTP–OUTN 0V Load Current OUTP OUTN Positive Output OUTP–OUTN PVCC 0V Load Current 0A OUTP OUTN Negative Output OUTP–OUTN 0V –PVCC 0A Load Current Figure 17. 1SPW Mode Modulation 16 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DRV595 DRV595 www.ti.com SLOS808A – DECEMBER 2012 – REVISED MARCH 2013 POWER DISSIPATION AND MAXIMUM AMBIENT TEMPERATURE Though the DRV595 is much more efficient than traditional linear solutions, the power drop across the onresistance of the output transistors does generate some heat in the package, which may be calculated as shown in Equation 5: P ǒ OUTǓ 2 + I r DS(on), total For example, at the maximum output current of 3 A through a total on-resistance of 60 mΩ (at TJ = 25°C), the power dissipated in the package is 1.1 W. (5) DISS Calculate the maximum ambient temperature using Equation 6: ǒ T A + TJ * θ JA P DISS Ǔ (6) PRINTED-CIRCUIT BOARD (PCB LAYOUT) It is necessary to take care when planning the layout of the printed circuit board. The following suggestions will help to meet EMC requirements. • Decoupling capacitors — The high-frequency decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. Large (100 μF or greater) bulk power supply decoupling capacitors should be placed near the DRV595 on the PVCC supplies. Local, high-frequency bypass capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the IC GND pad directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between 220 pF and 1 nF and a larger mid-frequency cap of value between 100 nF and 1 µF also of good quality to the PVCC connections at each end of the chip. • Grounding — The PVCC decoupling capacitors should connect to GND. All ground should be connected at the IC GND, which should be used as a central ground connection or star ground for the DRV595. For an example layout, see the DRV595 Evaluation Module (DRV595EVM) User Manual. Both the EVM user's manual and the thermal pad application report are available on the TI Web site at http://www.ti.com. spacer REVISION HISTORY Changes from Original (December 2012) to Revision A Page • Changed Title From: 15V/±3A High-Efficiency PWM Power Driver To: 15V/±4A High-Efficiency PWM Power Driver ....... 1 • Changed Feature From: ±3 A Output Current To: ±4 A Output Current .............................................................................. 1 • Changed the Over current trip point TYP value From: 3 A To: 7.5 A ................................................................................... 6 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DRV595 17 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DRV595DAP ACTIVE HTSSOP DAP 32 46 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DRV595 DRV595DAPR ACTIVE HTSSOP DAP 32 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DRV595 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of