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TLC5952
SBVS129A – MAY 2009 – REVISED JULY 2018
24-Channel, Constant-Current LED Driver With
Global Brightness Control And LED Open-Short Detection
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
24-Channel Constant-Current Sink Output With
On-Off Control
Current Capability:
– 35 mA for 16 Channels
– 26.2 mA for 8 Channels
Global Brightness Control (BC) for Each Color
Group: 7-Bit (128 Step), Three Groups
LED Power-Supply Voltage up to 15 V
VCC = 3 V to 5.5 V
Constant-Current Accuracy:
– Channel-to-Channel = ±1%
– Device-to-Device = ±3%
CMOS Logic Level I/O
Data Transfer Rate: 35 MHz
BLANK Pulse Duration: 15 ns
Open-Load, Shorted-Load, and Overtemperature
Detection
Thermal Shutdown (TSD) With Auto Restart
Delay Switching to Prevent Inrush Current
Operating Temperature: –40°C to 85°C
Packages: HTSSOP-32, QFN-32
Full-Color LED Displays
LED Signboards
3 Description
The TLC5952 device is a 24-channel, constantcurrent sink driver. Each channel can be turned on or
off with internal register data. The output channels
are grouped into three groups of eight channels each.
Each channel group has a 128-step global brightness
control (BC) function. Both on-off data and BC are
writable via a serial interface. The maximum current
value of all 24 channels is set by a single external
resistor.
The TLC5952 device has three error detection
circuits: LED-open detection (LOD), LED-shorted
detection (LSD), and a thermal error flag (TEF). The
error detection is read via a serial interface.
Device Information(1)
PART NUMBER
PACKAGE
TLC5952
BODY SIZE (NOM)
HTSSOP (32)
11.00 mm × 6.20 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit (Multiple Daisy-Chained TLC5952s)
VLED
+
OUTR0
DATA
¼
¼
¼
¼
¼
¼
¼
SIN
SCLK
OUTB7
SCLK
LAT
LAT
BLANK
BLANK
OUTR0
SOUT
OUTB7
SOUT
SCLK
VCC
TLC5952
IC1
¼
SIN
LAT
VCC
BLANK
GND
VCC
TLC5952
ICn
VCC
GND
Controller
IREF
IREF
RIREF
RIREF
3
ERROR
READ
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC5952
SBVS129A – MAY 2009 – REVISED JULY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1 Absolute Maximum Ratings .................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions...................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics.......................................... 6
6.6 Switching Characteristics......................................... 8
6.7 Typical Characteristics ............................................ 11
7
Parameter Measurement Information ................ 15
7.1
Pin Equivalent Input and Output Schematic
Diagrams.................................................................. 15
7.2 Test Circuits ............................................................ 15
8
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
17
19
9 Power Supply Recommendations...................... 25
10 Device and Documentation Support ................. 26
10.1
10.2
10.3
10.4
10.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
11 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2009) to Revision A
Page
•
Changed "Pulse Width" to "Pulse Duration" ........................................................................................................................... 1
•
Added the Device Information table ....................................................................................................................................... 1
•
Deleted pinout diagram for the RHB package........................................................................................................................ 3
•
Deleted the RHB column and corresponding table note from the Pin Functions table .......................................................... 3
•
Changed "free-air" in the Absolute Maximum Ratings condition statement to "junction"....................................................... 4
•
Deleted ESD ratings from the Absolute Maximum Ratings table........................................................................................... 4
•
Deleted the Dissipation Ratings section ................................................................................................................................ 4
•
Added the ESD Ratings section ............................................................................................................................................. 4
•
Changed TWH0 to tWH0 in the Recommended Operating Conditions table.............................................................................. 5
•
Added the Thermal Information table to the data sheet ........................................................................................................ 5
•
Changed Condition statement of Electrical Characteristics table from TA = –40°C to 85°C to TJ = –40°C to 150°C ............ 6
•
Changed the Electrical Characteristics table to combine multiple symbols for the Supply current and Constantoutput current parameters ...................................................................................................................................................... 6
•
Changed MAX value of VIREEF in Electrical Characteristics from 1.23 V to 1.25 V ................................................................ 7
•
Changed Txx to txx at multiple locations in Figure 1 ................................................................................................................ 8
•
Changed Txx to txx at multiple locations in Figure 3 .............................................................................................................. 10
•
Changed Figure 6................................................................................................................................................................. 11
•
Added the Overview section................................................................................................................................................. 16
•
Added the Device Functional Modes section ....................................................................................................................... 19
•
Added the Device and Documentation Support and Mechanical, Packaging, and Orderable Information sections............ 26
2
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SBVS129A – MAY 2009 – REVISED JULY 2018
5 Pin Configuration and Functions
DAP PowerPAD™ Package
32-Pin HTSSOP With Exposed Thermal Pad
Top View
GND
1
32
IREF
SIN
2
31
SCLK
3
30
VCC
SOUT
LAT
4
29
BLANK
OUTR0
5
28
OUTB7
OUTG0
6
27
OUTG7
OUTB0
7
26
OUTR7
OUTR1
8
25
OUTB6
OUTG1
9
24
OUTG6
OUTB1
10
23
OUTR6
OUTR2
11
22
OUTB5
OUTG2
12
21
OUTG5
OUTB2
13
20
OUTR5
OUTR3
14
19
OUTB4
OUTG3
15
18
OUTG4
OUTB3
16
17
OUTR4
Thermal
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
All outputs are blank. When BLANK is high, all constant-current outputs (OUTR0–OUTR7,
OUTG0–OUTG7, and OUTB0–OUTB7) are forced off. When BLANK is low, all constant
current outputs are controlled by the on-off control data in the data latch.
BLANK
29
I
GND
1
—
Power ground
IREF
32
I/O
Reference current terminal. The maximum current for the outputs OUTR0–OUTR7,
OUTG0–OUTG7, and OUTB0–OUTB7 is set with a resistor from IREF to GND.
LAT
4
I
Edge-triggered latch. The rising edge of LAT latches the data from the common shift register
into the output on-off data latch. See the Output On-Off Data Latch section for more details.
OUTB0–OUT
B7
7, 10, 13, 16,
19, 22, 25,
28
O
Constant-current outputs for the BLUE LED group.
Multiple outputs can be configured in parallel to increase the constant-current capability.
Different voltages can be applied to each output. These outputs are turned on or off by the
BLANK signal and the data in the output on-off control data latch.
OUTG0–OUT
G7
6, 9, 12, 15,
18, 21, 24,
27
O
Constant-current outputs for the GREEN LED group.
Multiple outputs can be configured in parallel to increase the constant-current capability.
Different voltages can be applied to each output. These outputs are turned on or off by the
BLANK signal and the data in the output on-off control data latch.
OUTR0–OUT
R7
5, 8, 11, 14,
17, 20, 23,
26
O
Constant-current outputs for the RED LED group.
Multiple outputs can be configured in parallel to increase the constant-current capability.
Different voltages can be applied to each output. These outputs are turned on or off by the
BLANK signal and the data in the output on-off control data latch.
SCLK
3
I
Serial data shift clock. Data present on SIN are shifted to the LSB of the common shift
register with the rising edge of SCLK. Data in the shift register are shifted toward the MSB at
each rising edge of SCLK. The MSB data of the common shift register appear on SOUT.
SIN
2
I
Serial data input for the 25-bit common shift register
SOUT
30
O
Serial data output. The MSB of the 25-bit common shift register is shifted out at the rising
edge of SCLK.
VCC
31
—
Power-supply voltage
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TLC5952
SBVS129A – MAY 2009 – REVISED JULY 2018
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6 Specifications
Absolute Maximum Ratings (1)
6.1
(2)
Over operating junction temperature range, unless otherwise noted.
PARAMETER
VCC
Supply voltage
IOUT
Output current (dc)
VIN
Input voltage range
VOUT Output voltage range
TJ(ma
VCC
MIN
MAX
–0.3
6
OUTR0–OUTR7, OUTG0–OUTG7
45
OUTB0–OUTB7
35
SIN, SCLK, LAT, BLANK, IREF
–0.3
VCC + 0.3
SOUT
–0.3
VCC + 0.3
OUTR0–OUTR7, OUTG0–OUTG7, OUTB0–OUTB7
–0.3
16
Operation junction temperature
UNIT
V
mA
V
V
150
°C
150
°C
x)
Tstg
(1)
(2)
Storage temperature range
–55
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
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6.3
SBVS129A – MAY 2009 – REVISED JULY 2018
Recommended Operating Conditions
At TA = –40°C to 85°C, unless otherwise noted.
PARAMETER
MIN
NOM
MAX
UNIT
DC CHARACTERISTICS: VCC = 3 V to 5.5 V
VCC
Supply voltage
3
5.5
V
15
V
V
VO
Voltage applied to output
OUTR0–OUTR7, OUTG0–OUTG7,
OUTB0–OUTB7
VIH
High-level input voltage
SIN, SCLK, LAT, BLANK
0.7 × VCC
VCC
VIL
Low-level input voltage
SIN, SCLK, LAT, BLANK
GND
0.3 × VCC
IOH
High-level output current
SOUT
IOL
Low-level output current
SOUT
OUTR0–OUTR7, OUTG0–OUTG7
V
–1
mA
1
mA
35
IOLC
Constant-output sink current
TA
Operating ambient
temperature
–40
85
°C
TJ
Operating junction
temperature
–40
125
°C
35
MHz
OUTB0–OUTB7
mA
26.2
AC CHARACTERISTICS, VCC = 3 V to 5.5 V
fCLK (SCLK)
Data shift clock frequency
SCLK
tWH0
SCLK
10
ns
tWL0
SCLK
10
ns
tWH1
LAT
15
ns
tWH2
BLANK
15
ns
tWL2
BLANK
15
ns
tSU0
Pulse duration
Setup time
tSU1
tH0
Hold time
tH1
SIN – SCLK↑
LAT↑ – SCLK↑
SIN – SCLK↑
LAT↑ – SCLK↑
4
ns
150
ns
3
ns
10
ns
6.4 Thermal Information
TLC5952
THERMAL METRIC
(1)
DAP (TSSOP)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
28.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.6
°C/W
RθJB
Junction-to-board thermal resistance
10.7
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
10.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.6
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
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TLC5952
SBVS129A – MAY 2009 – REVISED JULY 2018
6.5
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Electrical Characteristics
At TJ = –40°C to 150°C, VCC = 3 V to 5.5 V, and VLED = 5 V, unless otherwise noted. Typical values are at TA = 25°C and VCC
= 3.3 V.
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –1 mA at SOUT
VOL
Low-level output voltage
IOL = 1 mA at SOUT
IIN
Input current
VI = VCC or GND at SIN, SCLK, LAT, and BLANK
ICC
Supply current
IOLC
Constant-output current
MIN
TYP
VCC – 0.4
–1
MAX
UNIT
VCC
V
0.4
V
1
μA
SIN, SCLK, LAT = low, BLANK = high,
VOUTRn, -Gn, -Bn = 1 V, BCR, -G, -B = 7Fh,
RIREF = 24 kΩ (IOUTRn/Gn = 2 mA target, IOUTBn = 1.5 mA target)
1
3
SIN, SCLK, LAT = low, BLANK = high,
VOUTRn, -Gn, -Bn = 1 V, BCR, -G, -B = 7Fh,
RIREF = 2.4 kΩ (IOUTRn/Gn = 20 mA target, IOUTBn = 15 mA target)
8
14
SIN, SCLK, LAT = low, BLANK = low, all OUTRn, -Gn, -Bn = on,
VOUTRn, -Gn, -Bn = 1 V, BCR, -G, -B = 7Fh,
RIREF = 2.4 kΩ (IOUTRn/Gn = 20 mA target, IOUTBn = 15 mA target)
12
30
SIN, SCLK, LAT = low, BLANK = low, all OUTRn, -Gn, -Bn = on,
VOUTRn, -Gn, -Bn = 1 V, BCR, -G, -B = 7Fh,
RIREF = 1.5 kΩ (IOUTRn/Gn = 32 mA target, IOUTBn = 24 mA target)
20
50
32
35
mA
At OUTR0–OUTR7 and OUTG0–OUTG7,
All OUTRn, -Gn, -Bn = on, BCR, -G, -B = 7Fh,
VOUTRn, -Gn, -Bn = VOUTfix = 1 V,
RIREF = 1.5 kΩ (IOUTRn/Gn = 32 mA target)
29
At OUTB0–OUTB7,
All OUTRn, -Gn, -Bn = on, BCR, -G, -B = 7Fh,
VOUTRn, -Gn, -Bn = VOUTfix = 1 V,
RIREF = 1.5 kΩ (IOUTBn = 24 mA target)
21.8
mA
24
26.2
IOLKG
Leakage output current
At OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7,
BLANK = high, VOUTRn, -Gn, -Bn = VOUTfix = 15 V, RIREF = 1.5 kΩ
ΔIOLC
Constant-current error (1)
(channel-to-channel in
same color group)
At OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7,
All OUTRn, -Gn, -Bn = on, BCR, -G, -B = 7Fh,
VOUTRn, -Gn, -Bn = VOUTfix = 1 V,
RIREF = 1.5 kΩ (IOUTRn/Gn = 32 mA target, IOUTBn = 24 mA target),
at same color group output
±1%
±3%
ΔIOLC1
Constant current error (2)
(device to device in
same color group)
At OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7,
All OUTRn, -Gn, -Bn = on, BCR, -G, -B = 7Fh,
VOUTRn, -Gn, -Bn = VOUTfix = 1 V,
RIREF = 1.5 kΩ (IOUTRn/Gn = 32 mA target, IOUTBn = 24 mA target),
at same color group output
±3%
±6%
(1)
0.1
μA
The deviation of each output in the same color group from the average of the same color group (OUTR0–OUTR7, OUTG0–OUTG7, or
OUTB0–OUTB7) constant current. The deviation is calculated by the formula (X = R, G, or B; n = 0–7):
D (%) =
IOUTXn
(IOUTX0 + IOUTX1 + ... + IOUTX6 + IOUTX7)
-1
´ 100
8
(2)
The deviation of the constant-current average of each color group from the ideal constant-current value. The deviation is calculated by
the formula (X = R, G, or B):
(IOUTX0 + IOUTX1 +¼+IOUTX7)
- (Ideal Output Current)
8
D (%) =
´ 100
Ideal Output Current
Ideal current is calculated by the following equation for OUTR0–OUTR7 and OUTG0–OUTG7 (X = R, G, or B):
IOUTRn/Gn(IDEAL, mA) = 40 ´
1.20
RIREF (W)
Ideal current is calculated by the following equation for OUTR0–OUTR7 and OUTG0–OUTG7 (X = R, G, or B):
IOUTBn(IDEAL, mA) = 30 ´
6
1.20
RIREF (W)
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Electrical Characteristics (continued)
At TJ = –40°C to 150°C, VCC = 3 V to 5.5 V, and VLED = 5 V, unless otherwise noted. Typical values are at TA = 25°C and VCC
= 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±0.5%
±1%
±1
±3
%/V
ΔIOLC2
Line regulation (3)
At OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7,
All OUTRn, -Gn, -Bn = on, BCR, -G, -B = 7Fh,
VOUTRn, -Gn, -Bn = VOUTfix = 1 V, RIREF = 1.5 kΩ
ΔIOLC3
Load regulation (4)
At OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7,
All OUTRn, -Gn, -Bn = on, BCR, -G, -B = 7Fh,
VOUTRn, -Gn, -Bn = 1 V to 3 V, VOUTfix = 1 V, RIREF = 1.5 kΩ
TTEF
Thermal error flag
threshold
Junction temperature (5)
150
165
180
°C
THYS
Thermal error flag
hysteresis
Junction temperature (5)
5
10
20
°C
VLOD0
All OUTRn, -Gn, -Bn = on, detection voltage select code = 0h
0.25
0.3
0.35
V
VLOD1
All OUTRn, -Gn, -Bn = on, detection voltage select code = 1h
0.5
0.6
0.7
V
All OUTRn, -Gn, -Bn = on, detection voltage select code = 2h
0.8
0.9
1
V
VLOD3
All OUTRn, -Gn, -Bn = on, detection voltage select code = 3h
1.1
1.2
1.3
V
VLSD0
All OUTRn, -Gn, -Bn = on, detection voltage select code = 4h
0.55 × VCC
0.6 × VCC
0.65 × VCC
V
VLSD1
All OUTRn, -Gn, -Bn = on, detection voltage select code = 5h
0.65 × VCC
0.7 × VCC
0.75 × VCC
V
All OUTRn, -Gn, -Bn = on, detection voltage select code = 6h
0.75 × VCC
0.8 × VCC
0.85 × VCC
V
All OUTRn, -Gn, -Bn = on, detection voltage select code = 7h
0.85 × VCC
0.9 × VCC
0.95 × VCC
V
1.17
1.2
1.25
V
VLOD2
VLSD2
LED open detection
threshold
LED short detection
threshold
VLSD3
VIREF
(3)
Reference voltage output RIREF = 1.5 kΩ
Line regulation is calculated by the following equation (X = R, G, or B; n = 0–7):
D (%/V) =
(4)
(IOUTXn at VCC = 3.0 V)
´
100
5.5 V - 3 V
Load regulation is calculated by the following equation (X = R, G, or B; n = 0–7):
D (%/V) =
(5)
(IOUTXn at VCC = 5.5 V) - (IOUTXn at VCC = 3.0 V)
(IOUTXn at VOUTXn = 3 V) - (IOUTXn at VOUTXn = 1 V)
(IOUTXn at VOUTXn = 1 V)
´
100
3V-1V
Not tested; specified by design.
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6.6
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Switching Characteristics
At TA = –40°C to 85°C, VCC = 3 V to 5.5 V, CL = 15 pF, RL = 120 Ω, RIREF = 1.5 kΩ, and VLED = 5 V, unless otherwise noted.
Typical values are at TA = 25°C and VCC = 3.3 V.
PARAMETER
tR0
TEST CONDITIONS
Rise time
tR1
tF0
OUTR0–OUTR7, OUTG0–OUTG7, OUTB0–OUTB7, BCR, -G, -B = 7Fh
SOUT
Fall time
tF1
MIN
SOUT
OUTR0–OUTR7, OUTG0–OUTG7, OUTB0–OUTB7, BCR, -G, -B = 7Fh
TYP MAX UNIT
6
15
ns
10
30
ns
6
15
ns
10
30
ns
8
20
ns
tD0
SCLK↑ to SOUT
tD1
LAT↑ to OUTR0 on-off, BCR, -G, -B = 7Fh
22
45
ns
tD2
BLANK↓↑ to OUTR0 on-off, BCR, -G, -B = 7Fh
15
30
ns
tD3
OUTRn on to OUTGn on, OUTGn on to OUTBn on,
OUTBn on to OUTRn + 1 on, BCR, -G, -B = 7Fh
3
6
ns
tD4
OUTRn off to OUTGn off, OUTGn off to OUTBn off,
OUTBn off to OUTRn + 1 off, BCR, -G, -B = 7Fh
3
6
ns
tD5
LAT↑ to IOUTn changing by global brightness control (BC data are
0Ch–72h or 72h–0Ch)
20
50
ns
5
ns
Propagation delay
time (1)
tON_ERR
(1)
(2)
Output on-time error (2)
On-off latched data = 1, BCR, -G, -B = 7Fh, 20 ns BLANK low level oneshot pulse input
–11
Propagation delay, tD3 (OUTRn on to OUTGn on, OUTGn on to OUTBn on, OUTBn on to OUTRn + 1 on) is calculated by the formula:
tD3 (ns) = (the propagation delay between OUTR0 to OUTB7 = on) / 23
tD4 (OUTRn to OUTGn = off, OUTGn to OUTBn = off, OUTBn to OUTRn + 1 = off) is calculated by the formula:
tD4 (ns) = (the propagation delay between OUTR0 to OUTB7 = off) / 23
Output on-time error is calculated by the formula: tON_ERR (ns) = tOUT_ON – BLANK low-level pulse duration. tOUT_ON is the actual on-time
of the constant current output.
tWH0, tWL0, tWH1, tWH2, tWL2:
VCC
INPUT
50%
GND
tWH
tWL
tSU0, tSU1, tH0, tH1:
VCC
CLOCK
(1)
INPUT
50%
GND
tSU
tH
VCC
DATA/CONTROL
(1)
INPUT
50%
GND
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 1. Input Timing
8
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tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5:
VCC
(1)
INPUT
50%
GND
tD
VOH or VOUTRn/Gn/BnH
90%
OUTPUT
50%
10%
VOL or VOUTRn/Gn/BnL
tR or tF
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 2. Output Timing
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Output On/Off Data Write
SIN
0A
On
Low
B7B
On
R7B
On
G7B
On
Control Data Write
B6B
On
R6B
On
G6B
On
B0B
On
R0B
On
G0B
On
High
23
Cont
22
Cont
1
2
3
21
Cont
0
Cont
1
Cont
2
Cont
fCLK
(SCLK)
tSU0
tH0
tWH0
tSU1
SCLK
1
2
3
4
5
6
23
24
25
tWL0
tH1
23
24
25
tWH1
LAT
tWL2
tWH2
BLANK
LOD
G0A
Common Shift Register
Bit 23 (Internal)
LOD
B7A
B7B
On
G7B
On
R7B
On
B6B
On
G6B
On
B0B
On
G0B
On
R0B
On
LOD
R0B
High
23
Cont
22
Cont
2
Cont
1
Cont
0
Cont
Low
B7B
On
G7B
On
R7B
On
B6B
On
R1B
On
B0B
On
G0B
On
LOD
G0B
LOD
R0B
High
23
Cont
3
Cont
2
Cont
1
Cont
LOD
R7A
LOD
B6A
LOD
G6A
LOD
R6A
LOD
B5A
LOD
R0A
Low
B7B
On
LOD
B7B
LOD
G7B
LOD
R7B
LOD
B6B
LOD
G0B
LOD
R0B
23
Cont
¼
LOD
G7A
¼
Common Shift Register
Bit 1 (Internal)
Low
¼
LOD
R0A
¼
Common Shift Register
Bit 0 (Internal)
On/Off Data Latch
(Internal)
Previous Data
Control Data Latch
(Internal)
Current Data
Previous Data
Current Data
tD0
SOUT
(Common Shift Register Bit 24)
TEF
A
tR0/tF0
LOD
G7A
LOD
B7A
LOD
R7A
tD2
OUTR0
OUTG0
(VOUTRn/Gn/BnH) tF1
ON
(VOUTRn/Gn/BnL)
LOD
R0A
LOD
G0A
TEF
B
Low
LOD
B7B
LOD
G7B
LOD
R7B
LOD
G0B
LOD
R0B
tD1
High
tD5
tR1
RED outputs are turned off by output on/off data.
tD4
tD3
Output current
is changed
by BC data.
tD3
tD4
ON
OFF
OUTR1
LOD
R6A
ON
OFF
OUTB0
LOD
G6A
tD2
OFF
OFF
LOD
B6A
tD4
tD3
ON
¼
¼
¼
¼
OFF
OUTR7
ON
OFF
OUTG7
ON
OFF
OUTB7
ON
Figure 3. Timing Diagram
10
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6.7 Typical Characteristics
At TA = 25°C and VCC = 3.3 V, unless otherwise noted.
100
RIREF, Reference Resistor (kW)
RIREF, Reference Resistor (kW)
100
24000
9600
10
4800
3200
2400
1920
24000
18000
10
3600
2400
0
5
10
15
25
20
1440
1
0
35
30
5
Output Current (mA)
15
25
20
30
35
Figure 5. Reference Resistor vs Output Current (Blue Color
Group)
40
6000
Thermal Pad Soldered
TA = +25°C, VCC = 3.3 V, BCR/G = 7Fh
35
5000
Output Current (mA)
Power Dissipation Rate (mW)
10
Output Current (mA)
Figure 4. Reference Resistor vs Output Current (Red and
Green Color Group)
4000
3000
Thermal Not Pad Soldered
2000
1000
IO = 35 mA
IO = 30 mA
30
25
IO = 20 mA
20
15
IO = 10 mA
10
IO = 2 mA
IO = 5 mA
5
0
0
-40
-20
0
20
40
60
0
100
80
0.5
Figure 6. Power Dissipation Rate
40
40
IO = 26.2 mA
25
20
IO = 22.5 mA
15
IO = 15 mA
IO = 7.5 mA
IO = 3.75 mA
IO = 1.5 mA
10
2.0
2.5
3.0
IO = 35 mA
TA = +25°C, VCC = 5 V, BCR/G = 7Fh
35
5
Output Current (mA)
30
1.5
Figure 7. Output Current vs Output Voltage (Red and Green
Color Group)
TA = +25°C
VCC = 3.3 V
BCB = 7Fh
35
1.0
Output Voltage (V)
Ambient Temperature (°C)
Output Current (mA)
1374
1800
1600 1371
1
7200
IO = 30 mA
30
25
IO = 20 mA
20
15
IO = 10 mA
10
IO = 2 mA
IO = 5 mA
5
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
Output Voltage (V)
Output Voltage (V)
Figure 8. Output Current vs Output Voltage (Blue Color
Group)
Figure 9. Output Current vs Output Voltage (Red and Green
Color Group)
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Typical Characteristics (continued)
At TA = 25°C and VCC = 3.3 V, unless otherwise noted.
40
30
IO = 26.2 mA
25
20
IO = 22.5 mA
IO = 15 mA
15
10
IO = 7.5 mA
IO = 3.75 mA
IO = 1.5 mA
IOLCMax = 35 mA
VCC = 3.3 V
BCR/G = 7Fh
39
38
Output Current (mA)
35
Output Current (mA)
40
TA = +25°C
VCC = 5 V
BCB = 7Fh
37
36
35
34
33
TA = -40°C
TA = +25°C
TA = +85°C
32
5
31
0
30
0
1.0
1.5
2.0
2.5
0
3.0
2.0
2.5
3.0
Figure 10. Output Current vs Output Voltage (Blue Color
Group)
Figure 11. Output Current vs Output Voltage (Red and
Green Color Group)
40
IOLCMax = 26.2 mA
VCC = 3.3 V
BCB = 7Fh
IOLCMax = 35 mA
VCC = 5 V
BCR/G = 7Fh
39
38
Output Current (mA)
29
28
27
26
25
24
TA = -40°C
TA = +25°C
TA = +85°C
23
22
37
36
35
34
33
TA = -40°C
TA = +25°C
TA = +85°C
32
31
21
30
0
0.5
1.0
1.5
2.0
2.5
0
3.0
0.5
1.5
1.0
2.0
2.5
3.0
Output Voltage (V)
Output Voltage (V)
Figure 12. Output Current vs Output Voltage (Blue Color
Group)
Figure 13. Output Current vs Output Voltage (Red and
Green Color Group)
31
4
IOLCMax = 26.2 mA
VCC = 5 V
BCB = 7Fh
30
29
TA = +25°C
BCR = 7Fh
3
2
28
27
DIOLC (%)
Output Current (mA)
1.5
1.0
Output Voltage (V)
30
26
25
24
22
1
0
-1
-2
TA = -40°C
TA = +25°C
TA = +85°C
23
VCC = 3.3 V
-3
VCC = 5 V
-4
21
0
12
0.5
Output Voltage (V)
31
Output Current (mA)
0.5
0.5
1.0
1.5
2.0
2.5
3.0
0
5
10
15
20
25
30
35
Output Voltage (V)
Output Current (mA)
Figure 14. Output Current vs Output Voltage (Blue Color
Group)
Figure 15. Constant-Current Error vs Output Current
(Channel-to-Channel in Red Color Group)
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Typical Characteristics (continued)
At TA = 25°C and VCC = 3.3 V, unless otherwise noted.
4
3
2
2
1
1
0
-1
-2
0
-1
-2
VCC = 3.3 V
-3
VCC = 3.3 V
-3
VCC = 5 V
-4
VCC = 5 V
-4
0
5
10
15
20
25
0
35
30
5
15
10
20
30
25
Output Current (mA)
Output Current (mA)
Figure 16. Constant-Current Error vs Output Current
(Channel-to-Channel in Green Color Group)
Figure 17. Constant-Current Error vs Output Current
(Channel-to-Channel in Blue Color Group)
4
4
3
IOLCMax = 35 mA
BCR = 7Fh
IOLCMax = 35 mA
BCG = 7Fh
3
2
2
1
1
DIOLC (%)
DIOLC (%)
TA = +25°C
BCB = 7Fh
3
DIOLC (%)
DIOLC (%)
4
TA = +25°C
BCG = 7Fh
0
-1
-2
0
-1
-2
VCC = 3.3 V
-3
VCC = 3.3 V
-3
VCC = 5 V
-4
VCC = 5 V
-4
-40
-20
0
20
40
60
80
100
-40
20
0
-20
40
60
100
80
Ambient Temperature (°C)
Ambient Temperature (°C)
Figure 18. Constant-Current Error vs Ambient Temperature
(Channel-to-Channel in Red Color Group)
Figure 19. Constant-Current Error vs Ambient Temperature
(Channel-to-Channel in Green Color Group)
4
3
40
IOLCMax = 26.2 mA
BCB = 7Fh
Output Current (mA)
2
DIOLC (%)
IO = 35 mA
(R = 1.37 kW)
TA = +25°C
35
1
0
-1
-2
VCC = 3.3 V
-3
VCC = 5 V
-4
VCC = 3.3 V
30
VCC = 5 V
IO = 20 mA
(R = 2.4 kW)
25
20
IO = 10 mA
(R = 4.8 kW)
15
10
5
IO = 2 mA, (R = 24 kW)
0
-40
-20
0
20
40
60
80
100
0
16
32
48
64
80
96
112
128
Ambient Temperature (°C)
Brightness Control Data (dec)
Figure 20. Constant-Current Error vs Ambient Temperature
(Channel-to-Channel in Blue Color Group)
Figure 21. Global Brightness Control Linearity (Red and
Green Color Group)
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Typical Characteristics (continued)
At TA = 25°C and VCC = 3.3 V, unless otherwise noted.
30
TA = +25°C
IO = 26.6 mA
(R = 1.371 kW)
35
VCC = 3.3 V
Output Current (mA)
30
VCC = 5 V
IO = 15 mA
(R = 2.4 kW)
25
20
IO = 7.5 mA
(R = 4.8 kW)
20
15
15
10
IO = 1.5 mA
(R = 24 kW)
10
TA = +25°C
SIN = 17.5 MHz
SCLK = 35 MHz
BCR/G/B = 7Fh
All Group Output = On
25
ICC (mA)
40
5
5
VCC = 3.3 V
VCC = 5 V
0
0
0
16
32
48
64
80
96
112
128
0
5
10
15
20
25
35
30
Brightness Control Data (dec)
OUTRn/Gn Output Current (mA)
Figure 22. Global Brightness Control Linearity (Blue Color
Group)
Figure 23. Supply Current vs Output Current (Red and
Green Color Group)
25
ICC (mA)
20
35
TA = +25°C
SIN = 17.5 MHz
SCLK = 35 MHz
BCR/G/B = 7Fh
All Group Output = On
30
R = 1.37 kW, IO (Rn/Gn) = 35 mA
IO (Bn) = 26.2 mA
15
10
5
VCC = 3.3 V
R = 2.4 kW, IO (Rn/Gn) = 20 mA, IO (Bn) = 15 mA
15
SIN = 17.5 MHz, SCLK = 35 MHz,
BCR/G/B = 7Fh, All Group Output = On
5
VCC = 5 V
R = 24 kW, IO (Rn/Gn) = 2 mA, IO (Bn) = 1.5 mA
0
0
5
10
VCC = 5 V
20
10
0
VCC = 3.3 V
25
ICC (mA)
30
15
20
25
30
-40
-20
0
20
40
60
80
100
OUTBn Output Current (mA)
Ambient Temperature (°C)
Figure 24. Supply Current vs Output Current (Blue Color
Group)
Figure 25. Supply Current vs Ambient Temperature
CH1 (2 V/div)
CH2 (2 V/div)
CH3 (2 V/div)
CH1-BLANK
(15 ns)
CH2-OUTR0
(BLANK = 15 ns)
IOLCMax (R) = 32 mA
IOLCMAX (B) = 24 mA
RIREF = 1.5 kW, TA = +25°C
RL = 120 W, CL = 15 pF
VCC = 3.3 V, VLED = 5 V
CH3-OUTB0
(BLANK = 15 ns)
Time (12.5 ns/div)
Figure 26. Constant-Current Output-Voltage Waveform
14
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7 Parameter Measurement Information
7.1
Pin Equivalent Input and Output Schematic Diagrams
VCC
VCC
INPUT
SOUT
GND
GND
Figure 27. SIN, SCLK, LAT, BLANK
Figure 28. SOUT
OUTn
GND
Figure 29. OUTR0, -G0, -B0 Through OUTR7, -G7, -B7
7.2 Test Circuits
RL
VCC
VCC
OUTXn
IREF
RIREF
VCC
(2)
(1)
VLED
GND
GND
Figure 30. Rise Time and Fall Time Test Circuit for OUTRn,
-Gn, -Bn
IREF
(1)
OUTR0
(1)
OUTXn
¼
RIREF
CL
Figure 31. Rise Time and Fall Time Test Circuit for SOUT
¼
VCC
VCC
SOUT
VCC
CL
GND OUTB7
VOUTfix
VOUTRn/Gn/Bn
X = R, G, or B; n = 0–7.
Figure 32. Constant-Current Test Circuit for OUTRn, -Gn, -Bn
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8 Detailed Description
8.1 Overview
The TLC5952 device is a 24-channel, constant- current sink driver. Each channel can be turned on or off with
internal register data. The output channels are grouped into three groups of eight channels each. Each channel
group has a 128-step global brightness control (BC) function. Both on-off data and BC are writable via a serial
interface. The maximum current value of all 24 channels is set by a single external resistor.
8.2 Functional Block Diagram
24-Bit LOD or 24-Bit LSD Data
VCC
VCC
1-Bit TEF Data
MSB
LSB
SIN
Common Shift Register
0
SOUT
24
Bit 24
SCLK
24
LSB
MSB
24
Output On/Off Data Latch
0
23
24
LSB
MSB
Control Data Latch
(Three Groups, 7-Bit Global Brightness Control
LOD/LSD Voltage and Detection Type Select)
LAT
0
24
23
3
LOD/LSD
Holder
BLANK
21
On/Off Control with Output Delay
24
TEF
Holder
Thermal
Detector
7-Bit Global
Brightness
Control
7-Bit Global
Brightness
Control
7
IREF
Reference
Current
Control
16
16 Channels
Constant-Current Sink Driver
¼
GND
16
Detection
Voltage
7
¼
7-Bit Global
Brightness
Control
8
24
7
8 Channels
Constant-Current
Sink Driver
¼
LED Open Detection (LOD)/LED Short Detection (LSD)
¼
¼
¼
OUTR0 OUTR7
OUTG0 OUTG7
OUTB0 OUTB7
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8.3 Feature Description
8.3.1 Maximum Constant-Sink-Current Value
The maximum output current per channel, IOLCMax, is programmed by a single resistor, RIREF, which is placed
between the IREF and GND pins. The voltage on IREF is set by an internal band-gap VIREF, with a typical value
of 1.20 V. The maximum channel current is equivalent to the current flowing through RIREF multiplied by a factor
of 40 for OUTRn, -Gn and 30 for OUTBn. The maximum output current per channel can be calculated by
Equation 1.
RIREF (kW) =
=
VIREF (V)
´ 40 (for OUTRn/Gn)
IOLCMax (mA)
VIREF (V)
´ 30 (for OUTBn)
IOLCMax (mA)
where:
•
•
VIREF = the internal reference voltage on IREF (1.20 V, typical)
IOLCMax = 2 mA to 35 mA at OUTRn, -Gn and 1.5 mA to 26.2 mA at OUTBn
(1)
IOLCMax is the largest current for each output. Each output sinks the IOLCMax current when it is turned on and the
global brightness control data are set to the maximum value of 7Fh (127d). Each output sink current can be
reduced by lowering the output global brightness control (BC) value.
RIREF must be between 1.37 kΩ and 24 kΩ to hold IOLCMax between 35 mA (typ) and 2 mA (typ) for OUTRn, -Gn
and between 26.2 mA (typ) and 1.5 mA (typ) for OUTBn. Otherwise, the output may be unstable. Output currents
lower than 2 mA (or 1.5 mA for OUTBn) can be achieved by setting IOLCMax to 2 mA or higher and then using
global brightness control to lower the output current.
Table 1 shows the characteristics of the constant-current sink versus the external resistor, RIREF.
Table 1. Maximum Constant-Current Output Versus
External Resistor Value
IOLCMax (mA)
OUTRn, OUTGn
OUTBn
35
26.28
RIREF (kΩ)
1.37
30
22.5
1.6
25
18.75
1.92
20
15
2.4
15
11.25
3.2
10
7.5
4.8
5
3.75
9.6
2
1.5
24
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8.3.2 Global Brightness Control (BC) Function: Sink-Current Control
The TLC5952 is able to adjust the output current of each of the three color groups OUTR0–OUTR7,
OUTG0–OUTG7, and OUTB0–OUTB7. This function is called global brightness control (BC). The BC function
allows users to adjust the global brightness of LEDs connected to the three output groups (OUTR0–OUTR7,
OUTG0–OUTG7, and OUTB0–OUTB7). All color group output currents can be adjusted in 128 steps from 0% to
100% of the maximum output current, IOLCMax. The brightness control data are entered into the TLC5952 via the
serial interface. When the BC data change, the output current also changes immediately. When the device is
powered on, the data in the common shift register and the control data latch are not set to any default values.
Therefore, BC data must be written to the control data latch before turning on the constant-current output.
Equation 2 determines the output sink current for each color group. Table 2 summarizes the BC data versus
current ratio and set current value.
IOUT (mA) = IOLCMax (mA) ´
BCR/G/B
127d
where:
•
•
IOLCMax = the maximum channel current for each channel determined by R IREF
BCR, -G, -B = the global brightness control value in the control data latch for each output color group
(2)
Table 2. BC Data vs Current Ratio and Set-Current Value
BC DATA
(Binary)
BC DATA
(Decimal)
BC DATA
(Hex)
RATIO OF OUTPUT
CURRENT TO
IOLCMax
(mA, Typical)
000 0000
0
00
0
0
0
000 0001
1
01
0.8
0.28
0.02
000 0010
2
02
1.6
0.55
0.03
...
...
...
...
...
...
111 1101
125
7D
98.4
34.45
1.97
111 1110
126
7E
99.2
34.72
1.98
111 1111
127
7F
100
35
2
IOUT, mA
(IOLCMax = 35 mA,
Typical)
IOUT, mA
(IOLCMax = 2 mA,
Typical)
8.3.3 Constant-Current Output On-Off Control
When BLANK is low, each output is controlled by the data in the output on-off data latch. When data
corresponding to an output are equal to 1, the output turns on; when the data corresponding to an output are
equal to 0, the output turns off. When BLANK is high, all outputs are forced off.
When the device is powered on, the data in the output on-off data latch are not set to any default values.
Therefore, on-off data must be written to the output on-off data latch before turning on the constant-current
output and pulling BLANK low.
If there are any OUTRn, -Gn, -Bn outputs not connected to an LED, including open for short-to-ground failures,
the on-off data corresponding to the unconnected output should be set to 0 before the LED is turned on.
Otherwise, the VCC supply current (ICC) increases while the LEDs are on. A truth table for the on-off control data
is shown in Table 3.
Table 3. On-Off Control-Data Truth Table
18
ON-OFF CONTROL DATA
CONSTANT-CURRENT OUTPUT
STATUS
0
Off
1
On
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8.4 Device Functional Modes
8.4.1 LOD, LSD, and TEF Operation
0A
On
SIN
23B
On
Low
22B
On
21B
On
20B
On
3B
On
2B
On
1B
On
0B
On
Low
23C
On
22C
On
21C
On
20C
On
1
2
3
4
5
18C
On
19C
On
17C
On
16C
On
SCLK
1
2
3
4
5
22
23
24
25
6
7
The data in the common shift register are copied to the control data latch at the rising edge of LAT.
SID data (LOD or LSD and TEF) are loaded into the common shift register at the same time.
LAT
BLANK
SOUT
(Common Shift Register)
(Bit 24)
TEF
A
LOD
G7A
LOD
B7A
LOD
B6A
LOD
R7A
LOD
G6A
LOD
B0A
LOD
R1A
LOD
R0A
LOD
G0A
TEF
B
Low
OFF
OUTXn
(LSD Voltage)
LOD
G7B
LOD
B7B
LOD
B6B
LOD
R7B
LOD
G6B
LOD
R6B
LOD
B5B
LOD
G5B
SID data are copied to the 25-bit common shift register at the
rising edge of LAT with the common shift register MSB low.
ON
ON
(LOD Voltage)
0V
LOD/LSD Data
For OUTXn
(Internal)
'0'
'0'
Figure 33. LOD, LSD, and TEF Operation (No LED Error)
SIN
0A
On
23B
On
Low
22B
On
21B
On
20B
On
3B
On
2B
On
1B
On
0B
On
Low
23C
On
22C
On
21C
On
20C
On
1
2
3
4
5
19C
On
18C
On
16C
On
17C
On
SCLK
1
2
3
4
5
22
23
24
25
6
7
The data in the common shift register are copied to the control data latch at the rising edge of LAT.
SID data (LOD or LSD and TEF) are loaded into the common shift register at the same time.
LAT
BLANK
SOUT
(Common Shift Register)
(Bit 24)
TEF
A
LOD
B7A
LOD
G7A
LOD
R7A
LOD
B6A
LOD
G6A
LOD
R1A
LOD
B0A
LOD
G0A
LOD
R0A
TEF
B
Low
LOD
B7B
LOD
G7B
LOD
R7B
LOD
B6B
LOD
G6B
LOD
R6B
LOD
B5B
LOD
G5B
SID data are copied to the 25-bit common shift register at the
rising edge of LAT with the common shift register MSB low.
OFF
(LSD Voltage)
OUTXn
ON
(LOD Voltage)
ON
0V
LED is Open At This Time
LOD Circuit Output
For OUTXn
(Internal)
'1' (LED is Open)
'1' (LED is Open)
'0' (LED is Not Open)
LOD output becomes '0' when the output is off.
'1' (LED is Open)
LOD Data In LOD/LSD Holder
(Internal)
LOD data are immediately updated with the
LOD circuit output when BLANK is low.
'1' (LED is Open)
LOD data are not updated while BLANK is high.
Therefore, LOD data in previous display periods
can be read even if BLANK is high.
Figure 34. LOD, LSD, and TEF Operation (LED-Open Error)
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Device Functional Modes (continued)
0A
On
SIN
23B
On
Low
22B
On
21B
On
20B
On
3B
On
2B
On
1B
On
0B
On
Low
23C
On
22C
On
21C
On
20C
On
1
2
3
4
5
18C
On
19C
On
17C
On
16C
On
SCLK
1
2
3
4
5
22
23
24
25
6
7
The data in the common shift register are copied to the control data latch at the rising edge of LAT.
SID data (LOD or LSD and TEF) are loaded into the common shift register at the same time.
LAT
BLANK
SOUT
(Common Shift Register)
(Bit 24)
TEF
A
LOD
B7A
LOD
G7A
LOD
G6A
LOD
B6A
LOD
R7A
LOD
B0A
LOD
R1A
LOD
R0A
LOD
G0A
TEF
B
Low
LOD
G7B
LOD
B7B
LOD
B6B
LOD
R7B
LOD
G6B
LOD
R6B
LOD
B5B
LOD
G5B
SID data are copied to the 25-bit common shift register at the
rising edge of LAT with the common shift register MSB low.
OFF
OUTXn
ON
(LSD Voltage)
ON
0V
LED is Shorted At This Time
'1' (LED is Shorted)
'1' (LED is Shorted)
LSD Circuit Output
For OUTXn
(Internal)
'0' (LED is Not Shorted)
LSD output becomes '0' when the output is off.
'1' (LED is Shorted)
'1' (LED is Shorted)
LSD Data In LOD/LSD Holder
(Internal)
LSD data are immediately updated with the
LSD circuit output when BLANK is low.
LSD data are not updated while BLANK is high.
Therefore, LSD data in previous display periods
can be read even if BLANK is high.
Figure 35. LOD, LSD, and TEF Operation (LED-Short Error)
SIN
0A
On
Low
23B
On
22B
On
21B
On
20B
On
3B
On
2B
On
1B
On
0B
On
Low
23C
On
22C
On
21C
On
20C
On
1
2
3
4
5
19C
On
18C
On
17C
On
16C
On
SCLK
1
2
3
4
5
22
23
24
25
6
7
The data in the common shift register are copied to the control data latch at the rising edge of LAT.
SID data (LOD or LSD and TEF) are loaded into the common shift register at the same time.
LAT
BLANK
SOUT
(Common Shift Register)
(Bit 24)
TEF
A
LOD
B7A
LOD
G7A
LOD
R7A
LOD
B6A
LOD
G6A
LOD
R1A
LOD
B0A
LOD
G0A
LOD
R0A
TEF
B
Low
LOD
B7B
LOD
G7B
LOD
R7B
LOD
B6B
LOD
G6B
LOD
R6B
LOD
B5B
LOD
G5B
SID data are copied to the 25-bit common shift register at the
rising edge of LAT with the common shift register MSB low.
'1' (Temperature is Higher Than TTEF)
Thermal Detector Output
(Internal)
'0' (Temperature is Normal)
TEF Data In TEF Holder
(Internal)
'0' (Temperature is Normal)
'1' (Temperature is Higher Than TTEF)
The output becomes '0' because the
temperature drops below TTEF - THYS
when the output is off.
'1' (Temperature is Higher Than TTEF)
TEF data are immediately
updated when BLANK is low.
'1' (Temperature is Higher Than TTEF)
TEF data are set to '1' when the junction temperature exceeds TTEF. The TEF data are held in
the TEF holder until the SID data are loaded into the common shift register. The TEF data are reset to '0'
at the rising edge of LAT if the junction temperature is below TTEF - THYS.
Figure 36. LOD, LSD, and TEF Operation (Thermal Error)
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Device Functional Modes (continued)
8.4.2 Register and Data Latch Configuration
The TLC5952 device has two writable data latches: the output on-off data latch and the control data latch. Both
data latches are 24 bits in length. If the common shift register MSB is 0, the least significant 24 bits of data from
the 25-bit common shift register are latched into the output on-off data latch. If the MSB is 1, the data are latched
into the control data latch. Figure 37 shows the common shift register and the control data latch configuration.
Common Shift Register (25 Bits)
MSB
24
SOUT
Latch
Select
Bit
23
22
21
20
19
Common Common Common Common Common
Data
Data
Data
Data
Data
Bit 21
Bit 20
Bit 23
Bit 19
Bit 22
4
5
¼
3
2
1
Common Common Common Common Common
Data
Data
Data
Data
Data
Bit 3
Bit 1
Bit 4
Bit 2
Bit 5
LSB
0
Common
Data
Bit 0
SIN
SCK
24
24
Output On/Off Data Latch (24 Bits)
MSB
23
22
21
20
19
OUTB7
On
OUTG7
On
OUTR7
On
OUTB6
On
OUTG6
On
¼
5
4
3
2
1
LSB
0
OUTB1
On
OUTG1
On
OUTR1
On
OUTB0
On
OUTG0
On
OUTR0
On
7
6
The latch pulse comes
from LAT when the
MSB of the common
shift register is ‘0’.
24
To Output On/Off Control Circuit
24
Control Data Latch (24 Bits)
MSB
23
22
21
Detection Detection Detection OUTB0-7
Voltage
Voltage
Voltage
Bright
Select 2 Select 1 Select 0
Bit 6
¼
13
OUTB0-7 OUTG0-7
Bright
Bright
Bit 0
Bit 6
7
3
To LSD/LOD
Circuit
14
20
To Global Brightness
Control Circuit
for OUTB0-OUTB7
¼
OUTG0-7 OUTR0-7
Bright
Bright
Bit 0
Bit 6
7
To Global Brightness
Control Circuit
for OUTG0-OUTG7
LSB
0
¼
OUTR0-7
Bright
Bit 0
The latch pulse comes
from LAT when the
MSB of the common
shift register is ‘1’.
7
To Global Brightness
Control Circuit
for OUTR0-OUTR7
Figure 37. Grayscale Shift Register and Data-Latch Configuration
8.4.2.1 Output On-Off Data Latch
The output on-off data latch is 24 bits long. This latch is used to turn each output current sink (OUTRn, -Gn, -Bn)
on or off. When the MSB of the common shift register is set to 0, the lower 24 bits are written to the output on-off
data latch on the rising edge of LAT. If the output on-off data latch bit corresponding to an output is 0, the output
is turned off; if the bit is a 1, the output is turned on.
When the device is powered on, the data in the output on-off data latch are not set to any default value.
Therefore, the on-off control data should be written to the data latch before the constant-current outputs are
turned on.
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Device Functional Modes (continued)
8.4.2.2 Control-Data Latch
The control data latch is 24 bits long and is used to adjust the LED current for each color group (OUTR0-OUTR7,
OUTG0-OUTG7, and OUTB0-OUTB7). The LED current for each group can be adjusted between 0% and 100%
of IOLCMAX in 128 steps (7-bit resolution). This data latch is also used to select the error detection type, LED open
detection (LOD) or LED short detection (LSD), and the threshold voltage. When the MSB of the common shift
register is set to 1, the lower 24 bits are written to the control data latch on the rising edge of LAT. Table 4 shows
the control data latch bit assignment.
When the device is powered on, the data in the control data latch are not set to a default value. Therefore, the
control data latch data should be written to the latch before the constant-current outputs are turned on.
Table 4. Data Bit Assignment
BITS
22
DESCRIPTION
6–0
Global brightness control data for RED group (OUTR0-OUTR7, data = 00h to 7Fh)
13–7
Global brightness control data for GREEN group (OUTG0-OUTG7, data = 00h to 7Fh)
20–14
Global brightness control data for BLUE group (OUTB0-OUTB7, data = 00h to 7Fh)
23–21
Detection voltage and type select (data = 0h to 7h)
0 = LED open detection with 0.3 V (typ) threshold
1 = LED open detection with 0.6 V (typ) threshold
2 = LED open detection with 0.9 V (typ) threshold
3 = LED open detection with 1.2 V (typ) threshold
4 = LED short detection with VCC × 60% (typ) threshold
5 = LED short detection with VCC × 70% (typ) threshold
6 = LED short detection with VCC × 80% (typ) threshold
7 = LED short detection with VCC × 90% (typ) threshold
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Figure 38 shows the operation to write data into the common shift register and control data latch.
Output On/Off Data Write
SIN
0A
On
Low
B7B
On
G7B
On
1
2
3
R7B
On
Control Data Write
B6B
On
G6B
On
5
6
R6B
On
B0B
On
R0B
On
G0B
On
High
23
Cont
22
Cont
1
2
3
21
Cont
1
Cont
2
Cont
0
Cont
SCLK
4
23
24
25
23
24
25
LAT
The data in the common shift register are copied
to the on/off data latch at the rising edge of LAT.
BLANK
LOD
G0A
Common Shift Register
Bit 23 (Internal)
LOD
B7A
B7B
On
G7B
On
R7B
On
B6B
On
G6B
On
B0B
On
G0B
On
R0B
On
LOD
R0B
High
23
Cont
22
Cont
2
Cont
1
Cont
0
Cont
Low
B7B
On
G7B
On
R7B
On
B6B
On
R1B
On
B0B
On
G0B
On
LOD
G0B
LOD
R0B
High
23
Cont
3
Cont
2
Cont
1
Cont
LOD
R7A
LOD
B6A
LOD
G6A
LOD
R6A
LOD
B5A
LOD
R0A
Low
B7B
On
LOD
B7B
LOD
G7B
LOD
R7B
LOD
B6B
LOD
G0B
LOD
R0B
23
Cont
¼
LOD
G7A
¼
Common Shift Register
Bit 1 (Internal)
Low
¼
LOD
R0A
¼
Common Shift Register
Bit 0 (Internal)
On/Off Data Latch
(Internal)
Previous Data
Control Data Latch
(Internal)
Previous Data
SOUT
(Common Shift Register Bit 24)
TEF
A
LOD
B7A
LOD
G7A
LOD
B6A
LOD
R7A
LOD
G6A
LOD
R6A
LOD
G0A
LOD
R0A
Current Data
Current Data
Low
OFF
(VOUTRn/Gn/BnH)
ON
(VOUTRn/Gn/BnL)
TEF
B
LOD
B7B
LOD
G7B
LOD
R7B
LOD
G0B
LOD
R0B
RED outputs are turned off by the output on/off data.
Output current
is changed
by BC data.
OFF
OUTG0
High
SID data are copied to the 25-bit
common shift register at the
rising edge of LAT.
The LOD/LSD result of each LED comes from SOUT.
OUTR0
The data in the common shift register are copied
to the control data latch at the rising edge of LAT.
ON
OFF
OUTB0
ON
OFF
OUTR1
ON
¼
¼
¼
¼
OFF
OUTR7
ON
OFF
OUTG7
ON
OFF
OUTB7
ON
Figure 38. Data Write Operation
8.4.2.3 Status Information Data (SID)
The 25-bit word status information data (SID) contains the status of the LED open detection (LOD) or LED short
detection (LSD), and thermal error flag (TEF). When the MSB of the common shift register is set to 0, the SID
overwrites the common shift register data at the rising edge of LAT after the data in the common shift register are
copied to the output on-off data latch. If the common shift register MSB is 1, the SID data are not copied to the
common shift register.
After being copied into the common shift register, new SID data are not available until new data are written into
the common shift register. If new data are not written, the LAT signal is ignored. To recheck SID data without
changing the constant-current output on-off data, reprogram the common shift register with the same data that
are currently programmed into the output on-off data latch. When LAT goes high, the output on-off data do not
change, but new SID data are loaded into the common shift register. LOD, LSD, and TEF are shifted out of
SOUT with each rising edge of SCLK.
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LOD/LSD Holder (24 Bits) and TEF Holder (1 Bit)
Thermal
Error
Flag
LOD or
LSD for
OUTB7
LOD or
LSD for
OUTG7
LOD or
LSD for
OUTR7
LOD or
LSD for
OUTB6
LOD or
LSD for
OUTG6
¼
LOD or
LSD for
OUTB1
LOD or
LSD for
OUTG1
LOD or
LSD for
OUTR1
LOD or
LSD for
OUTB0
LOD or
LSD for
OUTG0
LOD or
LSD for
OUTR0
SID are loaded to the
common shift register
at the rising edge of LAT
when the common shift
register MSB is ‘0’.
SIN
SOUT
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
¼
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCK
MSB
LSB
Common Shift Register (25 Bits)
Figure 39. SID Load Assignment
8.4.2.4 LED-Open Detection (LOD), LED-Short Detection (LSD), And Thermal Error Flag (TEF)
LOD detects a fault caused by an LED open circuit or a short from OUTRn, -Gn, -Bn to ground by comparing the
OUTRn, -Gn, -Bn voltage to the LOD detection threshold voltage level set in the control data latch (Table 4). If
the OUTRn, -Gn, -Bn voltage is lower than the programmed voltage, that output LOD bit is set to 1 to indicate an
open LED. Otherwise, the LOD bit is set to 0. LOD data are only valid for outputs programmed to be on. LOD
data for outputs programmed to be off are always 0.
LSD data detects a fault caused by a shorted LED by comparing the OUTRn, -Gn, -Bn voltage to the LSD
detection threshold voltage level set in the control data latch (Table 4). If the OUTRn, -Gn, -Bn voltage is higher
than the programmed voltage, that output LOD bit is set to 1 to indicate a shorted LED. Otherwise, the LSD bit is
set to 0. LSD data are only valid for outputs programmed to be on. LSD data for outputs programmed to be off
are always 0.
LOD and LSD data are not valid until 1 μs after the falling edge of BLANK. Therefore, BLANK must be low for at
least 1 μs before going high. At the rising edge of BLANK, the LOD and LSD detection data are latched in the
LOD-LSD holder. Changes in the LOD or LSD data while BLANK is low are directly connected to the output of
the LOD-LSD holder, but are only valid 1 μs after the change. The rising edge of LAT transfers the output data of
the LOD-LSD holder to the common shift register.
As shown in Table 5, LOD and LSD data cannot be checked simultaneously. LOD and LSD data are not valid
when TEF is active because all outputs are forced off.
The TEF bit indicates that the device junction temperature exceeds the temperature threshold (TTEF = 165°C,
typ). The TEF bit also indicates that the device has turned off all drivers to avoid overheating. The device
automatically turns the drivers back on when the device temperature decreases to less than TTEF – THYS. The
TEF data are held in the TEF holder latch until the TEF data are loaded into the common shift register by the
rising edge of LAT. If the device temperature falls below TTEF – THYS when LAT goes high, the TEF data in the
TEF holder become 0. If the device temperature is not below TTEF – THYS when LAT goes high, then the TEF
data remain 1. Table 5 shows a truth table for LOD, LSD, and TEF. Figure 33 to Figure 36 show different
examples of LOD, LSD, and TEF operation.
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Table 5. LOD, LSD, and TEF Truth Table
CONDITION
LED OPEN DETECTION
(LOD, Voltage Select Data =
0h to 3h)
LED SHORT DETECTION
(LSD, Voltage Select Data = 4h to 7h)
THERMAL ERROR FLAG (TEF)
0
LED is not open or the output is off
(VOUTRn/Gn/Bn is greater than the
voltage selected by the detection
voltage select bit in the
control data latch)
LED is not shorted or the output is off
(VOUTRn/Gn/Bn is less than or equal to
the voltage selected by the detection
voltage select bit in the
control data latch)
Junction temperature is lower than the
detect temperature (TTEF) before TEF
is undetected or the detect temperature
(TTEF – THYS) after TEF is detected
1
LED is open or shorted to GND
(VOUTRn/Gn/Bn is less than or equal to
the voltage selected by the detection
voltage select bit in the
control data latch)
LED terminal is short or OUTn is short
to higher voltage (VOUTn is greater than
The selected voltage by detection
voltage select bit in the
control data latch)
Junction temperature is higher than the
detect temperature (TTEF)
SID DATA
8.4.2.5 Thermal Shutdown (TSD)
The thermal shutdown (TSD) function turns off all constant-current outputs when the device junction temperature
(TJ) exceeds the temperature threshold (TTEF = 165°C, typ). The outputs remain disabled as long as the
overtemperature condition exists. The outputs are turned on again after the device junction temperature drops
below (TTEF – THYS).
8.4.2.6 Noise Reduction
Large surge currents may flow through the device and the board on which the device is mounted if all 24 LED
channels turn on simultaneously when BLANK goes low. These large current surges could induce detrimental
noise and electromagnetic interference (EMI) into other circuits. The TLC5952 turns the LED channels on in a
series delay to provide a circuit soft-start feature.
A small delay circuit is implemented between each output. When all bits of the on-off data latch are set to 1, each
constant-current output turns on in order (OUTR0, OUTG0, OUTB0, OUTR1, OUTG1, OUTB1, OUTR2–OUTB6,
OUTR7, OUTG7, and OUTB7) with a small delay between each output after BLANK goes low or LAT goes high;
see Figure 38. Both turnon and turnoff are delayed.
9 Power Supply Recommendations
Connect at least one 10-nF ceramic capacitor as close as possible between the VCC pin and ground. Additional
capacitors are needed on the LED power supply to reduce ripple on the LED power supply to a minimum.
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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC5952DAP
ACTIVE
HTSSOP
DAP
32
46
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TLC5952
TLC5952DAPR
ACTIVE
HTSSOP
DAP
32
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TLC5952
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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