DRV8801QRTYRQ1

DRV8801-Q1 DRV8801-Q1 SLVSAS7D – FEBRUARY 2011 – REVISED MARCH 2021 SLVSAS7D – FEBRUARY 2011 – REVISED MARCH 2021 www.ti.com DRV8801-Q1 DMOS Full-Bridge Motor Drivers 1 Features 3 Description • • The DRV8801-Q1 provides a versatile power driver solution with a full H-bridge driver. The device can drive a brushed DC motor or one winding of a stepper motor, as well as other devices like solenoids. A simple PHASE/ENABLE interface allows easy interfacing to controller circuits • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With The Following Results: – Device Temperature Grade 1: TA = –40°C to 125°C – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C4 Low RDS(on) Outputs (0.83-Ω HS + LS Typical) Low-Power Sleep Mode 100% PWM Duty Cycle Supported 8–38 V Operating Supply Voltage Range Thermally Enhanced Surface Mount Package Configurable Overcurrent Limit Protection Features – VBB Undervoltage Lockout (UVLO) – Overcurrent Protection (OCP) – Short-to-supply Protection – Short-to-ground Protection – Overtemperature Warning (OTW) – Overtemperature Shutdown (OTS) – Overcurrent and Overtemperature Fault Conditions Indicated on Pins (nFAULT) 2 Applications • • • • Automotive Body Systems Door Locks HVAC Actuators Piezo Alarm The output stages use N-channel power MOSFETs configured as ½-H-bridges. The DRV8801-Q1 is capable of peak output currents up to ±2.8 A and operating voltages up to 38 V. An internal charge pump generates needed gate drive voltages. A low-power sleep mode is provided which shuts down internal circuitry to achieve very low quiescent current draw. This sleep mode can be set using a dedicated nSLEEP pin. Internal protection functions are provided: undervoltage lockout, overcurrent protection, shortto-supply protection, short-to-ground protection, overtemperature warning, and overtemperature shutdown. Overcurrent (including short-to-ground and short-to-supply) and overtemperature fault conditions are indicated via an nFAULT pin. The DRV8801-Q1 is packaged in a 16-pin QFN package with exposed thermal pad, providing enhanced thermal dissipation. Device Information PART NUMBER(1) DRV8801-Q1 (1) PACKAGE QFN (16) BODY SIZE (NOM) 4.00 mm × 4.00 mm For all available packages, see the orderable addendum at the end of the datasheet. 8 V to 38 V PH/EN DRV8801-Q1 nSLEEP Controller nFAULT Brushed DC Motor Driver BDC VPROPI Protection Simplified Schematic An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2021 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: DRV8801-Q1 1 DRV8801-Q1 www.ti.com SLVSAS7D – FEBRUARY 2011 – REVISED MARCH 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................4 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings........................................ 5 6.2 ESD Ratings............................................................... 5 6.3 Recommended Operating Conditions.........................5 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................7 6.6 Timing Requirements.................................................. 8 6.7 Typical Characteristics.............................................. 10 7 Detailed Description...................................................... 11 7.1 Overview................................................................... 11 7.2 Functional Block Diagram......................................... 11 7.3 Feature Description...................................................11 7.4 Device Functional Modes..........................................15 8 Application and Implementation.................................. 16 8.1 Application Information............................................. 16 8.2 Typical Application.................................................... 16 8.3 Parallel Configuration................................................19 9 Power Supply Recommendations................................23 9.1 Bulk Capacitance...................................................... 23 10 Layout...........................................................................24 10.1 Layout Guidelines................................................... 24 10.2 Layout Example...................................................... 24 11 Device and Documentation Support..........................25 11.1 Documentation Support.......................................... 25 11.2 Receiving Notification of Documentation Updates.. 25 11.3 Support Resources................................................. 25 11.4 Trademarks............................................................. 25 11.5 Electrostatic Discharge Caution.............................. 25 11.6 Glossary.................................................................. 25 12 Mechanical, Packaging, and Orderable Information.................................................................... 25 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (June 2016) to Revision D (March 2021) Page • Improved description for pins CP1,CP2,nFAULT, nSLEEP, VBB and VCP in Pin Functions table..................... 4 • Added entries for VCP and CP2 pins in Absolute Maximum Ratings table........................................................ 5 • Change SLEEP to nSLEEP in PWM Control Timing Figure............................................................................... 8 • Provide additional information on SENSE pin behavior....................................................................................13 • Added equation for VPROPI to help when connecting pin’s output to ADC in Feature Description ................14 • Added die temperature estimation equation utilizing junction to ambient thermal impedance in Application and Implementation section.....................................................................................................................................17 • Added information on using motor driver’s pulse width modulating modes in Application and Implementation section.............................................................................................................................................................. 18 • Added information on connecting multiple DRV8801-Q1 together to support higher current in Application and Implementation section.....................................................................................................................................19 Changes from Revision B (January 2016) to Revision C (June 2016) Page • Changed one of the MODE1 pins to MODE2 in the Functional Block Diagram section .................................. 11 • Added the Receiving Notification of Documentation Updates section .............................................................25 Changes from Revision A (January 2014) to Revision B (October 2014) Page • Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 5 • Added tpd to the Overcurrent Control Timing image......................................................................................... 13 Changes from Revision * (February 2011) to Revision A (January 2014) Page • Deleted part number DRV8800-Q1 from page header....................................................................................... 1 • Added AEC-Q100 qualifications to Features list.................................................................................................1 • Added an Applications section to the front page................................................................................................ 1 • Deleted part number DRV8800-Q1 from Description section.............................................................................1 • Deleted Ordering Information table.....................................................................................................................1 • Deleted DRV8800-Q1 pinout diagram................................................................................................................ 4 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8801-Q1 DRV8801-Q1 www.ti.com • • • • • • • • • • • • • • • • • • SLVSAS7D – FEBRUARY 2011 – REVISED MARCH 2021 Deleted Terminal Name column for DRV8800-Q1 from Terminal Functions table..............................................4 Deleted DRV8800-Q1 pin descriptions for pins 5 and 9 from Terminal Functions table..................................... 4 Added a Thermal Information table.................................................................................................................... 5 Removed DRV8800-Q1 part number from column heading of Thermal Information table................................. 5 Changed parameter name and test condition for Electrical Characteristics, VTRP row.....................................7 Added two notes to end of Electrical Characteristics table.................................................................................7 Changed "Overcurrent protection period" parameter to "Overcurrent retry time"............................................... 8 Deleted DRV8800-Q1 from text of Device Operation section........................................................................... 11 Deleted DRV8800-Q1 Functional Block Diagram............................................................................................. 11 Updated the Overcurrent Control Timing image............................................................................................... 13 Updated the Overcurrent Control Timing image............................................................................................... 14 Changed active low to low in Diagnostic Output section.................................................................................. 15 Deleted VREG section; deleted "(DRV8801-Q1 Only)" from VPROPI section title.......................................... 15 Changed a value in row 5 of the Control Logic Table....................................................................................... 15 Added a row to Control Logic Table..................................................................................................................15 Deleted DRV8800-Q1 from the text of the Low-Power Mode sedtion.............................................................. 15 Deleted DRV8800-Q1 Typical Application Diagram..........................................................................................16 Corrected part number in DRV8801-Q1 application diagram........................................................................... 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8801-Q1 3 DRV8801-Q1 www.ti.com SLVSAS7D – FEBRUARY 2011 – REVISED MARCH 2021 MODE1 nFAULT VPROPI VCP 15 14 13 8 4 VBB ENABLE 7 3 SENSE nSLEEP Exposed Thermal Pad 6 2 OUT+ GND 5 1 MODE2 PHASE 16 5 Pin Configuration and Functions 12 GND 11 CP2 10 CP1 9 OUT– Figure 5-1. RTY Package 16-Pin QFN With Exposed Thermal Pad Top View Table 5-1. Pin Functions PIN NAME I/O CP1 10 PWR CP2 11 PWR ENABLE DESCRIPTION Charge pump switching node. Connect a X7R, 0.1-μF, VBB-rated ceramic capacitor from CP1 to CP2. 4 I 2, 12 PWR MODE 1 16 I Mode logic input MODE 2 5 I Mode 2 logic input nFAULT 15 O Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor. nSLEEP 3 I Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor. GND Enable logic input Ground OUT+ 6 O DMOS full-bridge output positive OUT– 9 O DMOS full-bridge output negative PHASE 1 I Phase logic input for direction control SENSE 7 IO VBB 8 PWR VCP 13 O VPROPI Thermal Pad 4 NO. 14 O PAD PWR Sense power return Driver supply voltage. Bypass to GND with 0.1-μF ceramic capacitors plus a bulk capacitor rated for VBB. Charge pump reservoir capacitor pin. Connect a X7R, 0.1-μF, 16-V ceramic capacitor to VBB. Winding current proportional voltage output Exposed pad for thermal dissipation; connect to GND pins. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8801-Q1 DRV8801-Q1 www.ti.com SLVSAS7D – FEBRUARY 2011 – REVISED MARCH 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX VBB Load supply voltage(2) –0.3 40 V VCP and CP2 Charge pump voltage –0.3 VBB+17 V IOUT Output current 0 2.8 A –500 500 mV 36 V VSense Sense voltage VBB_OUT VBB to OUTx VOUT_SEN OUTx to SENSE VDD PHASE, ENABLE, MODE1, MODE2, nSLEEP, nFAULT(2) UNIT 36 V 7 V –0.3 PD Continuous total power dissipation TA Operating free-air temperature –40 125 °C TJ Maximum junction temperature –40 150 °C Tstg Storage temperature –40 125 °C (1) (2) See Section 6.4 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. 6.2 ESD Ratings VALUE Human body model (HBM), per AEC V(ESD) (1) Electrostatic discharge Q100-002(1) Charged device model (CDM), per AEC Q100-011 UNIT ±2000 Corner pins (1, 4, 5, 8, 9, 12, 13, and 16) ±750 Other pins ±500 V AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions VBB Power supply voltage MIN MAX UNIT 8 38 V VDD Logic voltage 0 5.5 V fPWM Applied PWM signal (PHASE and ENABLE) 0 100 kHz TA Ambient temperature –40 125 °C 6.4 Thermal Information DRV8801-Q1 THERMAL METRIC(1) RTY (QFN) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 46.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 43.0 °C/W RθJB Junction-to-board thermal resistance 22.5 °C/W ψJT Junction-to-top characterization parameter 0.6 °C/W ψJB Junction-to-board characterization parameter 22.5 °C/W Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8801-Q1 5 DRV8801-Q1 www.ti.com SLVSAS7D – FEBRUARY 2011 – REVISED MARCH 2021 DRV8801-Q1 THERMAL METRIC(1) RTY (QFN) UNIT 16 PINS RθJC(bot) (1) 6 Junction-to-case (bottom) thermal resistance 3.8 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8801-Q1 DRV8801-Q1 www.ti.com SLVSAS7D – FEBRUARY 2011 – REVISED MARCH 2021 6.5 Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VBB) VBB VBB operating voltage IVBB VBB operating supply current IVBBQ VBB sleep-mode supply current 8 fPWM < 50 kHz 38 6 Charge pump on, outputs disabled mA 3.2 nSLEEP = 0, TJ = 25°C V 10 μA CONTROL INPUTS (PHASE, ENABLE, MODE1, MODE2, nSLEEP) VIL Input logic low voltage VIH Input logic high voltage VIHYS Input hysteresis IIL Input logic low current IIH Input logic high current IIL Input logic low current IIH Input logic high current VIL Input logic low voltage VIH Input logic high voltage IIL Input logic low current IIH Input logic high current 0.8 PHASE, ENABLE, MODE1, MODE2 PHASE, MODE1, MODE2 ENABLE 2 100 500 800 –20 < –2 20 VIN = 2.0 V