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ISO7821LLS
SLLSET5A – MARCH 2016 – REVISED SEPTEMBER 2016
ISO7821LLS High-Performance, 8000-VPK Reinforced Isolated Dual-LVDS Buffer
1 Features
2 Applications
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Complies with TIA/EIA-644-A LVDS Standard
Signaling Rate: 50 Mbps to 150 Mbps
Optimized for DC-Balanced Data
Wide Supply Range: 3 V to 5.5 V
Wide Temperature Range: –55°C to 125°C
Low-Power Consumption, Typical 10.3 mA per
Channel at 150 Mbps
Low Propagation Delay: 17 ns Typical
Industry leading CMTI(Min): ±100 kV/μs
Robust Electromagnetic Compatibility (EMC)
System-Level ESD, EFT, and Surge Immunity
Low Emissions
Isolation Barrier Life: > 40 Years
SOIC-16 Wide Body (DW) and Extra-Wide Body
(DWW) Package Options
Isolation Surge Withstand Voltage 12800 VPK
Safety-Related Certifications:
– 8000-VPK Reinforced Isolation per DIN V VDE
V 0884–10 (VDE V 0884–10): 2006–12
– 5700-VRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950–1 and IEC 60601–1 End Equipment
Standards
– TUV Certification per EN 61010-1 and EN
60950-1
– CQC Certification per GB4943.1–2011
– All Certifications are Planned
Motor Control
Test and Measurement
Industrial Automation
Medical Equipment
Communication Systems
3 Description
The ISO7821LLS device is a high-performance,
isolated dual-LVDS buffer with 8000-VPK isolation
voltage. This device provides high electromagnetic
immunity and low emissions at low-power
consumption, while isolating the LVDS bus signal.
Each isolation channel has an LVDS receive and
transmit buffer. Timing performance for the
ISO7821LLS device is optimized for use with
communication systems that use DC-balanced data
streams which is achieved through an internal
distortion correction scheme.
The ISO7821LLS device has one forward and one
reverse-direction channel.
Through innovative chip design and layout
techniques, the electromagnetic compatibility of the
ISO7821LLS device has been significantly enhanced
to ease system-level ESD, EFT, surge, and
emissions compliance.
The ISO7821LLS device is available in a 16-pin SOIC
wide-body (DW) and extra-wide body (DWW)
packages.
Device Information(1)
PART NUMBER
ISO7821LLS
PACKAGE
BODY SIZE (NOM)
DW (16)
10.30 mm × 7.50 mm
DWW (16)
10.30 mm × 14.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCCI
Isolation
Capacitor
VCCO
INx+
OUTx+
LVDS RX
LVDS TX
INx±
OUTx±
ENx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI and GNDI are supply and ground connections respectively for the input channels.
VCCO and GNDO are supply and ground connections respectively for the output channels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7821LLS
SLLSET5A – MARCH 2016 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
Absolute Maximum Ratings ..................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety Limiting Values .............................................. 7
DC Electrical Characteristics .................................... 8
DC Supply Current Characteristics ......................... 9
Timing Requirements for Distortion Correction
Scheme ...................................................................... 9
6.12 Switching Characteristics ...................................... 10
6.13 Insulation Characteristics Curves ......................... 11
6.14 Typical Characteristics .......................................... 12
7
8
Detailed Description ............................................ 17
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
18
19
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
Parameter Measurement Information ................ 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2016) to Revision A
•
2
Page
Changed the device status from Product Preview to Production Data and released full version of the data sheet .............. 1
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SLLSET5A – MARCH 2016 – REVISED SEPTEMBER 2016
5 Pin Configuration and Functions
DW and DWW Packages
16-Pin SOIC
Top View
1
16 VCC2
GND1
2
15 GND2
INA+
3
14 OUTA+
INA±
4
OUTB± 5
ISOLATION
VCC1
13 OUTA±
OUTB+ 6
EN1
7
GND1
8
12
INB±
11
INB+
10
EN2
9 GND2
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN1
7
I
Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high
impedance state when EN1 is low.
EN2
10
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high
impedance state when EN2 is low.
GND1
GND2
2
8
9
15
—
Ground connection for VCC1
—
Ground connection for VCC2
INA+
3
I
Positive differential input, channel A
INA–
4
I
Negative differential input, channel A
INB+
11
I
Positive differential input, channel B
INB–
12
I
Negative differential input, channel B
OUTA+
14
O
Positive differential output, channel A
OUTA–
13
O
Negative differential output, channel A
OUTB+
6
O
Positive differential output, channel B
OUTB–
5
O
Negative differential output, channel B
VCC1
1
—
Power supply, side 1, VCC1
VCC2
16
—
Power supply, side 2, VCC2
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCCx
Supply voltage (2)
VCC1, VCC2
–0.5
6
V
V
Voltage on input, output, and
enable pins
OUTx, INx, ENx
–0.5
VCCx + 0.5 (3)
V
IO
Maximum current through OUTx pins
–20
20
mA
TJ
Junction temperature
–55
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground pin (GND1 or GND2) and are peak voltage
values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±4500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VCC1, VCC2
Supply voltage
|VID|
Magnitude of RX input
differential voltage
Driven with voltage sources on RX pins
VIC
RX input commonmode voltage
VCC1, VCC2 ≥ 3 V
RL
TX far-end differential termination
DR
Signaling rate
TA
Ambient temperature
4
MIN
NOM
MAX
3
3.3
5.5
V
100
600
mV
0.5 |VID|
2.4 – 0.5 |VID|
100
50
–55
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25
UNIT
V
Ω
150
Mbps
125
°C
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6.4 Thermal Information
ISO7821LLS
THERMAL METRIC (1)
DW (SOIC)
DWW (SOIC)
16 PINS
16 PINS
UNIT
82
84.6
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case(top) thermal resistance
44.6
46.4
°C/W
RθJB
Junction-to-board thermal resistance
46.6
55.3
°C/W
ψJT
Junction-to-top characterization parameter
17.8
18.7
°C/W
ψJB
Junction-to-board characterization parameter
46.1
54.5
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 5 pF, RL = 100-Ω differential, input a 75-MHz 50% duty-cycle square wave,
EN1 = EN2 = 5.5 V
PARAMETER
TEST CONDITIONS
MAX
UNIT
180
mW
Maximum power dissipation (side 1)
90
mW
Maximum power dissipation (side 2)
90
mW
PD
Maximum power dissipation (both sides)
PD1
PD2
MAX
TYP
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6.6 Insulation Specifications
over operating free-air temperature range (unless otherwise noted)
PARAMETER
SPECIFICATION
TEST CONDITIONS
DW
DWW
UNIT
GENERAL
External clearance (1)
Shortest terminal-to-terminal distance through air
>8
>14.5
mm
CPG
External creepage (1)
Shortest terminal-to-terminal distance across the
package surface
>8
>14.5
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>21
>21
μm
CTI
Tracking resistance (comparative
tracking index)
DIN EN 60112 (VDE 0303–11); IEC 60112; UL 746A
>600
>600
V
Material group
According to IEC 60664-1
CLR
Overvoltage category per IEC 60664-1
DIN V VDE V 0884–10 (VDE V 0884–10):2006–12
VIORM
Maximum repetitive peak isolation
voltage
VIOWM Maximum isolation working voltage
I
I
Rated mains voltage ≤ 600 VRMS
I–IV
I–IV
Rated mains voltage ≤ 1000 VRMS
I–III
I–IV
AC voltage (bipolar)
2121
2828
VPK
AC voltage (sine wave); time dependent dielectric
breakdown (TDDB) test; see Figure 1 and Figure 2
1500
2000
VRMS
DC voltage
2121
2828
VDC
8000
8000
VPK
8000
8000
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 2545 VPK (DW) and
3394 VPK (DWW), tm = 10 s
≤5
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 3394 VPK (DW) and
4525 VPK (DWW), tm = 10 s
≤5
≤5
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = VIORM, tini = 1 s;
Vpd(m) = 1.875 × VIORM= 3977 VPK (DW) and
5303 VPK (DWW), tm = 1 s
≤5
≤5
(2)
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM, t = 60 s (qualification)
t = 1 s (100% production)
VIOSM
Maximum surge isolation voltage (3)
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
qpd
Apparent charge
(4)
Barrier capacitance, input to output (5)
CIO
Isolation resistance, input to output (5)
RIO
VIO = 0.4 × sin (2πft), f = 1 MHz
~0.7
~0.7
VIO = 500 V, TA = 25°C
>1012
>1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
>1011
9
>109
VIO = 500 V at TS = 150°C
>10
Pollution degree
2
2
Climatic category
55/125/21
55/125/21
5700
5700
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstanding isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 6840 VRMS,
t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Safety-Related Certifications
VDE
CSA
Plan to certify according to
DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
and DIN EN 60950-1 (VDE
0805 Teil 1):2011-01
UL
Plan to certify under CSA
Component Acceptance
Notice 5A, IEC 60950-1 and
IEC 60601-1
Plan to certify according
to UL 1577 Component
Recognition Program
CQC
TUV
Plan to certify according to
GB 4943.1-2011
Reinforced insulation per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed., 800 VRMS
Reinforced insulation
(DW package) and 1450 VRMS
Maximum transient
isolation voltage, 8000 VPK; (DWW package) max working
voltage (pollution degree 2,
Maximum repetitive peak
Single protection,
isolation voltage, 2121 VPK material group I);
5700 VRMS
(DW), 2828 VPK (DWW);
2 MOPP (Means of Patient
Maximum surge isolation
Protection) per CSA 60601voltage, 8000 VPK
1:14 and IEC 60601-1 Ed. 3.1,
250 VRMS (354 VPK) max
working voltage (DW package)
Reinforced Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS
maximum working voltage
Certification planned
Certification planned
Certification planned
Certification planned
Plan to certify according to
EN 61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to
working voltage of 600 VRMS (DW
package) and 1000 VRMS (DWW
package)
5700 VRMS Reinforced insulation per
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working
voltage of 800 VRMS (DW package) and
1450 VRMS (DWW package)
Certification planned
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DW PACKAGE
IS
Safety input, output, or supply
current
PS
Safety input, output, or total power
TS
Maximum safety temperature
RθJA = 82°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
see Figure 3
277
RθJA = 82°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 3
423
mA
RθJA = 82°C/W, TJ = 150°C, TA = 25°C,
see Figure 5
1524
mW
150
°C
DWW PACKAGE
IS
Safety input, output, or supply
current
PS
Safety input, output, or total power
TS
Maximum safety temperature
RθJA = 84.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
see Figure 4
269
RθJA = 84.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 4
410
RθJA = 84.6°C/W, TJ = 150°C, TA = 25°C,
see Figure 6
mA
1478
mW
150
°C
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a
device installed on a High-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
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6.9 DC Electrical Characteristics
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
13
40
µA
2.25
V
GENERAL
IIN(EN)
Leakage Current on ENx
pins
VCC+(UVLO)
Positive-going undervoltagelockout (UVLO) threshold
VCC–(UVLO)
Negative-going UVLO
threshold
VHYS(UVLO)
UVLO threshold hysteresis
VEN(ON)
EN pin turn-on threshold
VEN(OFF)
EN pin turn-off threshold
VEN(HYS)
EN pin threshold hysteresis
Internal pullup on ENx pins
1.7
V
0.2
V
0.7 VCCx
0.3 VCCx
V
V
0.1 VCCx
V
(1)
Common-mode transient
immunity
VI = VCCI or 0 V;
VCM = 1000 V, see Figure 22
100
120
|VOD|
TX DC output differential
voltage
RL = 100 Ω, see Figure 23
250
350
450
mV
∆VOD
Change in TX DC output
differential between logic 1
and 0 states
RL = 100 Ω, see Figure 23
–10
0
10
mV
VOC
TX DC output commonmode voltage
RL = 100 Ω, see Figure 23
1.125
1.2
1.375
∆VOC
TX DC common-mode
voltage difference
RL = 100 Ω, see Figure 23
–25
0
25
IOS
TX output short circuit
current through OUTx
IOZ
TX output current when in
high impedance
CMTI
kV/μs
LVDS TX
TX output pad capacitance
on OUTx at 1 MHz
COUT
OUTx = 0
10
OUTxP = OUTxM
10
ENx = 0, OUTx from 0 to VCCx
–5
5
DW package: ENx = 0, DC offset = VCC / 2,
Swing = 200 mV, Frequency (f) = 1 MHz
10
DWW package: ENx = 0,
DC offset = VCC / 2, Swing = 200 mV,
Frequency (f) = 1 MHz
10
V
mV
mA
µA
pF
LVDS RX
VIC
RX input common mode
voltage
VCCx ≥ 3 V
VIT1
Positive going RX input
differential threshold
Across VIC
VIT2
Negative going RX input
differential threshold
Across VIC
IINx
Input current on INx
From 0 to VCC (each input independently)
IINxP – IINxM
Input current balance
From 0 to VCC
CIN
DW package: DC offset = 1.2 V,
RX input pad capacitance on Swing = 200 mV, f = 1 MHz
INx at 1 MHz
DWW package: DC offset = 1.2 V,
Swing = 200 mV, f = 1 MHz
(1)
8
0.5 |VID|
1.2
2.4 – 0.5 |VID|
50
–50
V
mV
mV
10
–6
20
µA
6
µA
6.6
pF
7.5
VCCI = Input-side VCCx; VCCO = Output-side VCCx.
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6.10 DC Supply Current Characteristics
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
3 V < VCC1,
VCC2 < 3.6 V
ICC1
ICC2
Supply current
side 1 and
side 2
MIN
TYP MAX
EN1 = EN2 = 0, OUTx floating, VID ≥ 50 mV
2.3
3.6
EN1 = EN2 = 0, OUTx floating, VID ≤ –50 mV
3.5
5.6
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≥ 50 mV
6.2
9.9
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≤ –50 mV
7.5
12
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
50 Mbps
7.6
12.1
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
125 Mbps
8.5
13.6
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
150 Mbps
8.9
14.2
EN1 = EN2 = 0, OUTx floating, VID ≥ 50 mV
2.3
3.6
EN1 = EN2 = 0, OUTx floating, VID ≤ –50 mV
3.6
5.7
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≥ 50 mV
6.6
10.5
7.9
12.6
8.3
13.2
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
125 Mbps
9.7
15.5
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
150 Mbps
10.3
16.4
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≤ –50 mV
4.5 V < VCC1,
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
VCC2 < 5.5 V
50 Mbps
UNIT
mA
6.11 Timing Requirements for Distortion Correction Scheme
Valid data = 8b10b like data with DC balance and bounded disparity. See Figure 25.
MIN
tCALIB
Time to complete internal calibration, after exiting idle state. LVDS TX
output is held high during this time. During this time valid data must be
presented at the receiver.
tIDLE
The minimum duration of any idle state that must be maintained between
valid data transmissions.
tIDLE_OUT
After a channel enters idle state, the internal calibration loses lock after this
time, and the LVDS outputs are gated high.
250
NOM
MAX
UNIT
750
µs
10
200
µs
600
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6.12 Switching Characteristics
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
17
25
ns
LVDS CHANNEL
tPLH
tPHL
Propagation delay time
tsk(o)
Channel-to-channel output skew time
Opposite directional channels, same
voltage and temperature
4.5
ns
tsk(pp)
Part-part skew
Same directional channels, same
voltage and temperature
4.5
ns
tCMset
Common-mode setting time after
EN = 0 to EN = 1 transition
Common-mode capacitive
load = 100 pF to 0.5 nF
20
µs
Total eye closure
Default output delay time from input
power loss
tfs
DC balanced data with maximum run
length of 6 at 125 Mbps,
RX VID = 350 mVPP, 1 ns trf 10%-90%,
–40 < TA < 125°C, 3 V < VCC1,
VCC2 < 5 V
30%
DC balanced data with maximum run
length of 6 at 150 Mbps,
RX VID = 350 mVPP, 1 ns trf 10%-90%,
–40 < TA < 125°C, 3 V < VCC1,
VCC2 < 5 V
40%
Measured from the time VCC goes
below 1.7 V, see Figure 21
0.2
9
µs
780
1380
ps
0
150
mVPP
LVDS TX AND RX
trf
TX differential rise and fall times
(20% to 80%)
∆VOC(pp)
TX common-mode voltage peak-topeak at 100 Mbps
tPLZ, tPHZ TX disable time—valid output to HiZ
See Figure 19
300
See Figure 20
10
20
ns
tPZH
TX enable time—HiZ to valid high
output (1)
See Figure 20
10
20
ns
|VID|
Magnitude of RX input differential
voltage for valid operation
Driven with voltage sources on RX pins,
see figures in the Parameter
Measurement Information section
600
mV
trf(RX)
Allowed RX input differential rise and
fall times (20% to 80%)
See Figure 24
0.3 × UI (2)
ns
(1)
(2)
10
100
1
The tPZL parameter is not defined because of the distortion-correction scheme. See the Distortion-Correction Scheme section for more
information.
UI is the unit interval.
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6.13 Insulation Characteristics Curves
1.E+11
87.5%
1.E+9
1.E+9
1.E+8
1.E+8
1.E+7
1.E+6
1.E+5
Safety Margin Zone: 2400 VRMS, 63 Years
Operating Zone: 2000 VRMS, 34 Years
TDDB Line ( VIN+
B.
The data to ISOLVDS channel should be either idle high, idle low, clock, or valid data.
Valid data = 8b10b like data with DC balance and bounded disparity.
C.
When transitioning from an uncalibrated sate to a calibrated state, the ISOLVDS channel output is gated high for up
to tCALIB, during which the channel is calibrated.
D.
If the channel finds no transitions in the incoming data for a period of tIDLE_OUT, the channel goes to an uncalibrated
state.
E.
Power loss (which implies no data transitions) takes the channel to an uncalibrated state.
F.
If, for some reason, the idle-high or idle-low state must be held on the line, this state must be held for at least tIDLE.
Figure 25. DCD Correction Timing Diagram
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8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO7821LLS device.
Table 2. ISO7821LLS Function Table (1)
VCCI
VCCO
PU
PU
X
(1)
(2)
(3)
INPUT
(INx±) (2)
OUTPUT ENABLE
(ENx)
OUTPUT
(OUTx±) (3)
H
H or open
H
L
H or open
L
I
H or open
H or L
X
L
Z
A low-logic state at the output enable causes the outputs to be in high
impedance.
Default mode: When VCCI is unpowered, a channel output assumes
the logic high state.
When VCCI transitions from unpowered to powered up, a channel
output assumes the logic state of the input.
When VCCI transitions from powered up to unpowered, a channel
output assumes the selected default high state.
PU
COMMENTS
Normal Operation:
A channel output assumes the logic state of the input.
PD
PU
X
H or open
H
X
PD
X
X
Undetermined
When VCCO is unpowered, a channel output is undetermined.
When VCCO transitions from unpowered to powered up, a channel
output assumes the logic state of the input
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCCx ≥ 2.25 V); PD = Powered down (VCCx ≤ 1.7 V); X = Irrelevant
Input (INx±): H = high level (VID ≥ 50 mV); L = low level (VID ≤ –50 mV); I = indeterminate (–50 mV < VID < 50 mV)
Output (OUTx±): H = high level (VOD ≥ 250 mV); L = low level (VOD ≤ –250 mV); Z = high impedance.
8.4.1 Device I/O Schematics
LVDS Input
LVDS Output
VCC
600 k
600 k
VCC
INx+
INx±
20
20 k
OUTx
Enable
VCC
275 k
ENx
1k
Figure 26. Device I/O Schematics
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7821LLS device is a high-performance, reinforced isolated dual-LVDS buffer. Isolation can be used to
help achieve human and system safety, to overcome ground potential difference (GPD), or to improve noise
immunity and system performance.
The LVDS signaling can be used over most interfaces to achieve higher data rates because the LVDS is only a
physical layer. LVDS can also be used for a proprietary communication scheme implemented between a host
controller and a slave. Example use cases include connecting a high-speed I/O module to a host controller, a
subsystem connecting to a backplane, and connection between two high-speed subsystems. Many of these
systems operate under harsh environments making them susceptible to electromagnetic interferences, voltage
surges, electrical fast transients (EFT), and other disturbances. These systems must also meet strict limits on
radiated emissions. Using isolation in combination with a robust low-noise signaling standard such as LVDS,
achieves both high immunity to noise and low emissions.
Example end applications that could benefit from the ISO7821LLS device include high-voltage motor control, test
and measurement, industrial automation, and medical equipment.
9.2 Typical Application
One application for isolated LVDS buffers is for point-to-point communication between two high-speed capable,
application-specific integrated circuits (ASICs) or FPGAs. In a high-voltage motor control application, for
example, Node 1 could be a controller on a low-voltage or earth referenced board, and Node 2, could be
controller placed on the power board, biased to high voltage. Figure 27 and Figure 28 show the application
schematics.
Figure 28 provides further details of using the ISO7821LLS device to isolate the LVDS interface. The LVDS
connection to the ISO7821LLS device can be traces on a board (shown as straight lines between Node 1 and
the ISO7821LLS device), a twisted pair cable (as shown between Node 2 and the ISO7821LLS device), or any
other controlled impedance channel. Differential 100-Ω terminations are placed near each LVDS receiver. The
characteristic impedance of the channel should also be 100-Ω differential.
In the example shown in Figure 27 and Figure 28, the ISO7821LLS device provides reinforced or safety isolation
between the high-voltage elements of the motor drive and the low-voltage control circuitry. This configuration
also ensures reliable communication, regardless of the high conducted and radiated noise present in the system.
20
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Typical Application (continued)
Isolated IGBT
Gate Drivers
Rectifier Diodes
IGBT Module
DC+
DC±
Drive
Output
Power
Input
M
DC±
PWM
Signals
DC±
ISO7821LLS
Node 2
Node 1
DC±
DC±
Isolated Current
and Voltage Sense
DC±
Communication Bus
RS-485, CAN,
Ethernet
Encoder
High Voltage Motor Drive
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Isolation Barrier
Figure 27. Isolated LVDS Interface in Motor Control Application
VCC1
0.1 F
3.3 V
1
Vcc1
7
EN1
3
Node 1
100 Ÿ
ASIC or FPGA
100 Ÿ
VCC2
0.1 F
3.3 V
16
Vcc2
EN2
10
14
INA+
OUTA+
ISO7821LLS
13
INA±
OUTA±
5
INB± 12
OUTB±
6
INB+ 11
OUTB+
100 Ÿ
4
GND1
2, 8
Node 2
ASIC or FPGA
100 Ÿ
GND2
9, 15
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Figure 28. Isolated LVDS Interface Between Two Nodes (ASIC or FPGA)
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Typical Application (continued)
9.2.1 Design Requirements
For the ISO7821LLS device, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
Supply voltage range, VCC1 and VCC2
3 V to 5.5 V
Receiver common-mode voltage range
0.5 |VID| to 2.4 – 0.5 |VID|
External termination resistance
100 Ω
Interconnect differential characteristic impedance
100 Ω
Signaling rate
50 to 150 Mbps
Decoupling capacitor from VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
The ISO7821LLS device has minimum requirements on external components for correct operation. External
bypass capacitors (0.1 µF) are required for both supplies (VCC1 and VCC2). A termination resistor with a value of
100 Ω is required between each differential input pair (INx+ and INx–), with the resistors placed as close to the
device pins as possible. A differential termination resistor with a value of 100 Ω is required on the far end for the
LVDS transmitters. Figure 29 shows these connections.
VCC2
VCC1
1
16
0.1 F
0.1 F
GND2
GND1
2
15
3
14
INA+
LVDS
RX
INA±
4
OUTB±
5
LVDS
TX
OUTB+
Isolation Capacitor
100
OUTA+
LVDS
TX
OUTA±
13
INB±
12
LVDS
RX
INB+
6
11
7
10
8
9
100
EN2
EN1
GND1
GND2
Figure 29. Typical ISO7821LLS Circuit Hook-Up
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9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the
ISO7821LLS device incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
9.2.3 Application Curve
Figure 30 shows a typical eye diagram of the ISO7821LLS device which indicates low jitter and a wide-open eye
at the maximum data rate of 150 Mbps.
Figure 30. Eye Diagram at 150 Mbps PRBS, 3.3 V and 25°C
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 or
SN6505. For such applications, detailed power supply design and transformer selection recommendations are
available in the following data sheets: SN6501 Transformer Driver for Isolated Power Supplies (SLLSEA0) and
SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies (SLLSEP9).
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 31). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
• While routing differential traces on a board, TI recommends that the distance between two differential pairs be
much higher (at least 2x) than the distance between the traces in a differential pair. This distance minimizes
crosstalk between the two differential pairs.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
The ISO7821LLS device requires no special layout considerations to mitigate electromagnetic emissions.
For detailed layout recommendations, see the application note, Digital Isolator Design Guide (SLLA284).
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps (or rise and fall times higher than 1 ns) and trace
lengths of up to 10 inches, use standard FR–4 UL94V-0 epoxy-glass as PCB material. This PCB is preferred
over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption,
greater strength and stiffness, and self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 31. Layout Example
24
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Digital Isolator Design Guide (SLLA284)
• ISO782xLLx Isolated Dual LVDS Buffer Evaluation Module (SLLU240)
• Isolation Glossary (SLLA353)
• LVDS Owner’s Manual (SNLA187)
• SN6501 Transformer Driver for Isolated Power Supplies (SLLSEA0)
• SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies (SLLSEP9)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates — go to the product folder for your device on ti.com. In the
upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information
that has changed (if any). For change details, check the revision history of any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
ISO7821LLSDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7821LLS
ISO7821LLSDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7821LLS
ISO7821LLSDWW
ACTIVE
SOIC
DWW
16
45
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
ISO7821LLS
ISO7821LLSDWWR
ACTIVE
SOIC
DWW
16
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
ISO7821LLS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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