LM25066I, LM25066IA
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SNVS824C – JUNE 2012 – REVISED MARCH 2013
Intel Node Manager Compliant System Power Management and Protection IC with PMBus
Check for Samples: LM25066I, LM25066IA
FEATURES
DESCRIPTION
•
While the LM25066I/A is functionally similar to the
LM25066/A, the LM25066I/A is fully compliant to Intel
Node Manager 2.0, 2.5 and adds the READ_EIN
energy accumulator feature. The LM25066I/A
combines a high-performance hot-swap controller
with a PMBus 1.2™ compliant SMBus/I2C interface to
accurately measure, control and protect the electrical
operating conditions of critical systems. The
LM25066I/A continuously supplies real-time power,
voltage, current, temperature, and fault data to the
system management host via the SMBus interface.
1
2
•
•
•
•
•
•
•
•
•
•
•
Fully Node Manager 2.0 and 2.5 Compliant with
I2C/SMBus interface and PMBus™ compliant
command structure
Input voltage range: 2.9V to 17V
Programmable 25mV or 46mV current limit
threshold
Read_EIN accurately measures true input
power via simultaneous sampling
Configurable circuit breaker protection for
hard shorts
Configurable under- and over-voltage lockouts
with hysteresis
Real time monitoring of VIN, VOUT, IIN, PIN, VAUX
with 12-bit resolution and 1 kHz sampling rate
Current measurement accuracy: ±1%
(LM25066IA) and Power measurement
accuracy: ±2.0% (LM25066IA) over temperature
Averaging of VIN, IIN, PIN, and VOUT over
programmable interval ranging from 0.001 to 4
seconds
Programmable WARN and FAULT thresholds
with SMBA notification
Blackbox capture of telemetry measurements
and device status triggered by WARN or
FAULT condition
24-lead WQFN package
The LM25066I/A control block includes a unique hotswap architecture that provides current and power
limiting to protect sensitive circuitry even during the
most stressful conditions. A fast-acting circuit breaker
prevents damage in the event of a short circuit on the
output. The input under-voltage, over-voltage
hysteresis, insertion delay time and fault detection
time are all configurable. A temperature monitoring
block on the LM25066I/A interfaces with a low-cost
external
diode
for
continuous
temperature
assessment of the external MOSFET or other thermal
sensitive components. The POWER GOOD output
provides a fast alert when the input and/or output
voltages are outside their programmed range.
Accurate power readings are accomplished by using
the
READ_EIN
command.
A
black
box
(Telemetry/Fault Snapshot) function captures and
stores telemetry data and device status in the event
of a warning or a fault.
APPLICATIONS
•
•
•
Server backplane systems
Basestation power distribution systems
Solid state circuit breaker (eFuse)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
LM25066I, LM25066IA
SNVS824C – JUNE 2012 – REVISED MARCH 2013
www.ti.com
Typical Application Schematic
Q2
VIN
CIN
VOUT
RS
Q1
DZ
R1
VIN
CLOAD
GATE
SENSE
OUT
R4
DIODE
UVLO/EN
UVLO/EN
R2
FB
VDD
R5
OVLO
R3
RPG
VDD
ADR2
N/C
ADR1
N/C
ADR0
PGD
LM25066I/A
VAUX
RETRY
SMBA
SMBus
Interface
Auxillary ADC Input
(0V - 1.16V)
CB
SDA
CL
SCL
VDD
VREF
CVDD
GND
TIMER
CVREF
PWR
RPWR
CT
GATE
SENSE
VIN
UVLO/EN
OVLO
GND
SDA
Connection Diagram
OUT
SCL
SMBA
PGD
Exposed
Pad
VREF
FB
CB
CL
RETRY
VDD
VAUX
ADR0
TIMER
ADR1
DIODE
ADR2
24
PWR
5x4 mm WQFN 24L
1
Solder exposed pad to ground.
Top View
WQFN-24
2
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SNVS824C – JUNE 2012 – REVISED MARCH 2013
Pin Descriptions
Pin
No.
Name
Description
Applications Information
Pad
Exposed
Pad
Exposed pad of WQFN
package
No internal electrical connection. Solder to the ground plane to reduce thermal resistance.
1
ADR2
SMBUS address line 2
3 - state address line. Should be connected to GND, VDD, or left floating.
2
ADR1
SMBUS address line 1
3 - state address line. Should be connected to GND, VDD, or left floating.
3
ADR0
SMBUS address line 0
3 - state address line. Should be connected to GND, VDD, or left floating.
4
VDD
Internal sub-regulator
output
Internally sub-regulated 4.5V bias supply. Connect a 1 µF capacitor on this pin to ground
for bypassing.
5
CL
Current limit range
Connect this pin to GND to set the nominal over-current threshold at 25mV. Connecting
CL to VDD will set the over-current threshold to be 46mV.
6
CB
Circuit breaker range
This pin sets the circuit breaker protection point in relation to the over-current trip point.
When connected to GND, this pin will set the circuit breaker point to be 1.8 times the
over-current threshold. Connecting this pin to VDD sets the circuit breaker trip point to be
3.6 times the over-current threshold.
7
FB
Power Good feedback
An external resistor divider from OUT sets the output voltage at which the PGD pin
switches. The threshold at the pin is 1.167V. An internal 24 µA current source provides
hysteresis.
8
RETRY
Fault retry input
This pin configures the power up fault retry behavior. When this pin is grounded, the
device will continually try to engage power during a fault. If the pin is connected to VDD,
the device will latch off during a fault.
9
TIMER
Timing capacitor
An external capacitor connected to this pin sets the insertion time delay, fault timeout
period and restart timing.
10
PWR
Power limit set
11
PGD
Power Good indicator
12
OUT
Output feedback
Connect to the output rail (external MOSFET source). Internally used to determine the
MOSFET VDS voltage for power limiting, and to monitor the output voltage.
Connect to the external MOSFET's gate.
An external resistor connected to this pin, in conjunction with the current sense resistor
(RS), sets the maximum power dissipation allowed in the external series pass MOSFET.
An open drain output. This output is high when the voltage at the FB pin is above 1.167V
and the input supply is within its under-voltage and over-voltage thresholds. Connect via a
pullup resistor to the output rail (external MOSFET source) or any other voltage to be
monitored.
13
GATE
Gate drive output
14
SENSE
Current sense input
The voltage across the current sense resistor (RS) is measured from VIN to this pin. If the
voltage across RS reaches over-current threshold, the load current is limited and the fault
timer activates.
15
VIN
Positive supply input
A small ceramic bypass capacitor close to this pin is recommended to suppress transients
which occur when the load current is switched off.
16
UVLO/EN
Under-voltage lockout
An external resistor divider from the system input voltage sets the under-voltage turn-on
threshold. An internal 23 µA current source provides hysteresis. The enable threshold at
the pin is 1.16V. This pin can also be used for remote shutdown control.
17
OVLO
Over-voltage lockout
An external resistor divider from the system input voltage sets the over-voltage turn-off
threshold. An internal 23 µA current source provides hysteresis. The disable threshold at
the pin is 1.16V.
18
GND
Circuit ground
19
SDA
SMBus data pin
Data pin for SMBus.
Clock pin for SMBus.
20
SCL
SMBus clock
21
SMBA
SMBus alert line
22
VREF
Internal Reference
23
DIODE
External diode
24
VAUX
Auxiliary voltage input
Alert pin for SMBus, active low.
Internally generated precision 2.73V reference used for analog to digital conversion.
Connect a 1 µF capacitor on this pin to ground for bypassing.
Connect this to a diode-configured NPN transistor for temperature monitoring.
Auxiliary pin allows voltage telemetry from an external source. Full scale input of 1.16V.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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SNVS824C – JUNE 2012 – REVISED MARCH 2013
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Absolute Maximum Ratings (1)
VIN, SENSE to GND
(2)
-0.3V to 24V
GATE, FB, UVLO/EN, OVLO, PGD to GND
(2)
-0.3V to 20V
Out to GND
-1 to 20V
SCL, SDA, SMBA, CL, CB, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY to GND
-0.3V to 6V
VIN to SENSE
-0.3V to +0.3V
ESD Rating, Human Body Model (3)
2kV
Storage Temperature
-65°C to +150°C
Junction Temperature
+150°C
(1)
(2)
(3)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional.
The GATE pin voltage is typically 7.5V above VIN when the LM25066I/A is enabled. Therefore, the Absolute Maximum Rating of 24V for
VIN and SENSE apply only when the LM25066I/A is disabled or for a momentary surge to that voltage since the Absolute Maximum
Rating for the GATE pin is 20V.
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Operating Ratings
VIN, SENSE, OUT voltage
2.9V to 17V
VDD
2.9V to 5.5V
−40°C to +125°C
Junction Temperature
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +85°C unless otherwise stated. Minimum and Maximum limits are specified through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12V. See (1) and
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input (VIN Pin)
IIN-EN
Input Current, enabled
UVLO = 2V and OVLO = 0.7V
5.8
8
mA
POR
Power On Reset threshold at VIN
VIN increasing
2.6
2.8
V
POREN Hysteresis
VIN decreasing
150
PORHYS
mV
VDD Regulator (VDD pin)
VDD
VDDILIM
IVDD = 5mA, VIN = 12V
4.3
4.5
4.7
IVDD = 5mA, VIN = 4.5V
3.5
3.9
4.3
25
45
1.147
1.16
1.173
V
18
23
28
µA
VDD Current Limit
V
V
mA
UVLO/EN, OVLO Pins
UVLOTH
UVLO threshold
VUVLO Falling
UVLOHYS
UVLO hysteresis current
UVLO = 1V
UVLODEL
UVLO delay
Delay to GATE high
8
Delay to GATE low
20
UVLOBIAS
µs
UVLO bias current
UVLO = 3V
OVLOTH
OVLO threshold
VOVLO rising
1.141
1.16
1.185
V
OVLOHYS
OVLO hysteresis current
OVLO = 1V
-28
-23
-18
µA
OVLODEL
OVLO delay
Delay to GATE high
19
Delay to GATE low
9
OVLOBIAS
OVLO bias current
1
OVLO = 1V
µA
µs
1
µA
60
mV
1
µA
Power Good (PGD pin)
(1)
4
PGDVOL
Output low voltage
ISINK = 2 mA
PGDIOH
Off leakage current
VPGD = 17V
PGDDELAY
Power Good Delay
VFB to VPG
25
115
ns
Current out of a pin is indicated as a negative value.
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SNVS824C – JUNE 2012 – REVISED MARCH 2013
Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +85°C unless otherwise stated. Minimum and Maximum limits are specified through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12V. See (1) and
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.141
1.167
1.19
V
-31
-24
-18
µA
1
µA
15
mV
FB Pin
FBTH
FB Threshold
FBHYS
FB Hysteresis Current
FBLEAK
Off Leakage Current
VFB rising
VFB = 1V
Power Limit (PWR Pin)
PWRLIM
IPWR
RSAT(PWR)
Power limit sense voltage (VIN-SENSE)
SENSE-OUT = 12V, RPWR = 25 kΩ
9
12.5
PWR pin current
VPWR = 2.5V
-10
µA
PWR pin impedance when disabled
UVLO = 0.7V
180
Ω
Gate Control (GATE Pin)
IGATE
VGATE
Source current
Normal operation
-28
-22
-16
µA
Fault Sink current
UVLO = 1V
1.5
POR Circuit Breaker sink current
VIN - SENSE = 150 mV or VIN < RPOR,
VGATE = 5V
105
2
2.5
mA
190
275
mA
Gate output voltage in normal operation
GATE voltage with respect to ground
17
18.8
20.3
V
OUT bias current, enabled
OUT = VIN, normal operation
16
µA
Disabled, OUT = 0V, SENSE = VIN
-12
µA
OUT Pin
IOUT-EN
IOUT-DIS
OUT bias current, disabled
(2)
Current Limit
VCL
tCL
ISENSE
Threshold voltage
CL = GND
22.5
25
27.5
CL = GND, TJ = 10°C to 85°C
23
25
27
CL = VDD
41
46
52
mV
Response time
VIN-SENSE stepped from 0 mV to 80 mV
1.2
µs
SENSE input current
Enabled, SENSE = OUT
33
µA
Disabled, OUT = 0V
46
Enabled, OUT = 0V
45
Circuit Breaker
VCB
VCB
tCB
Threshold voltage x 1.8
VIN - SENSE, CL = GND, CB = GND
35
45
55
CB:CL Ratio
CB = GND
1.6
1.8
2
mV
Threshold voltage x 3.6
VIN - SENSE, CL = GND, CB = VDD
70
90
110
CB:CL Ratio
CB = VDD
3.1
3.6
4
Response time
VIN - SENSE stepped from 0 mV to 150
mV, time to GATE low, no load
0.6
1.2
µs
1.54
1.7
1.85
V
0.85
1.0
1.07
V
mV
Timer (TIMER pin)
VTMRH
Upper threshold
VTMRL
Lower threshold
ITIMER
(2)
Restart cycles
Insertion time current
End of 8th cycle
0.3
V
Re-enable threshold
0.3
V
-8
-5.5
-3
µA
Sink current, end of insertion time
TIMER pin = 2V
1.4
1.9
2.4
mA
Fault detection current
-120
-90
-60
µA
Fault sink current
2.8
DCFAULT
Fault Restart Duty Cycle
0.67
%
tFAULT_DELAY
Fault to GATE low delay
17
µs
TIMER pin reaches the upper threshold
µA
OUT bias current (disabled) due to leakage current through an internal 0.9 MΩ resistance from SENSE to VOUT.
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Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +85°C unless otherwise stated. Minimum and Maximum limits are specified through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12V. See (1) and
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.703
2.73
2.757
V
Internal Reference
VREF
Reference Voltage
ADC and MUX
Resolution
12
Bits
Integral Non-Linearity
ADC only
+/-1
LSB
tAQUIRE
Acquisition + Conversion Time
Any channel
100
µs
tRR
INL
6
Acquisition Round Robin Time
Cycle all channels
1
ms
IINFSR
Current input full scale range
CL = GND
30.2
mV
CL = VDD
60.4
mV
IINLSB
Current input LSB
CL = GND
7.32
µV
CL = VDD
14.64
µV
VAUXFSR
VAUX input full scale range
1.16
V
VAUXLSB
VAUX input LSB
283.2
µV
VINFSR
Input voltage full scale range
18.7
V
VINLSB
Input voltage LSB
4.54
mV
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SNVS824C – JUNE 2012 – REVISED MARCH 2013
Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +85°C unless otherwise stated. Minimum and Maximum limits are specified through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12V. See (1) and
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
+1
%
Telemetry Accuracy LM25066IA
IINACC
VACC
PINACC
Input Current Accuracy
VAUX, VIN, VOUT Accuracy
Input Power Accuracy
VIN – SENSE = 25mV, CL = GND
TJ = 10°C to 85°C
-1
VIN – SENSE = 25mV, CL = GND
-1.2
+1
VIN – SENSE = 50mV, CL = VDD
-1.8
+1.8
VIN- SENSE= 5mV, CL= GND
TJ = 10°C to 85°C
-5
+5
VIN, VOUT = 12V
VAUX = 1V
TJ = 10°C to 85°C
-1
+1
VIN, VOUT = 12V
VAUX = 1V
-1
+1.2
VIN = 12V, VIN – SENSE = 25mV,
CL = GND
-2.0
+2.0
%
VIN – SENSE = 25mV, CL = GND
-2.7
+2.4
%
VIN – SENSE = 25mV, CL = GND
TJ = 10°C to 85°C
-2.4
+2.4
VIN, VOUT = 12V
VAUX = 1V
-1.6
+1.4
VIN, VOUT = 12V
VAUX = 1V
TJ = 10°C to 85°C
-1.4
+1.4
VIN = 12V, VIN – SENSE = 25mV,
CL = GND
-3.0
+3.0
%
10
°C
%
Telemetry Accuracy LM25066I
IINACC
VACC
PINACC
Input Current Accuracy
VAUX, VIN, VOUT Accuracy
Input Power Accuracy
%
Remote Diode Temperature Sensor
TACC
Temperature Accuracy Using Local
Diode
TA = 10°C to 85°C
2
Remote Diode Resolution
IDIODE
9
External Diode Current Source
High level
250
Low level
9.4
Diode Current Ratio
bits
300
µA
µA
26
PMBus Pin Thresholds (SMBA, SDA, SCL)
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
VOL
Data Output Low Voltage
IPULLUP = 4mA
ILEAK
Input Leakage Current
SDA, SMBA, SCL = 5V
Pin Capacitance
SDA, SCL
CL
0.8
V
2.1
5.5
V
0
0.4
V
1
µA
5
pF
Configuration Pin Thresholds (CB, CL, RETRY)
VIH
ILEAK
Thermal
(3)
Threshold Voltage
3
Input Leakage Current
V
CL, CB, RETRY = 5V
1
mA
(3)
θJA
Junction to Ambient
42.3
°C/W
θJC
Junction to Case
9.5
°C/W
Junction-to-ambient thermal resistance is highly application and board layout dependent. Specified thermal resistance values for the
package specified is based on a 4-layer, 4"x3", 2/1/1/2 oz. Cu board as per JEDEC standards is used.
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Typical Performance Characteristics
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V. All graphs show junction temperature.
VIN Pin Current
5.5
SENSE Pin Current (Enabled)
VIN = 17V
5.0
VIN = 12V
4.5
4.0
VIN = 3V
3.5
3.0
-40 -20
0
20 40 60 80 100 120 140
54
SENSE PIN CURRENT (ENABLED) ( A)
VIN INPUT CURRENT (mA)
6.0
50
VIN = 17V
46
VIN = 12V
42
38
VIN = 2.9V
34
30
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 1.
Figure 2.
50
VIN = 17V
48
46
44
VIN = 12V
42
40
38
VIN = 2.9V
36
34
-40 -20
OUT Pin Current (Enabled)
OUTPUT PIN CURRENT (ENABLED) ( A)
SENSE PIN CURRENT (DISABLED) ( A)
SENSE Pin Current (Disabled)
52
28
24
VIN = 17V
20
16
VIN = 12V
12
8
VIN = 2.9V
4
0 20 40 60 80 100 120
TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 3.
Figure 4.
GATE Pin Voltage
20
VIN = 17V
-4
VIN = 17V
-6
-8
VIN = 12V
-10
-12
-14
18
GATE PIN VOLTAGE (V)
OUTPUT PIN CURRNET (DISABLED) ( A)
OUT Pin Current (Disabled)
-2
VIN = 12V
16
VIN = 9V
14
VIN = 5V
12
10
8
-16
VIN = 2.9V
VIN = 2.9V
-18
6
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 5.
8
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Figure 6.
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SNVS824C – JUNE 2012 – REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V. All graphs show junction temperature.
GATE Pin Source Current
Power Limit Threshold
24
POWER LIMIT THRESHOLD (mV)
GATE PIN SOURCE CURRENT ( A)
23
22
21
20
VIN = 5V TO 17V
19
18
17
VIN = 2.9V
16
15
20
RPWR
16
12
14
8
RPWR
4
0 20 40 60 80 100 120 140
TEMPERATURE (°C)
-40 -20
Figure 7.
0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 8.
PGD Low Voltage
UVLO Threshold
42
1.17
38
UVLO THRESHOLD (V)
PGD LOW VOLTAGE (mV)
=25K; CL = GND
0
-40 -20
34
30
26
VIN = 2.9 to 12V
1.16
VIN = 17V
22
PGD Sink Current = 2mA
18
-60 -40 -20 0 20 40 60 80 100120140
1.15
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9.
Figure 10.
UVLO Hysteresis Current
FB Threshold
24.0
1.172
1.171
23.8
1.170
FB THRESHOLD (V)
UVLO HYSTERESIS CURRENT ( A)
=50K; CL = VDD
1.169
23.6
1.168
1.167
23.4
1.166
1.165
23.2
1.164
1.163
23.0
-60 -40 -20 0 20 40 60 80 100120140
1.162
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11.
Figure 12.
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Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V. All graphs show junction temperature.
OVLO Threshold
OVLO Hysteresis
-16
OVLO HYSTERESIS CURRENT ( A)
1.167
OVLO THRESHOLD (V)
VIN = 2.9V
1.166
VIN = 12V
1.165
1.164
1.163
VIN = 17V
1.162
-18
-20
-22
VIN = 12V to 17V
-24
-26
-28
-30
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 13.
Figure 14.
FB Pin Hysteresis
Current Limit Threshold
27.0
CURRENT LIMIT THRESHOLD (mV)
-23.0
FB HYSTERESIS ( A)
-23.5
-24.0
-24.5
-25.0
-25.5
26.5
26.0
25.5
VIN = 5V to 17V
25.0
24.5
24.0
VIN = 2.9V
23.5
23.0
-26.0
-60 -40 -20 0 20 40 60 80 100120140
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15.
Figure 16.
CURRENT LIMIT THRESHOLD (mV)
49
48
47
VIN = 5V to 17V
46
45
44
VIN = 2.9V
43
42
41
40
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Circuit Breaker Threshold (CL = VDD)
CIRCUIT BREAKER THRESHOLD (mV)
Current Limit Threshold
50
200
180
160
CL = VDD, CB = VDD
140
120
CL = GND, CB = VDD
100
80
60
CL = GND, CB = GND
40
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
Figure 17.
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Figure 18.
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Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V. All graphs show junction temperature.
Reference Voltage
Startup (Insertion Delay)
2.75
INSERTION DELAY = 140 ms
VREF (V)
2.74
2.73
2.72
TIMER
1V/DIV
VIN
10V/DIV
10V/DIV
GATE
2.71
VOUT
10V/DIV
2.70
100 ms/DIV
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
Figure 19.
Figure 20.
Startup (Short circuit VOUT)
Startup (5A Load)
TIMER
1V/DIV
TIMER
VIN
1V/DIV
10V/DIV
RETRY PERIOD = 1.10s
GATE
10V/DIV
10V/DIV
GATE
10V/DIV
VOUT
VOUT
10V/DIV
2.5A/DIV
ILOAD
1 ms/DIV
400 ms/DIV
Figure 21.
Figure 22.
Startup (UVLO, OVLO)
Startup (PGOOD)
PGOOD
5V/DIV
OVLO = 15.2V
GATE
VIN
hyst = 1.2V
5V/DIV
10.7V
10.25V
5V/DIV
VIN
hyst = 0.2V
VOUT
UVLO = 2.9V
40 ms/DIV
40 ms/DIV
Figure 23.
Figure 24.
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Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V. All graphs show junction temperature.
Current Limit Event (CL = GND)
Circuit Breaker Event (CL = CB = GND)
1V/DIV
TIMER
TIMER
TIMEOUT PERIOD
= 8.3 ms
GATE
1V/DIV
GATE
10V/DIV
VOUT
10V/DIV
VOUT
10V/DIV
>50A
10V/DIV
ILOAD
> 90A Triggers
Circuit Breaker
25A/DIV
ILOAD
50A/DIV
1 ms/DIV
4 ms/DIV
Figure 25.
Figure 26.
Retry Event (Retry = GND)
Latch Off (Retry = VDD)
RETRY PERIOD = 1.1s
1V/DIV
TIMER
TIMER
1V/DIV
GATE
10V/DIV
VOUT
VOUT
10V/DIV
ILOAD
10V/DIV
ILOAD
25A/DIV
25A/DIV
100 ms/DIV
Figure 27.
Figure 28.
IIN Measurement Accuracy
(VIN - SENSE = 25 mV)
PIN Measurement Accuracy
(VIN - SENSE = 25 mV)
0.5
1.0
0.4
0.8
0.3
0.6
PIN ERROR (% OF FSR)
IIN ERROR ( % OF FSR)
400 ms/DIV
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-0.5
-15 -5
0.4
-1.0
5 15 25 35 45 55 65 75 85
TEMPERATURE ( °C)
-15 -5
Figure 29.
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5 15 25 35 45 55 65 75 85
TEMPERATURE (°C)
Figure 30.
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SNVS824C – JUNE 2012 – REVISED MARCH 2013
24 A
LM25066I/A
VDD
REG
VDD
REF
GEN
1.167V
UV
OV
S/H
AMUX
1/16
ID
25 mV
VAUX
1M
SCL
SMBUS
INTERFACE
VDS
10 A
Diode
Temp
Sense
Gate
Control
2 mA
190
mA
Power Limit
Threshold
GATE
18.8V
Current Limit/
Power Limit
Control
5.5 A
Insertion
Timer
SnapShot
MEASUREMENT/
AVERAGING
FAULT REGISTERS
SDA
22 A
Current Limit
Threshold
Gain = 2.3V/V
DIODE
Charge
Pump
1/16
12bit
ADC
VREF
PGD
FB
OUT
SENSE
VIN
BLOCK DIAGRAM
90 A
23 A
Fault
Timer
TIMER
TELEMETRY
STATE
MACHINE
1.16V
TIMER AND GATE
LOGIC CONTROL
1.16V
SMBA
1.9 mA
End
Insertion
Time
2.8 A
Fault
Discharge
1.72V
ADDRESS
DECODER
1.0V
23 A
0.3V
2.5V
ADR0
VDD
ADR1
POR
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RETRY
CB
GND
UVLO/EN
PWR
OVLO
ADR2
CL
2.6V
VIN
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FUNCTIONAL DESCRIPTION
The inline protection functionality of the LM25066I/A is designed to control the in-rush current to the load upon
insertion of a circuit card into a live backplane or other “hot” power source, thereby limiting the voltage sag on the
backplane’s supply voltage and the dV/dt of the voltage applied to the load. Effects on other circuits in the
system are minimized, preventing possible unintended resets. A controlled shutdown when the circuit card is
removed can also be implemented using the LM25066I/A.
In addition to a programmable current limit, the LM25066I/A monitors and limits the maximum power dissipation
in the series pass device to maintain operation within the device Safe Operating Area (SOA). Either current
limiting or power limiting for an extended period of time results in the shutdown of the series pass device. In this
event, the LM25066I/A can latch off or repetitively retry based on the hardware setting of the RETRY pin. Once
started, the number of retries can be set to none, 1, 2, 4, 8, 16, or infinite. The circuit breaker function quickly
switches off the series pass device upon detection of a severe over-current condition. Programmable undervoltage lockout (UVLO) and over-voltage lockout (OVLO) circuits shut down the LM25066I/A when the system
input voltage is outside the desired operating range.
The telemetry capability of the LM25066I/A provides intelligent monitoring of the input voltage, output voltage,
input current, input power, temperature, and an auxiliary input. The LM25066I/A also provides a peak capture of
the input power and programmable hardware averaging of the input voltage, current, power, and output voltage.
Warning thresholds which trigger the SMBA pin may be programmed for input and output voltage, current, power
and temperature via the PMBus interface. Additionally, the LM25066I/A is capable of detecting damage to the
external MOSFET, Q1.
Q2
VIN
CIN
VOUT
RS
Q1
DZ
R1
VIN
SENSE
CLOAD
GATE
OUT
R4
DIODE
UVLO/EN
UVLO/EN
R2
FB
VDD
R5
OVLO
R3
RPG
VDD
ADR2
N/C
ADR1
N/C
ADR0
PGD
LM25066I/A
VAUX
RETRY
SMBA
SMBus
Interface
Auxillary ADC Input
(0V - 1.16V)
CB
SDA
CL
SCL
VDD
CVDD
VREF
CVREF
GND
TIMER
PWR
RPWR
CT
Figure 31. Typical Application Circuit
Power Up Sequence
The VIN operating range of the LM25066I/A is +2.9V to +17V, with transient capability to +24V. Referring to
Figure 31 and Figure 32, as the voltage at VIN initially increases, the external N-channel MOSFET (Q1) is held
off by an internal 190 mA pulldown current at the GATE pin. The strong pulldown current at the GATE pin
prevents an inadvertent turn-on as the MOSFET’s gate-to-drain (Miller) capacitance is charged. Additionally, the
TIMER pin is initially held at ground. When the VIN voltage reaches the POR threshold, the insertion time begins.
During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 5.5 µA current source and Q1 is
held off by a 2 mA pulldown current at the GATE pin regardless of the input voltage. The insertion time delay
allows ringing and transients at VIN to settle before Q1 is enabled. The insertion time ends when the TIMER pin
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voltage reaches 1.7V. CT is then quickly discharged by an internal 1.9 mA pulldown current. The GATE pin then
switches on Q1 when VSYS, the input supply voltage, exceeds the UVLO threshold. If VSYS is above the UVLO
threshold at the end of the insertion time, Q1 switches on at that time. The GATE pin charge pump sources 22
µA to charge the gate capacitance of Q1. The maximum voltage at the GATE pin with respect to ground is limited
by an internal 18.8V zener diode.
As the voltage at the OUT pin increases, the LM25066I/A monitors the drain current and power dissipation of
MOSFET Q1. Inrush current limiting and/or power limiting circuits actively control the current delivered to the
load. During the inrush limiting interval (t2 in Figure 32), an internal 90 µA fault timer current source charges CT.
If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER
pin reaches 1.7V, the 90 µA current source is switched off and CT is discharged by the internal 2.8 µA current
sink (t3 in Figure 32). The PGD pin switches high when FB exceeds its rising threshold of 1.167V.
If the TIMER pin voltage reaches 1.7V before inrush current limiting or power limiting ceases during t2, a fault is
declared and Q1 is turned off. See Fault Timer and Restart for a complete description of the fault mode.
The LM25066I/A will pull the SMBA pin low after the input voltage has exceeded its POR threshold to indicate
that the volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the
STATUS_MFR_SPECIFIC register (80h) indicates default configuration of warning thresholds and device
operation and will remain set until a CLEAR_FAULTS command is received.
VSYS
VIN
UVLO
POR
1.7V
5.5 PA
90 PA
2.8 PA
TIMER
Pin
GATE
Pin
190 mA
pull-down
2 mA pull-down
22 PA source
ILIMIT
Load
Current
Output
Voltage
(OUT Pin)
PGD
t1
Insertion Time
t2
t3
In rush
Limiting
Normal Operation
Figure 32. Power Up Sequence (Current Limit Only)
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Gate Control
A charge pump provides the voltage at the GATE pin to enhance the N-Channel MOSFET’s gate. During normal
operating conditions (t3 in )Figure 32) the gate of Q1 is held charged by an internal 22 µA current source. The
voltage at the GATE pin (with respect to ground) is limited by an internal 18.8 V zener diode. See the graph
“GATE Pin Voltage” shown previously. Since the gate-to-source voltage applied to Q1 could be as high as 18.8 V
during various conditions, a zener diode with the appropriate voltage rating must be added between the GATE
and OUT pins if the maximum VGS rating of the selected MOSFET is less than 18.8 V. The external zener diode
must have a forward current rating of at least 190 mA. When the system voltage is initially applied, the GATE pin
is held low by a 190 mA pulldown current. This helps prevent an inadvertent turn-on of the MOSFET through its
drain-gate capacitance as the applied system voltage increases.
During the insertion time (t1 in Figure 32) the GATE pin is held low by a 2 mA pulldown current. This maintains
Q1 in the off-state until the end of t1, regardless of the voltage at VIN or UVLO. Following the insertion time (t2 in
Figure 32), the gate voltage of Q1 is controlled to keep the current or power dissipation level from exceeding the
programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is charging. If the
current and power limiting cease before the TIMER pin reaches 1.7V, the TIMER pin capacitor then discharges,
and the circuit begins normal operation. If the inrush limiting condition persists such that the TIMER pin reached
1.7V during t2, the GATE pin is then pulled low by the 190 mA pulldown current. The GATE pin is then held low
until either a power up sequence is initiated (RETRY pin to VDD), or an automatic retry is attempted (RETRY pin
to GROUND). See Fault Timer and Restart. If the system input voltage falls below the UVLO threshold or rises
above the OVLO threshold, the GATE pin is pulled low by the 2 mA pulldown current to switch off Q1.
Current Limit
The current limit threshold is reached when the voltage across the sense resistor RS (VIN to SENSE) exceeds
the internal voltage limit of 25 mV or 46 mV depending on whether the CL pin is connected to GND or VDD,
respectively. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1.
While the current limit circuit is active, the fault timer is active as described in Fault Timer and Restart. If the load
current falls below the current limit threshold before the end of the Fault Timeout Period, the LM25066I/A
resumes normal operation. If the current limit condition persists for longer than the Fault Timeout Period set by
the timer capacitor, CT, the IIN OC FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the
STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h)
register will be toggled high and SMBA pin will be pulled low unless this feature is disabled using the
ALERT_MASK (D8h) register. For proper operation, the RS resistor value should be less than 200 mΩ. Higher
values may create instability in the current limit control loop. The current limit threshold pin value may be
overridden by setting appropriate bits in the DEVICE_SETUP register (D9h).
Circuit Breaker
If the load current increases rapidly (e.g. the load is short circuited), the current in the sense resistor (RS) may
exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds
1.8 or 3.6 times (user settable) the current limit threshold, Q1 is quickly switched off by the 190 mA pulldown
current at the GATE pin, and a Fault Timeout Period begins. When the voltage across RS falls below the
threshold the 190 mA pulldown current at the GATE pin is switched off and the gate voltage of Q1 is then
determined by the current limit or power limit functions. If the TIMER pin reaches 1.7V before the current limiting
or power limiting condition ceases, Q1 is switched off by the 2 mA pulldown current at the GATE pin as described
in Fault Timer and Restart. A circuit breaker event will cause the CIRCUIT BREAKER FAULT bit in the
STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin will
be pulled low unless this feature is disabled using the ALERT_MASK (D8h) register. The circuit breaker pin
configuration may be overridden by setting appropriate bits in the DEVICE_SETUP (D9h) register.
Power Limit
An important feature of the LM25066I/A is the MOSFET power limiting. The Power Limit function can be used to
maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM25066I/A
determines the power dissipation in Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain
current through RS (VIN to SENSE). The product of the current and voltage is compared to the power limit
threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the
GATE voltage is controlled to regulate the current in Q1. While the power limiting circuit is active, the fault timer is
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active as described in Fault Timer and Restart. If the power limit condition persists for longer than the Fault
Timeout Period set by the timer capacitor, CT, the IIN_OC_FAULT bit in the STATUS_INPUT (7Ch) register, the
INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the
DIAGNOSTIC_WORD (E1h) register will be toggled high and SMBA pin will be pulled low unless this feature is
disabled using the ALERT_MASK (D8h) register.
Fault Timer and Restart
When the current limit or power limit threshold is reached during turn-on, or as a result of a fault condition, the
gate-to-source voltage of Q1 is controlled to regulate the load current and power dissipation in Q1. When either
limiting function is active, a 90 µA fault timer current source charges the external capacitor (CT) at the TIMER pin
as shown in Figure 32 (Fault Timeout Period). If the fault condition subsides during the Fault Timeout Period
before the TIMER pin reaches 1.7V, the LM25066I/A returns to the normal operating mode and CT is discharged
by the 1.9 mA current sink. If the TIMER pin reaches 1.7V during the Fault Timeout Period, Q1 is switched off by
a 2 mA pulldown current at the GATE pin. The subsequent restart procedure then depends on the selected retry
configuration.
If the RETRY pin is high, the LM25066I/A latches the GATE pin low at the end of the Fault Timeout Period. CT is
then discharged to ground by the 2.8 µA fault current sink. The GATE pin is held low by the 2 mA pulldown
current until a power up sequence is externally initiated by cycling the input voltage (VSYS), or momentarily pulling
the UVLO/EN pin below its threshold with an open-collector or open-drain device as shown in Figure 33. The
voltage at the TIMER pin must be
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