LM48556TLBD

LM48556 www.ti.com SNAS452B – JUNE 2008 – REVISED MAY 2013 LM48556 Boomer™ Fully Differential, Mono, Ceramic Speaker Driver Check for Samples: LM48556 FEATURES DESCRIPTION • • • • • The LM48556 is a single supply, mono, ceramic speaker driver with an integrated charge-pump, designed for portable devices, such as cell phones, where board space is at a premium. The LM48556 charge pump allows the device to deliver 17.5VPP (typ) from a single 4.5V supply. Additionally, the charge pump features a soft start function that minimizes transient current during power-up. 1 23 Fully Differential Amplifier Externally Configurable Gain Integrated Charge Pump Low Power Shutdown Mode Soft Start Function APPLICATIONS • • • Mobile Phones PDA's Digital Cameras KEY SPECIFICATIONS • • • • Output Voltage Swing – VDD = 3.6V, 1kHz 14.2VPP (typ) – VDD = 4.5V, 1kHz 17.5VPP (typ) Power Supply Rejection Ratio – f = 217Hz, VDD = 3.6V 80dB (typ) IDD at VDD = 3.6V 4.8mA (typ) Wake-Up Time 0.5ms (typ) The LM48556 features high power supply rejection ratio (PSRR) of 80dB at 217Hz, allowing the device to operate in noisy environments without additional power supply conditioning. Flexible power supply requirements allow operation from 2.7V to 5.0V. Additionally, the LM48556 features a differential input function and an externally configurable gain. A low power shutdown mode reduces supply current consumption to 0.1μA. Superior click and pop suppression eliminates audible transients on power-up/down and during shutdown. The LM48556 is available in an ultra-small 12-bump DSBGA package (2mm x 1.5mm). 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Boomer is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated LM48556 SNAS452B – JUNE 2008 – REVISED MAY 2013 www.ti.com TYPICAL APPLICATION R F200 k: C FR F+ 82 pF 200 k: VDD C F+ 82 pF C S1 C S2 0.1 PF 4.7 PF RIN+ C IN+ SVDD PVDD 0.47 P F 20 k: IN+ RO 15: OUT- CL 1 PF OUT+ INC IN- R IN- Ceramic Speaker Load 0.47 PF 20 k: C1P SHUTDOWN SD Shutdown Control Charge Pump C1 4.7 PF C1N CPVSS PGND SVSS C SS 10 PF Figure 1. Typical Audio Amplifier Application Circuit Connection Diagram A B C D 3 IN+ IN- SD PVDD 2 SVDD OUT+ C1P PGND 1 OUT- SVSS CPVSS C1N Figure 2. 12 Bump DSBGA - Top View See Package Number YZR00121AA 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM48556 LM48556 www.ti.com SNAS452B – JUNE 2008 – REVISED MAY 2013 Figure 3. 12 Bump DSBGA - Package View BUMP DESCRIPTIONS Bump Name A1 OUT- Amplifier Inverting Output Description A2 SVDD Signal Power Supply - Positive A3 IN+ B1 SVSS Amplifier Non-inverting Input Signal Power Supply - Negative B2 OUT+ Amplifier Non-inverting Output B3 IN- C1 CPVSS C2 C1P Charge Pump Flying Capacitor Positive Terminal C3 SD Active Low Reset Input. Connect to VDD for normal operation. Drive SD low to disable. Amplifier Inverting Input Charge Pump Output Voltage D1 C1N D2 PGND Charge Pump Flying Capacitor Negative Terminal Power Ground D3 PVDD Power Supply Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM48556 3 LM48556 SNAS452B – JUNE 2008 – REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage (SVDD, PVDD) (1) 5.25V −65°C to +150°C Storage Temperature −0.3V to VDD + 0.3V Input Voltage Power Dissipation (4) Internally limited ESD Rating (5) 2000V ESD Rating (6) 200V Junction Temperature 150°C θJA (YZR) Thermal Resistance 114°C/W Soldering Information (1) (2) (3) (4) (5) (6) See AN-1112 (SNVA009) Micro SMD Wafer Level Chip Scale “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. Human body model, applicable std. JESD22-A114C. Machine model, applicable std. JESD22-A115-A. Operating Ratings Temperature Range TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ +85°C 2.7V ≤ _VDD ≤ 5.0V Supply Voltage (SVDD, PVDD) Electrical Characteristics VDD = 3.6V (1) The following specifications apply for VDD = 3.6V, AV-BTL = 20dB (R F = 200kΩ, RIN = 20kΩ), ZL = 15Ω+1μF, unless otherwise specified. Limits apply for TA = 25°C. Symbol Parameter LM48556 Conditions Typical (2) Limit (3) Units (Limits) IDD Quiescent Power Supply Current VIN = 0V 4.8 7 mA (max) ISD Shutdown Current VSD = GND (Note 8) 0.1 1 µA (max) VOS Output Offset Voltage CIN = 0.47μF, AV = 1V/V (0dB) 0.6 4 mV (max) TWU Wake-up Time VOUT Output Voltage Swing THD+N Total Harmonic Distortion + Noise 0.5 ms THD+N = 1% (max); f = 1kHz 14.2 VPP THD+N = 1% (max); f = 10kHz 11.5 11 VPP (min) VOUT = 11VPP, f = 1kHz AV = 0dB 0.005 % AV = 20dB 0.03 % μV εOS Output Noise A-weighted filter, VIN = 0V Input referred 8 PSRR Power Supply Rejection Ratio VRIPPLE = 200mVPP, f = 217Hz 80 (1) (2) (3) 4 60 dB (min) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Datasheet min/max specification limits are specified by test or statistical analysis. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM48556 LM48556 www.ti.com SNAS452B – JUNE 2008 – REVISED MAY 2013 Electrical Characteristics VDD = 3.6V(1) (continued) The following specifications apply for VDD = 3.6V, AV-BTL = 20dB (R F = 200kΩ, RIN = 20kΩ), ZL = 15Ω+1μF, unless otherwise specified. Limits apply for TA = 25°C. Symbol Parameter Conditions Input Referred LM48556 Typical (2) Limit (3) Units (Limits) 60 dB (min) CMRR Common Mode Rejection Ratio VLH Logic High Threshold Voltage 70 1.2 V (min) VLL Logic Low Threshold Voltage 0.45 V (max) Electrical Characteristics VDD = 4.5V (1) The following specifications apply for VDD = 4.5V, AV-BTL = 20dB (R F = 200kΩ, RIN = 20kΩ), ZL = 15Ω+1μF, unless otherwise specified. Limits apply for TA = 25°C. Symbol Parameter Conditions LM48556 Typical (2) Limit (3) Units (Limits) IDD Quiescent Power Supply Current VIN = 0V 6.5 10 mA (max) ISD Shutdown Current VSD = GND (Note 8) 0.1 1 µA (max) VOS Output Offset Voltage CIN = 0.47μF, AV = 1V/V (0dB) 0.6 4 mV (max) TWU Wake-up Time VOUT Output Voltage Swing 0.5 ms (max) THD+N = 1% (max); f = 1kHz 17.5 VPP THD+N = 1% (max); f = 10kHz 14.6 14 VPP (min) VOUT = 14VPP, f = 1kHz THD+N Total Harmonic Distortion + Noise AV = 0dB 0.005 % AV = 20dB 0.03 % 8 μV εOS Output Noise A-weighted filter, VIN = 0V Input referred PSRR Power Supply Rejection Ratio VRIPPLE = 200mVPP, f = 217Hz, 80 CMRR Common Mode Rejection Ratio Input Referred 70 VLH Logic High Threshold Voltage 1.2 V (min) VLL Logic Low Threshold Voltage 0.45 V (max) (1) (2) (3) 60 dB (min) 60 dB (min) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Datasheet min/max specification limits are specified by test or statistical analysis. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM48556 5 LM48556 SNAS452B – JUNE 2008 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics ( ZL = 15Ω+1μF, AV = 20dB, BW = 22kHz) THD+N vs Frequency VDD = 2.7V, VO = 8VPP 10 10 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 0.001 20 200 2k 0.001 20 20k 200 2k FREQUENCY (Hz) FREQUENCY (Hz) Figure 4. Figure 5. THD+N vs Frequency VDD = 4.5V, VO = 17.5VPP 10 10 1 0.1 20k THD+N vs Output Voltage Swing VDD = 2.7V, f = 1kHz f = 10 kHz 1 THD+N (%) THD+N (%) THD+N vs Frequency VDD = 3.6V, VO = 14.2VPP 0.1 f = 1 kHz 0.01 0.01 f = 100 Hz 0.001 20 200 2k 20k 0.001 10m 100m 1 10 FREQUENCY (Hz) OUTPUT VOLTAGE SWING (VRMS) Figure 7. THD+N vs Output Voltage Swing VDD = 3.6V, f = 1kHz THD+N vs Output Voltage Swing VDD = 4.5V, f = 1kHz THD+N (%) 1 10 f = 10 kHz 1 THD+N (%) 10 Figure 6. 0.1 f = 1 kHz f = 10 kHz 0.1 f = 1 kHz 0.01 0.01 f = 100 Hz 0.001 10m 100m f = 100 Hz 1 10 0.001 10m OUTPUT VOLTAGE SWING (VRMS) 1 10 OUTPUT VOLTAGE SWING (VRMS) Figure 8. 6 100m Figure 9. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM48556 LM48556 www.ti.com SNAS452B – JUNE 2008 – REVISED MAY 2013 Typical Performance Characteristics (continued) ( ZL = 15Ω+1μF, AV = 20dB, BW = 22kHz) CMRR vs Frequency VDD = 3.6V, Input referred 0 -10 -10 -20 -20 -30 -30 CMRR (dB) 0 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 200 2k 20k FREQUENCY (Hz) Figure 11. CMRR vs Frequency VDD = 4.5V, Input referred PSRR vs Frequency VDD = 2.7V, Input referred 0 0 -10 -20 -20 -30 -30 -40 -50 -60 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 200 2k 20k 200 2k Figure 13. PSRR vs Frequency VDD = 3.6V, Input referred PSRR vs Frequency VDD = 4.5V, Input referred 0 -10 -20 -20 -30 -30 PSRR (dB) 0 -10 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 2k 20k FREQUENCY (Hz) Figure 12. 200 20k -40 FREQUENCY (Hz) PSRR (dB) 2k Figure 10. -10 -100 20 200 FREQUENCY (Hz) PSRR (dB) CMRR (dB) CMRR (dB) CMRR vs Frequency VDD = 2.7V, Input referred 20k -100 20 FREQUENCY (Hz) 200 2k 20k FREQUENCY (Hz) Figure 14. Figure 15. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM48556 7 LM48556 SNAS452B – JUNE 2008 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) ( ZL = 15Ω+1μF, AV = 20dB, BW = 22kHz) Output Voltage vs Frequency VDD = 2.7V, THD+N = 1% 6.0 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) 4.00 3.75 3.50 3.25 3.00 10 100 Output Voltage vs Frequency VDD = 3.6V, THD+N = 1% 1k 5.5 5.0 4.5 4.0 10 10k 100 FREQUENCY (Hz) FREQUENCY (Hz) Figure 17. Output Voltage vs Frequency VDD = 4.5V, THD+N = 1% Supply Current vs Supply Voltage VIN = GND, No Load 6.5 6.5 6.0 6.0 5.5 5.5 5.0 4.5 4.0 2.7 5.0 10 100 1k 10k 3.0 3.3 3.6 3.9 4.2 4.5 SUPPLY VOLTAGE (V) FREQUENCY (Hz) Figure 18. Figure 19. Power Consumption vs Output Voltage Swing VDD = 2.7V, THD+N ≤ 1% Power Consumption vs Output Voltage Swing VDD = 3.6V, THD+N ≤ 1% 500 800 POWER CONSUMPTION (mW) POWER CONSUMPTION (mW) 450 400 350 f = 10 kHz 300 250 200 150 f = 1 kHz 100 50 0.00 700 600 500 f = 10 kHz 400 300 200 f = 1 kHz 100 0 0 1 2 3 4 OUTPUT VOLTAGE SWING (VRMS) Figure 20. 8 10k Figure 16. SUPPLY CURRENT (mA) OUTPUT VOLTAGE (VRMS) 7.0 1k 0 1 2 3 4 5 OUTPUT VOLTAGE SWING (VRMS) Figure 21. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM48556 LM48556 www.ti.com SNAS452B – JUNE 2008 – REVISED MAY 2013 Typical Performance Characteristics (continued) ( ZL = 15Ω+1μF, AV = 20dB, BW = 22kHz) Power Consumption vs Output Voltage Swing VDD = 4.5V, THD+N ≤ 1% POWER CONSUMPTION (mW) 1200 1000 800 f = 10 kHz 600 400 f = 1 kHz 200 0 0 1 2 3 4 5 OUTPUT VOLTAGE SWING (VRMS) Figure 22. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM48556 9 LM48556 SNAS452B – JUNE 2008 – REVISED MAY 2013 www.ti.com APPLICATION INFORMATION GENERAL AMPLIFIER FUNCTION The LM48556 is a fully differential ceramic speaker driver that utilizes TI’s inverting charge pump technology to deliver the high drive voltages required by ceramic speakers, without the need for noisy, board-space consuming inductive based regulators. The low-noise, inverting charge pump creates a negative supply (CPVSS) from the positive supply (PVDD). Because the amplifiers operate from these bipolar supplies, the maximum output voltage swing for each amplifier is doubled compared to a traditional single supply device. Additionally, the LM48556 is configured as a bridge-tied load (BTL) device, quadrupling the maximum theoretical output voltage range when compared to a single supply, single-ended output amplifier, see Bridge Configuration Explained section. The charge pump and BTL configuration allow the LM48556 to deliver over 17VP-P at 1kHz to a 1µF ceramic speaker while operating from a single 4.5V supply . DIFFERENTIAL AMPLIFIER EXPLANATION The LM48556 features a differential input stage, which offers improved noise rejection compared to a singleended input amplifier. Because a differential input amplifier amplifies the difference between the two input signals, any component common to both signals is cancelled. An additional benefit of the differential input structure is the possible elimination of the DC input blocking capacitors. Since the DC component is common to both inputs, and thus cancelled by the amplifier, the LM48556 can be used without input coupling capacitors when configured with a differential input signal. BRIDGE CONFIGURATION EXPLAINED The LM48556 is designed to drive a load differentially, a configuration commonly referred to as a bridge-tied load (BTL). The BTL configuration differs from the single-ended configuration, where one side of the load is connected to ground. A BTL amplifier offers advantages over a single-ended device. Driving the load differentially doubles the output voltage compared to a single-ended amplifier under similar conditions. Any component common to both outputs is cancelled, thus there is no net DC voltage across the load, eliminating the DC blocking capacitors required by single-ended, single-supply amplifiers. SHUTDOWN FUNCTION The LM48556 features a low current shutdown mode. Set SD = GND to disable the amplifier and reduce supply current to 0.1µA. Switch SD between VDD and GND for minimum current consumption in shutdown. The LM48556 may be disabled with shutdown voltages less than 0.45V, however, the idle current will be greater than the typical 0.1µA value. PROPER SELECTION OF EXTERNAL COMPONENTS Power Supply Bypassing/Filtering Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close to the device as possible. Place a 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VDD to GND. Additional bulk capacitance may be added as required. Charge Pump Capacitor Selection Use low ESR ceramic capacitors (less than 100mΩ) for optimum performance. Charge Pump Flying Capacitor (C1) The flying capacitor (C1) affects the load regulation and output impedance of the charge pump. A C1 value that is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C1 improves load regulation and lowers charge pump output impedance to an extent. Above 4.7µF, the RDS(ON) of the charge pump switches and the ESR of C1 and CSS dominate the output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. 10 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM48556 LM48556 www.ti.com SNAS452B – JUNE 2008 – REVISED MAY 2013 Charge Pump Hold Capacitor (CSS) The value and ESR of the hold capacitor (CSS) directly affects the ripple on CPVSS. Increasing the value of CSS reduces output ripple. Decreasing the ESR of CSS reduces both output ripple and charge pump output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. Gain Setting Resistor Selection The amplifier gain of the LM48556 is set by four external resistors, two per each input, RIN_ and RF_ Figure 1. The amplifier gain is given by Equation 1: AV = RF / RIN (V/V) (1) Careful matching of the resistor pairs, RF+ and RF-, and RIN+ and RIN-, is required for optimum performance. Any mismatch between the resistors results in a differential gain error that leads to an increase in THD+N, decrease in PSRR and CMRR, as well as an increase in output offset voltage. Resistors with a tolerance of 1% or better are recommended. The gain setting resistors should be placed as close to the device as possible. Keeping the input traces close together and of the same length increases noise rejection in noisy environments. Noise coupled onto the input traces which are physically close to each other will be common mode and easily rejected. Feedback Capacitor Selection Due to their capacitive nature, ceramic speakers poorly reproduce high frequency audio content. At high frequencies, a ceramic speaker presents a low impedance load to the amplifier, increasing the required drive current. The higher output current can drive the device into clipping, increasing THD+N. Low-pass filtering the audio signal improves audio quality by decreasing the signal amplitude at high frequencies, reducing the speaker drive current. Adding a capacitor in parallel with each feedback resistor creates a simple low-pass filter with the 3dB point determined by Equation 2: f−3dB = 1 / 2πRFCF (Hz) Where • • RF is the value of the feedback resistor determined by Equation 1 in the Gain Setting Resistor Selection section CF is the value of the feedback capacitor (2) The feedback capacitor is optional and not required for normal operation. Input Capacitor Selection Input capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of the audio source and the bias voltage of the LM48556. The input capacitors create a high-pass filter with the input resistors RIN. The -3dB point of the high pass filter is found using Equation 3 below. f = 1 / 2πRINCIN (Hz) Where • the value of RIN is determined by Equation 1 in the Gain Setting Resistor Selection section (3) When the LM48556 is using a single-ended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not amplified and heard on the output. Capacitors with a tolerance of 1% or better are recommended for impedance matching and improved CMRR and PSRR. SINGLE-ENDED AUDIO AMPLIFIER CONFIGURATION The LM48556 is compatible with single-ended sources. Figure 4 shows the typical single-ended applications circuit. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM48556 11 LM48556 SNAS452B – JUNE 2008 – REVISED MAY 2013 www.ti.com RF CIN RIN IN+ OUT- IN- OUT+ RIN CIN RF Figure 23. Single-Ended Input Configuration Bill Of Materials Component Description Designator Footprint LM48556TL LM48556TL 1 Capacitor 4.7μF, ceramic, low ESR (