LP2995MR

LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 LP2995 DDR Termination Regulator Check for Samples: LP2995 FEATURES DESCRIPTION • • • • • • • The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DDR DIMMS. 1 2 • Low Output Voltage Offset Works with +5v, +3.3v and 2.5v Rails Source and Sink Current Low External Component Count No External Resistors Required Linear Topology Available in SOIC-8, SO PowerPAD-8 or WQFN-16 Packages Low Cost and Easy to Use APPLICATIONS WHITE SPACE • • • WHITE SPACE DDR Termination Voltage SSTL-2 SSTL-3 WHITE SPACE WHITE SPACE Typical Application Circuit VREF = 1.25V + LP2995 0.1PF VDDQ = 2.5V VDDQ VREF VDD = 2.5V AVIN VSENSE PVIN VTT + 50PF GND VTT = 1.25V + 220PF 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2013, Texas Instruments Incorporated LP2995 SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 www.ti.com 4 5 VDDQ N/C GND Figure 1. SOIC-8 (D0008A) Package Top View 16 15 14 13 1 12 PVIN 11 PVIN 2 GND N/C 3 10 AVIN N/C 4 9 N/C 5 6 7 8 Figure 2. NHP- 16 Package Top View NC 1 GND 2 VSENSE 3 VREF N/C VREF VTT 6 AVIN VREF 3 VDDQ 7 PVIN VSENSE VTT 8 VTT N/C 1 2 VSENSE NC GND N/C Connection Diagram 8 VTT GND 4 7 PVIN 6 AVIN 5 VDDQ Figure 3. SO PowerPAD-8 (DDA0008A) Package Top View PIN DESCRIPTIONS 2 SOIC-8 Pin or SO PowerPAD-8 Pin WQFN Pin Name 1 1,3,4,6,9, 13,16 NC 2 2 GND 3 5 VSENSE 4 7 VREF Buffered internal reference voltage of VDDQ/2. 5 8 VDDQ Input for internal reference equal to VDDQ/2. 6 10 AVIN Analog input pin. 7 11, 12 PVIN Power input pin. 8 14, 15 VTT Output voltage for connection to termination resistors. EP EP Exposed pad thermal connection. Connect to Ground. Function No internal connection. Can be used for vias. Ground. Feedback pin for regulating VTT. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP2995 LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) AVIN to GND −0.3V to +6V PVIN to GND -0.3V to AVIN VDDQ (3) −0.3V to +6V −65°C to +150°C Storage Temp. Range Junction Temperature 150°C SO PowerPAD-8 Thermal Resistance (θJA) 43°C/W SOIC-8 Thermal Resistance (θJA) 151°C/W WQFN-16 Thermal Resistance (θJA) 51°C/W Lead Temperature (Soldering, 10 sec) ESD Rating (1) (2) (3) (4) 260°C (4) 1kV Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Operating Range Junction Temp. Range (1) 0°C to +125°C AVIN to GND 2.2V to 5.5V PVIN to GND 2.2V to AVIN (1) At elevated temperatures, devices must be derated based on thermal resistance. The device in the SOIC-8 package must be derated at θJA = 151° C/W junction to ambient with no heat sink. The device in the WQFN-16 must be derated at θJA = 51° C/W junction to ambient. Electrical Characteristics Specifications with standard typeface are for TJ = 25°C and limits in boldface type apply over the full Operating Temperature Range (TJ = 0°C to +125°C). Unless otherwise specified, AVIN = PVIN = 2.5V, VDDQ = 2.5V (1). Min Typ Max Units VREF Symbol VREF Voltage IREF_OUT = 0mA 1.21 1.235 1.26 V VOSVTT VTT Output Voltage Offset IOUT = 0A −15 −20 0 15 20 mV ΔVTT/VTT Load Regulation IOUT = 0 to 1.5A 0.5 IOUT = 0 to −1.5A −0.5 ZVREF VREF Output Impedance ZVDDQ VDDQ Input Impedance Iq Quiescent Current (1) (2) (3) (4) Parameter (3) Conditions (2) IREF = −5µA to +5µA IOUT = 0A (4) % 5 kΩ 100 kΩ 250 400 µA Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL). VTT offset is the voltage measurement defined as VTT subtracted from VREF. Load regulation is tested by using a 10ms current pulse and measuring VTT. Quiescent current defined as the current flow into AVIN. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP2995 3 LP2995 SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VIN Iq vs (25°C) Iq vs Temperature ( VIN = 2.5V) 260 800 700 255 600 250 Iq (PA) Iq (PA) 500 400 245 300 240 200 235 100 2 2.5 3 VIN 3.5 4 4.5 5 0 5.5 25 50 75 100 VIN (VOLTS) TEMPERATURE (oC) Figure 4. Figure 5. Iq vs (0, 25, 85, and 125°C) VREF vs IREF 1.26 1050 125 1.255 900 125oC 1.25 1.245 VREF (V) Iq (PA) 750 600 0oC 450 1.24 1.235 1.23 1.225 300 1.22 150 1.215 1.21 -5 0 2 2.5 3 3.5 4 4.5 5 5.5 -4 -3 -2 -1 0 1 2 3 4 5 IREF (PA) VIN (VOLTS) Figure 6. Figure 7. VREF vs Temperature (No Load) VTT vs IOUT (0, 25, 85, and 125°C) 1.2346 1.25 1.245 1.2344 125oC VTT (V) VREF (V) 1.24 1.2342 0oC 1.235 1.234 1.23 1.2338 1.225 1.2336 0 25 50 75 100 125 -50 -25 0 25 50 75 100 IOUT (mA) TEMPERATURE (oC) Figure 8. 4 1.22 -100 -75 Figure 9. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP2995 LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Maximum Output Current (Sourcing) vs VIN (VDDQ = 2.5) VTT vs IOUT 1.25 3.5 1.245 3 2.5 OUTPUT CURRENT (A) VTT (V) 1.24 1.235 1.23 2 1.5 1 1.225 1.22 -100 -75 0.5 0 -50 -25 0 25 50 75 100 2 IOUT (mA) 2.5 3 3.5 4 4.5 5 5.5 VIN (V) Figure 10. Figure 11. Maximum Output Current (Sinking) vs VIN (VDDQ = 2.5) 3.5 OUTPUT CRRENT (A) 3 2.5 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VIN (V) Figure 12. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP2995 5 LP2995 SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 www.ti.com Block Diagram VDDQ AVIN PVIN 50k + + VREF VTT - 50k - VSENSE GND 6 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP2995 LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 DETAILED DESCRIPTION The LP2995 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and SSTL-3. The LP2995 is capable of sinking and sourcing current at the output VTT, regulating the voltage to equal VDDQ / 2. A buffered reference voltage that also tracks VDDQ / 2 is generated on the VREF pin for providing a global reference to the DDR-SDRAM and Northbridge Chipset. VTT is designed to track the VREF voltage with a tight tolerance over the entire current range while preventing shoot through on the output stage. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR RAM. The most common form of termination is Class II single parallel termination. This involves using one Rs series resistor from the chipset to the memory and one Rt termination resistor. This implementation can be seen below in Figure 13. VDD VTT RT RS MEMORY CHIPSET VREF Figure 13. Typical values for RS and RT are 25 Ohms although these can be changed to scale the current requirements from the LP2995. For determination of the current requirements of DDR-SDRAM termination please refer to the accompanying application notes. Pin Descriptions AVIN AND PVIN AVIN and PVIN are the input supply pins for the LP2995. AVIN is used to supply all the internal control circuitry for the two op-amps and the output stage of VREF. PVIN is used exclusively to provide the rail voltage for the output stage on the power operational amplifier used to create VTT. For SSTL-2 applications AVIN and PVIN pins should be connected directly and tied to the 2.5V rail for optimal performance. This eliminates the need for bypassing the two supply pins separately. VDDQ VDDQ is the input that is used to create the internal reference voltage for regulating VTT and VREF. This voltage is generated by two internal 50kΩ resistors. This specifies that VTT and VREF will track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a remote sense for the reference input. This can be achieved by connecting VDDQ directly to the 2.5V rail at the DIMM. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-2 applications VDDQ will be a 2.5V signal, which will create a 1.25V reference voltage on VREF and a 1.25V termination voltage at VTT. For SSTL-3 applications it may be desirable to have a different scaling factor for creating the internal reference voltage besides 0.5. For instance a typical value that is commonly used is to have the reference voltage equal VDDQ*0.45. This can be achieved by placing a resistor in series with the VDDQ pin to effectively change the resistor divider. VSENSE The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the termination resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output of the LP2995, then the long trace will cause a significant IR drop, resulting in a termination voltage lower at one end of the bus than the other. The VSENSE pin can be used to improve this performance, by connecting it to the middle of the bus. This will provide a better distribution across the entire termination bus. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP2995 7 LP2995 SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 www.ti.com NOTE If remote load regulation is not used, then the VSENSE pin must still be connected to VTT. VREF VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the reference voltage for the Northbridge chipset and memory. Since these inputs are typically an extremely high impedance, there should be little current drawn from VREF. For improved performance, an output bypass capacitor can be used, located close to the pin, to help with noise. A ceramic capacitor in the range of 0.1 µF to 0.01 µF is recommended. VTT VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output precisely to VDDQ / 2. The LP2995 is designed to handle peak transient currents of up to ± 3A with a fast transient response. The maximum continuous current is a function of VIN and can be viewed in the Typical Performance Characteristics section. If a transient is expected to last above the maximum continuous current rating for a significant amount of time then the output capacitor should be sized large enough to prevent an excessive voltage drop. Despite the fact that the LP2995 is designed to handle large transient output currents it is not capable of handling these for long durations, under all conditions. The reason for this is the standard packages are not able to thermally dissipate the heat as a result of the internal power loss. If large currents are required for longer durations, then care should be taken to ensure that the maximum junction temperature is not exceeded. Proper thermal derating should always be used (please refer to the Thermal Dissipation section). Component Selection INPUT CAPACITOR The LP2995 does not require a capacitor for input stability, but it is recommended for improved performance during large load transients to prevent the input rail from dropping. The input capacitor should be located as close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A typical value recommended for AL electrolytic capacitors is 50 µF. Ceramic capacitors can also be used, a value in the range of 10 µF with X5R or better would be an ideal choice. The input capacitance can be reduced if the LP2995 is placed close to the bulk capacitance from the output of the 2.5V DC-DC converter. OUTPUT CAPACITOR The LP2995 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance). This allows the flexibility to use any capacitor desired. The choice for output capacitor will be determined solely on the application and the requirements for load transient response of VTT. As a general recommendation the output capacitor should be sized above 100 µF with a low ESR for SSTL applications with DDR-SDRAM. The value of ESR should be determined by the maximum current spikes expected and the extent at which the output voltage is allowed to droop. Several capacitor options are available on the market and a few of these are highlighted below: • AL - It should be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP2995. To improve the ESR several AL electrolytics can be combined in parallel for an overall reduction. An important note to be aware of is the extent at which the ESR will change over temperature. Aluminum electrolytic capacitors can have their ESR rapidly increase at cold temperatures. • Ceramic - Ceramic capacitors typically have a low capacitance, in the range of 10 to 100 µF range, but they have excellent AC performance for bypassing noise because of very low ESR (typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature. Because of the typically low value of capacitance it is recommended to use ceramic capacitors in parallel with another capacitor such as an aluminum electrolytic. A dielectric of X5R or better is recommended for all ceramic capacitors. • Hybrid - Several hybrid capacitors such as OS-CON and SP are available from several manufacturers. These offer a large capacitance while maintaining a low ESR. These are the best solution when size and 8 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP2995 LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 performance are critical, although their cost is typically higher than any other capacitor. Capacitor recommendations for different application circuits can be seen in the accompanying application notes with supporting evaluation boards. Thermal Dissipation Since the LP2995 is a linear regulator any current flow from VTT will result in internal power dissipation generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature, care should be taken to derate the part dependent on the maximum expected ambient temperature and power dissipation. The maximum allowable internal temperature rise (TRmax) can be calculated given the maximum ambient temperature (TAmax) of the application and the maximum allowable junction temperature (TJmax). TRmax = TJmax − TAmax From this equation, the maximum power dissipation (PDmax) of the part can be calculated: PDmax = TRmax / θJA The θJA of the LP2995 will be dependent on several variables: the package used; the thickness of copper; the number of vias and the airflow. For instance, the θJA of the SOIC-8 is 163°C/W with the package mounted to a standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5W dissipation at room temperature. This value can be reduced to 151.2°C/W by changing to a 3x4 board with 2 oz. copper that is the JEDEC standard. Figure 14 shows how the θJA varies with airflow for the two boards mentioned. 180 170 160 150 SOP Board TJA 140 130 120 110 JEDEC Board 100 90 80 0 200 400 600 800 1000 AIRFLOW (Linear Feet per Minute) Figure 14. θJA vs Airflow (SOIC-8) Layout is also extremely critical to maximize the output current with the WQFN package. By simply placing vias under the DAP the θJA can be lowered significantly. Figure 15 shows the WQFN thermal data when placed on a 4-layer JEDEC board with copper thickness of 0.5/1/1/0.5 oz. The number of vias, with a pitch of 1.27 mm, has been increased to the maximum of 4 where a θJA of 50.41°C/W can be obtained. Via wall thickness for this calculation is 0.036 mm for 1oz. Copper. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP2995 9 LP2995 SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 www.ti.com 100 90 TJA (qC/W) 80 70 60 50 40 0 1 2 3 4 NUMBER OF VIAS Figure 15. WQFN-16 θJA vs # of Vias (4 Layer JEDEC Board)) Additional improvements in lowering the θJA can also be achieved with a constant airflow across the package. Maintaining the same conditions as above and utilizing the 2x2 via array, Figure 16 shows how the θJA varies with airflow. 51 50 qJA (oC/W) 49 48 47 46 45 0 100 200 300 400 500 600 AIRFLOW (Linear Feet Per Minute) Figure 16. θJA vs Airflow Speed (JEDEC Board with 4 Vias) Typical Application Circuits The typical application circuit used for SSTL-2 termination schemes with DDR-SDRAM can be seen in Figure 17. LP2995 VDDQ VDDQ VREF VREF VDD AVIN VTT VTT PVIN VSENSE + COUT + CIN GND Figure 17. SSTL-2 Implementation 10 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP2995 LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 For SSTL-3 and other applications it may be desirable to change internal reference voltage scaling from VDDQ * 0.5. An external resistor in series with the VDDQ pin can be used to lower the reference voltage. Internally two 50 kΩ resistors set the output VTT to be equal to VDDQ * 0.5. The addition of a 11.1 kΩ external resistor will change the internal reference voltage causing the two outputs to track VDDQ * 0.45. An implementation of this circuit can be seen in Figure 18. LP2995 RVddq VDDQ VDDQ VREF VREF VDD AVIN VTT VTT PVIN VSENSE + COUT + CIN GND Figure 18. SSTL-3 Implementation Another application that is sometimes required is to increase the VTT output voltage from the scaling factor of VDDQ * 0.5. This can be accomplished independently of VREF by using a resistor divider network between VTT, VSENSE and Ground. An example of this circuit can be seen in Figure 19. LP2995 VDDQ VDDQ VREF VDD AVIN VTT PVIN VSENSE VREF VTT R1 COUT + CIN GND + R2 Figure 19. PCB Layout Considerations 1. AVIN and PVIN should be tied together for optimal performance. A local bypass capacitor should be placed as close as possible to the PVIN pin. 2. GND should be connected to a ground plane with multiple vias for improved thermal performance. 3. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For motherboard applications an ideal location would be at the center of the termination bus. 4. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the most accurate point for creating the reference voltage. 5. VREF should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This capacitor should be located as close as possible to the VREF pin. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP2995 11 LP2995 SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision L (March 2013) to Revision M • 12 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 11 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP2995 PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LP2995LQ/NOPB ACTIVE WQFN NHP 16 1000 RoHS & Green SN Level-3-260C-168 HR 0 to 125 L00005B LP2995M NRND SOIC D 8 95 Non-RoHS & Green Call TI Level-1-235C-UNLIM 0 to 125 2995M LP2995M/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM 0 to 125 2995M LP2995MR NRND SO PowerPAD DDA 8 95 Non-RoHS & Green Call TI Level-3-260C-168 HR 0 to 125 LP2995 LP2995MR/NOPB ACTIVE SO PowerPAD DDA 8 95 RoHS & Green SN Level-3-260C-168 HR 0 to 125 LP2995 LP2995MRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-3-260C-168 HR 0 to 125 LP2995 D 8 2500 RoHS & Green SN Level-1-260C-UNLIM 0 to 125 2995M LP2995MX/NOPB ACTIVE SOIC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of