OPA1637
OPA1637
SBOSA00B – DECEMBER 2019 – REVISED AUGUST
2020
SBOSA00B – DECEMBER 2019 – REVISED AUGUST 2020
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OPA1637 High-Fidelity, Low-Noise, Fully-Differential, Burr-Brown™ Audio
Operational Amplifier
1 Features
3 Description
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The OPA1637 is a low-noise, low total harmonic
distortion (THD), fully differential, Burr-Brown™ Audio
operational amplifier that easily filters and drives fully
differential, audio signal chains.
Low input voltage noise: 3.7 nV/√Hz at 1 kHz
Low THD + N: –120 dB at 1 kHz
Low supply current: 950 µA at ±18 V
Input offset voltage: ±200 µV (maximum)
Input bias current: 2 nA (maximum)
Low bias current noise: 400 fA/√Hz at 10 Hz
Gain-bandwidth product: 9.2 MHz
Differential output slew rate: 15 V/µs
Wide input and output common-mode range
Wide single-supply operating range: 3 V to 36 V
Low supply current power-down feature: < 20 µA
Overload power limit
Current limit
Package: 8-pin VSSOP
Temperature range: –40°C to +125°C
2 Applications
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Professional audio mixer or control surface
Professional microphones and wireless systems
Professional speaker systems
Professional audio amplifier
Soundbar
Turntable
Professional video camera
Guitar and other instrument amplifier
Data aquisition (DAQ)
The OPA1637 also converts single-ended sources to
differential outputs required by high-fidelity analog-todigital converters (ADCs). Designed for exceptional
low noise and THD, the bipolar super-beta inputs yield
a very low noise figure at very-low quiescent current
and input bias current. This device is designed for
audio circuits where low power consumption is
required along with excellent signal-to-noise ratio
(SNR) and spurious-free dynamic range (SFDR).
The OPA1637 features high-voltage supply capability,
allowing for supply voltages up to ±18 V. This
capability allows high-voltage differential signal chains
to benefit from the improved headroom and dynamic
range without adding separate amplifiers for each
polarity of the differential signal. Very-low voltage and
current noise enables the OPA1637 for use in highgain configurations with minimal impact to the audio
signal noise.
The OPA1637 is characterized for operation over the
wide temperature range of –40°C to +125°C, and is
available in an 8-pin VSSOP package.
Device Information (1)
PART NUMBER
PACKAGE
OPA1637
(1)
VSSOP (8)
For all available packages, see the package option
addendum at the end of the datasheet.
RISO1
75
RI1
49
5V
C2
1 µF
INPUT_A
5V
±
PCM1795
Audio DAC
IOUTL/R+
IOUTL/R±
C5
1 µF
GND
± 3.5 V
±10 V
RF2
1k
RI2
49
+
OPA1637
±
+
PD
CDF
10 nF
C3
1 µF
±10 V 5 V
CF2
3.3 nF
TPA3251
Class D
ADC
Amplifier
INPUT_B
RISO2
75
Voltage Noise Density (nV/—Hz)
RF1
1k
CF1
3.3 nF
BODY SIZE (NOM)
3.00 mm × 3.00 mm
100
70
50
30
20
10
7
5
3
2
GND
Low-Noise, Low-Power, Fully-Differential Amplifier
Gain Block and Interface
1
100m
1
10
100
1k
Frequency (Hz)
10k
100k
D022
Low Input Voltage Noise
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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© 2020 Texas
Instruments
Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 8
7 Parameter Measurement Information.......................... 15
7.1 Characterization Configuration................................. 15
8 Detailed Description......................................................16
8.1 Overview................................................................... 16
8.2 Functional Block Diagram......................................... 16
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................17
9 Application and Implementation.................................. 18
9.1 Application Information............................................. 18
9.2 Typical Applications.................................................. 22
10 Power Supply Recommendations..............................27
11 Layout........................................................................... 27
11.1 Layout Guidelines................................................... 27
11.2 Layout Example...................................................... 27
12 Device and Documentation Support..........................28
12.1 Device Support....................................................... 28
12.2 Documentation Support.......................................... 28
12.3 Receiving Notification of Documentation Updates..28
12.4 Support Resources................................................. 28
12.5 Trademarks............................................................. 28
12.6 Electrostatic Discharge Caution..............................28
12.7 Glossary..................................................................28
13 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2020) to Revision B (August 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed front page application diagram to show correct label and value for RF1 ............................................ 1
• Changed Figure 7-1 to show correct labels...................................................................................................... 15
• Changed Figure 9-5 to show correct label and value for RF1 .......................................................................... 22
• Changed Figure 9-8 negative rail from 0 V to –5 V.......................................................................................... 24
Changes from Revision * (December 2019) to Revision A (May 2020)
Page
• Changed device status from advanced information (preview) to production data (active) ................................ 1
2
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5 Pin Configuration and Functions
IN-
1
8
IN+
VOCM
2
7
PD
VS+
3
6
VS-
OUT+
4
5
OUT-
Figure 5-1. DGK Package, 8-Pin VSSOP, Top View
Pin Functions
PIN
NAME
NO.
IN–
1
IN+
OUT–
OUT+
I/O
DESCRIPTION
I
Inverting (negative) amplifier input
8
I
Noninverting (positive) amplifier input
5
O
Inverting (negative) amplifier output
4
O
Noninverting (positive) amplifier output
PD
7
I
Power down.
PD = logic low = power off mode.
PD = logic high = normal operation.
The logic threshold is referenced to VS+.
If power down is not needed, leave PD floating.
VOCM
2
I
Ouput common-mode voltage control input
VS–
6
I
Negative power-supply input
VS+
3
I
Positive power-supply input
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VS
MAX
Single supply
Supply voltage
UNIT
40
Dual supply
IN+, IN–, Differential voltage(2)
IN+, IN–, VOCM, PD, OUT+, OUT− voltage(3)
V
±20
V
±0.5
V
VVS– – 0.5
VVS+ + 0.5
IN+, IN− current
–10
10
mA
OUT+, OUT− current
–50
50
mA
Output short-circuit(4)
V
Continuous
TA
Operating Temperature
–40
150
°C
TJ
Junction Temperature
–40
175
°C
Tstg
Storage Temperature
–65
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Input pins IN+ and IN– are connected with anti-parallel diodes in between the two terminals. Differential input signals that are greater
than 0.5 V or less than –0.5 V must be current-limited to 10 mA or less.
Input terminals are diode-clamped to the supply rails (VS+, VS–). Input signals that swing more than 0.5 V greater or less the supply
rails must be current-limited to 10 mA or less.
Short-circuit to VS / 2.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Single-supply
VS
Supply voltage
TA
Specified temperature
Dual-supply
NOM
MAX
3
36
±1.5
±18
–40
125
UNIT
V
°C
6.4 Thermal Information
OPA1637
THERMAL METRIC(1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
68.3
°C/W
RθJB
Junction-to-board thermal resistance
102.8
°C/W
ψJT
Junction-to-top characterization parameter
10.6
°C/W
ψJB
Junction-to-board characterization parameter
101.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
181.1
For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
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6.5 Electrical Characteristics
at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = 0 V, input common mode voltage (VICM) = 0 V, RF = 2
kΩ, V PD = VVS+, RL = 10 kΩ(1) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
SSBW
Small-signal bandwidth
VO (2) = 100 mVPP, G = –1 V/V
7
MHz
GBP
Gain-bandwidth product
VO = 100 mVPP, G = –10 V/V
9.2
MHz
FBP
Full-power bandwidth
VO = –1 VPP, G = –1 V/V
2.5
MHz
SR
Slew rate
G = –1, 10-V step
15
V/µs
Settling time
0.1% of final value, G = –1 V/V, VO = 10-V step
1
0.01% of final value, G = –1 V/V, VO= 10-V step
2
Differential input, f = 1 kHz, VO = 10 VPP
THD+N
Total harmonic distortion and
noise
Single-ended input, f = 1 kHz, VO = 10 VPP
Differential input, f = 10 kHz, VO = 10 VPP
Single-ended input, f = 10 kHz, VO = 10 VPP
HD2
Second-order harmonic distortion
HD3
Third-order harmonic distortion
Overdrive recovery time
µs
–120
dB
0.0001
%
–115
dB
0.00018
%
–112
dB
0.00025
%
–107
dB
0.00045
%
Differential input, f = 1 kHz, VO = 10 VPP
–126
Single-ended input, f = 1 kHz, VO = 10 VPP
–120
Differential input, f = 1 kHz, VO = 10 VPP
–131
Single-ended input, f = 1 kHz, VO = 10 VPP
–119
G = 5 V/V, 2x output overdrive, dc-coupled
3.3
f = 1 kHz
3.7
f = 10 Hz
4
dB
dB
µs
NOISE
en
ei
Input differential voltage noise
Input current noise, each input
f = 0.1 Hz to 10 Hz
0.1
f = 1 kHz
300
f = 10 Hz
400
f = 0.1 Hz to 10 Hz
13.4
nV/√ Hz
µVPP
fA/√ Hz
pAPP
OFFSET VOLTAGE
VIO
Input-referred offset voltage
Input offset voltage drift
PSRR
Power-supply rejection ratio
20
TA = –40°C to +125°C
TA = –40°C to +125°C
±200
±250
0.1
±1
0.025
±0.5
TA = –40°C to +125°C
±1
µV
µV/°C
µV/V
INPUT BIAS CURRENT
IB
Input bias current
Input bias current drift
IOS
0.2
TA = –40°C to +125°C
TA = –40°C to +125°C
Input offset current
±4
2
±15
0.2
±1
TA = –40°C to +125°C
Input offset current drift
TA = –40°C to +125°C
±2
±3
1
±10
nA
pA/°C
nA
pA/°C
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6.5 Electrical Characteristics (continued)
at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = 0 V, input common mode voltage (VICM) = 0 V, RF = 2
kΩ, V PD = VVS+, RL = 10 kΩ(1) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE
Common-mode voltage
TA = –40°C to +125°C
VVS– + 1
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V
CMRR
Common-mode rejection ratio
VVS+ – 1
V
140
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V, VS = ±18 V
126
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V, VS = ±18 V
TA = –40°C to +125°C
120
140
dB
INPUT IMPEDANCE
Input impedance differential
mode
VICM = 0 V
1 || 1
GΩ || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = ±2.5 V, VVS– + 0.2 V < VO < VVS+ – 0.2 V
115
120
VS = ±2.5 V, VVS– + 0.3 V < VO < VVS+ – 0.3 V,
TA = –40°C to +125°C
110
120
VS = ±15 V, VVS– + 0.6 V < VO < VVS+ – 0.6 V
115
120
VS = ±15 V, VVS– + 0.6 V < VO < VVS+ – 0.6 V,
TA = –40°C to +125°C
110
120
dB
OUTPUT
Output voltage difference from
supply voltage
ISC
VS = ±2.5 V
±100
VS = ±2.5 V, TA = –40°C to +125°C
±100
VS = ±18 V
±230
VS = ±18 V, TA = –40°C to +125°C
±270
Short-circuit current
CLOAD
Capacitive load drive
Differential capacitive load, no output Isolation
resistors, phase margin = 30°
ZO
Open-loop output impedance
f = 100 kHz (differential)
mV
±31
mA
50
pF
14
Ω
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL
Input Voltage Range
VS = ±2.5 V
VVS– + 1
VVS+ – 1
VS = ±18 V
VVS– + 2
VVS+ – 2
Small-signal bandwidth from
VOCM pin
VVOCM= 100 mVPP
Large-signal bandwidth from
VOCM pin
VVOCM = 0.6 VPP
5.7
VVOCM = 0.5-V step, rising
3.5
VVOCM = 0.5-V step, falling
5.5
VVOCM fixed midsupply (VO = ±1 V)
78
Slew rate from VOCM pin
DC output balance
2
MHz
VOCM input impedance
V/µs
dB
2.5 || 1
VOCM offset from mid-supply
VOCM pin floating
VOCM common-mode offset
voltage
VVOCM = VICM, VO = 0 V
VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C
VOCM common-mode offset
voltage drift
VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C
MΩ || pF
2
±1
mV
±6
±10
±20
±60
0.95
1.2
mV
µV/°C
POWER SUPPLY
IQ
6
Quiescent operating current
TA = –40°C to +125°C
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1.6
mA
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6.5 Electrical Characteristics (continued)
at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = 0 V, input common mode voltage (VICM) = 0 V, RF = 2
kΩ, V PD = VVS+, RL = 10 kΩ(1) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER DOWN
V PD(HI)
Power-down enable voltage
TA = –40°C to +125°C
V PD(LOW)
Power-down disable voltage
TA = –40°C to +125°C
PD bias current
V PD = VVS+ – 2 V
Powerdown quiescent current
(1)
(2)
VVS+ –
0.5
V
VVS+ –
2.0
V
1
2
µA
10
20
µA
Turn-on time delay
VIN = 100 mV, time to VO = 90% of final value
10
µs
Turn-off time delay
VIN = 100 mV, time to VO = 10% of original value
15
µs
RL is connected differentially, from OUT+ to OUT–.
VO refers to the differential output voltage, VOUT+ – VOUT–.
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6.6 Typical Characteristics
5000
100
70
50
Input-Referred Current Noise (fA/—Hz)
30
20
10
7
5
3
2
1
100m
1
10
100
1k
Frequency (Hz)
10k
3000
2000
1000
700
500
300
200
100
0.1
100k
D013
Total Harmonic Distortion
-100
-105
-110
-115
-120
-125
10
100
1k
Frequency (Hz)
D014
-60
0.01
-80
0.001
-100
0.0001
-120
1E-5
10m
10k 20k
160
200
Gain
Phase 160
140
120
120
80
40
80
0
60
-40
40
-80
20
-120
0
-160
-20
-200
100k
1M
10M
50
40
30
Phase (q)
100
1k
10k
Frequency (Hz)
D016
Figure 6-4. Total Harmonic Noise + Distortion vs
Amplitude
Gain (dB)
180
100
10
f = 1 kHz, VS = ±15 V
Figure 6-3. Total Harmonic Distortion + Noise vs
Frequency
10
-140
100m
1
Output Amplitude (VRMS)
D015
VOUT = 3 VRMS, VS = ±15 V
1
100000
RL = 2 k:
RL = 10 k:
Noise (%)
Noise (dB)
RL = 2 k:
RL = 10 k:
RL = 600 :
-95
Total Harmonic Distortion
10000
0.1
-90
Gain (dB)
2 3 5 10 20
100
1000
Frequency (Hz)
Figure 6-2. Current Noise vs Frequency
Figure 6-1. Input-Referred Voltage Noise vs
Frequency
20
10
0
-10
-20
1k
D068
VS = ±15 V, CL = 50 pF
G=1
G = 10
G = 100
10k
100k
Frequency (Hz)
1M
10M
D009
VS = ±15 V, CL = 50 pF
Figure 6-5. Open Loop Gain vs Frequency
8
0.5
Total Harmonic Distortion + Noise (dB)
Input-Referred Voltage Noise (nV/—Hz)
at VS = ±18 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, VOUT = 2 VPP, G = 1 V/V, and V PD = VS
+ (unless otherwise noted)
Figure 6-6. Closed-Loop Gain vs Frequency
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0.09
Common-Mode Rejection Ratio (PV/V)
Common-Mode Rejection Ratio (dB)
180
160
140
120
100
80
60
40
20
0
10m 100m
1
10
100
1k
10k
Frequency (Hz)
100k
1M
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
-40
10M
-25
-10
5
20 35 50 65
Temperature (oC)
D011
80
95
110 125
D030
VS = ±15 V
Figure 6-8. Common Mode Rejection Ratio vs
Temperature
Figure 6-7. Common Mode Rejection Ratio vs
Frequency
180
-0.01
Power Supply Rejection Ratio (dB)
160
Power Supply Rejection Ratio (PV/V)
PSRR
PSRR
140
120
100
80
60
40
20
0
10m 100m
1
10
100
1k
10k
Frequency (Hz)
100k
1M
-0.02
-0.03
-0.04
-0.05
-40
10M
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
D031
D012
VS = ±15 V
Figure 6-10. Power Supply Rejection Ratio vs
Temperature
40
10000
35
5000
3000
2000
Open-Loop Output Impedance :
Maximum Output Voltage (VPP)
Figure 6-9. Power Supply Rejection Ratio vs
Frequency
30
25
20
15
10
5
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
1000
500
300
200
100
50
30
20
10
1
D019
VS = ±15 V
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
D017
VS = ±15 V
Figure 6-11. Maximum Output Voltage vs
Frequency
Figure 6-12. Output Impedance vs Frequency
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15
15
10
10
Amplifiers (%)
Amplifiers (%)
SBOSA00B – DECEMBER 2019 – REVISED AUGUST 2020
5
0
-200
-150
-100
-50
0
50
100
Input Offset Voltage (PV)
150
5
0
-200
200
-150
-100
D001
VS = ±1.5 V
-50
0
50
100
Input Offset Voltage (PV)
150
200
D061
VS = ±18 V
Figure 6-13. Input Offset Voltage Histogram
Figure 6-14. Input Offset Voltage Histogram
25
20
20
Amplifiers (%)
Amplifiers (%)
15
15
10
10
5
5
0
-1
-0.8
-0.6
-0.4 -0.2
0
0.2 0.4
Offset Voltage Drift (PV/qC)
0.6
0.8
0
-6
1
-4
-2
0
2
4
Common-Mode Input Offset Voltage (mV)
D002
VS = ±15 V
6
D006
VS = ±18 V, VOCM = floating
Figure 6-15. Input Offset Voltage Drift Histogram
Figure 6-16. Output Common Mode Voltage Offset
2
15
Quiescent Current (mA)
Amplifiers (%)
1.8
10
5
1.6
1.4
1.2
1
0.8
0.6
-40oC
25oC
85oC
125oC
0.4
0.2
0
-6
0
-5
-4 -3 -2 -1
0
1
2
3
4
Common-Mode Input Offset Voltage (mV)
5
6
3
6
D007
9
12
15 18 21 24
Supply Voltage (V)
27
30
33
36
D045
VS = ±18 V, VOCM = 0 V
Figure 6-17. Output Common Mode Voltage Offset
10
Figure 6-18. Quiescent Current vs Supply Voltage
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1.6
1.5
1.3
1.2
1.1
1
0.9
0.8
0.7
0.5
-50
1
0.8
0.6
0.4
0
-25
0
25
50
75
Temperature (oC)
100
125
150
0
0.5
1
D065
Figure 6-19. Quiescent Current vs Temperature
1.5
2
2.5
3
3.5
4
VS+ Delta from Power Down (V)
4.5
5
D053
Figure 6-20. Quiescent Current vs Power-Down
Delta from Supply Voltage
500
250
55oC
40oC
25oC
85oC
125oC
150oC
200
150
100
50
400
300
Input Bias Current (pA)
Input-Referred Offset Voltage (PV)
1.2
0.2
VS = r18 V
VS = r1.5 V
0.6
0
-50
-100
17 V
17 V
-150
200
100
0
-100
-200
IB
IB+
IOS
-300
-400
-200
-250
-18
-14
-10
-6
-2
2
6
10
Input Common-Mode Voltage (V)
14
-500
-18
18
-14
D023
-10
-6
-2
2
6
10
Input Common-Mode Voltage (V)
14
18
D025
Figure 6-22. Input Bias Current vs Input CommonMode Voltage
Figure 6-21. Input Offset Voltage vs Input
Common-Mode Voltage
500
30
IB
IB+
IOS
450
400
28
350
Output Voltage (V)
Input Bias Current (pA)
Vs = r1.5 V
Vs = r18 V
1.4
Quiescent Current (mA)
Quiescent Current (mA)
1.4
300
250
200
150
100
26
24
40qC
125qC
25qC
85qC
50
22
0
-50
-100
20
3
6
9
12
15 18 21 24
Supply Voltage (V)
27
30
33
36
0
D027
Figure 6-23. Input Bias Current vs Supply Voltage
5
10
15
20
25
Output Current (mA)
30
35
40
D028
Figure 6-24. Output Voltage vs Output Current
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-20
128
40qC
125qC
25qC
85qC
126
124
Open-Loop Gain (dB)
Output Voltage (V)
-22
-24
-26
122
120
118
116
114
-28
112
-30
-40
108
0.3
25 qC
85 qC
125 qC
40 qC
110
-35
-30
-25
-20
-15
Output Current (mA)
-10
-5
0
D029
Figure 6-25. Output Voltage vs Output Current
Figure 6-26. Open-Loop Gain vs Ouput Delta From
Supply
20
20
RISO = 0 :
RISO = 25 :
RISO = 50 :
17.5
RISO = 0 :
RISO = 25 :
RISO = 50 :
15
15
Overshoot (%)
Overshoot (%)
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
Output Voltage Delta from Supply Voltage, VS+/VS (V) D049
12.5
10
7.5
5
10
5
2.5
0
20
40
60
80
100
120
Capacitive Load (pF)
140
160
0
180
0
50
100
150
200
250
Capacitive Load (pF)
D036
AV = 1
300
350
400
D037
AV = 10
Figure 6-27. Small-Signal Overshoot vs Capacitive
Load
Figure 6-28. Small-Signal Overshoot vs Capacitive
Load
50
20
40
Short-Circuit Current (mA)
Slew Rate (V/Ps)
17
14
11
8
Falling Edge
Rising Edge
6
9
12
15 18 21 24
Supply Voltage (V)
27
30
33
36
IOUT
IOUT
IOUT
IOUT
10
0
-10
(sinking)
(sourcing)
(sourcing)
(sinking)
-20
-30
-50
-25
-10
D041
Figure 6-29. Output Slew Rate vs Supply Voltage
12
20
-40
5
3
30
5
20
35
50
65
80
Temperature (oC)
95
110
125
D048
Figure 6-30. Short-Circuit Current vs Temperature
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3
1.1
2.5
1.08
2
1.06
1.5
1.04
0.5
Voltage (V)
Voltage (V)
1
VOUT
VOUT
0
-0.5
1.02
1
0.98
-1
0.96
-1.5
-2
0.94
-2.5
0.92
-3
0.9
Time (1 Ps/div)
VVOCM
(VOUT
VOUT )/2
Time (5 Ps /div)
D044
D054
Figure 6-31. Large-Signal Step Response
Figure 6-32. Output Common-Mode Step
Response, Rising
0.1
VVOCM
(VOUT
0.08
VIN
VOUT
VOUT
VOUT )/2
Voltage (50 mV/div)
0.06
Voltage (V)
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
Time (5 Ps / div)
Time (500 ns/div)
D055
Figure 6-33. Output Common-Mode Step
Response, Falling
D043
Voltage (50 mV/div)
VOUT Delta to Final Value (250 PV/div)
Figure 6-34. Small-Signal Step Response, Falling
VIN
VOUT
VOUT
Time (500 ns/div)
+0.01
Settling
Threshold
0.01%
Settling
Threshold
Input
Transition
Time (250 ns/div)
D042
Figure 6-35. Small-Signal Step Response, Rising
D046
Figure 6-36. Output Settling Time to ±0.01%
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18
15
0.25
15
0.3
VPD
VOUT 0.2
12
0.2
12
0.1
9
0.15
6
0.1
3
0.05
0
0
VPD -0.05
VOUT
-3
-6
Power-down Voltage, VPD (V)
0.3
Output Voltage, VOUT (V)
Power-down Voltage, VPD (V)
18
-0.1
9
0
6
-0.1
3
-0.2
0
-0.3
-3
-0.4
-6
Time (1 Ps/div)
-0.5
Time (1 Ps/div)
D050
D051
Figure 6-37. Power-Down Time (PD Low to High)
Figure 6-38. Power-Down Time (PD High to Low)
Voltage (5 V/div)
VIN
VOUT
VOUT
Voltage (5 V/div)
VIN
VOUT
VOUT
Time (20 Ps/div)
Time (20 Ps/div)
D039
Figure 6-39. Output Negative Overload Recovery
14
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D040
Figure 6-40. Output Positive Overload Recovery
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7 Parameter Measurement Information
7.1 Characterization Configuration
The OPA1637 provides the advantages of a fully differential amplifier (FDA) configuration that offers very low
noise and harmonic distortion in a single, low-power amplifier. The FDA is a flexible device, where the main aim
is to provide a purely differential output signal centered on a user-configurable, common-mode voltage that is
usually matched to the input common-mode voltage required by an analog-to-digital converter (ADC) or class-D
amplifier. The circuit used for characterization of the differential-to-differential performance is seen in Figure 7-1.
VIN±
RI
2k
±
+
±
+
±
+
VOUT+
RISO
0
VVS+
VIDIFF/2
+
±
VVOCM
VCM
RF
2k
+
OPA1637
±
+
VIDIFF/2
RI
2k
RL
10 k
RISO
0
CL
VOUT
DNP
±
VVS± VPD
RF
2k
VIN+
VOUT±
All voltages except VIN and VOUT are
referenced to ground.
Figure 7-1. Differential Source to a Differential Gain of a 1-V/V Test Circuit
A similar circuit is used for single-ended to differential measurements, as shown in Figure 7-2.
RI
2k
VIN±
VOUT+
VVS+
RISO
0
+
±
VVOCM
+
OPA1637
±
+
RI
2k
RISO
0
RL
10 k
CL
VOUT
DNP
±
VVS± VPD
±
+
VIN
RF
2k
VIN+
RF
2k
VOUT±
All voltages except VOUT are
referenced to ground.
Figure 7-2. Single-Ended to Differential Gain of a 1-V/V Test Circuit
The FDA requires feedback resistor for both output pins to the input pins. These feedback resistors load the
output differentially only if the input common-mode voltage is equal to the output common-mode voltage set by
VOCM. When VOCM differs from the input common-mode range, the feedback resistors create single-ended
loading. The characterization plots fix the RF (RF1 = RF2) value at 2 kΩ, unless otherwise noted. This value can
be adjusted to match the system design parameters with the following considerations in mind:
•
•
The current needed to drive RF from the peak output voltage to the input common-mode voltage adds to the
overall output load current. If the total load current (current through RF + current through RL) exceeds the
current limit conditions, the device enters a current limit state, causing the output voltage to collapse.
High feedback resistor values (RF> 100 kΩ) interact with the amplifier input capacitance to create a zero in
the feedback network. Compensation must be added to account for this potential source of instability; see the
TI Precision Labs FDA Stability Training for guidance on designing an appropriate compensation network.
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8 Detailed Description
8.1 Overview
The OPA1637 is a low-noise, low-distortion fully-differential amplifier (FDA) that features Texas Instrument's
super-beta bipolar input devices. Super-beta input devices feature very low input bias current as compared to
standard bipolar technology. The low input bias current and current noise makes the OPA1637 an excellent
choice for audio applications that require low-noise differential signal processing without significant current
consumption. This device is also designed for analog-to-digital audio input circuits that require low noise in a
single fully-differential amplifier. This device achieves lower current consumption at lower noise levels than what
is achievable with two low-noise amplifiers. The OPA1637 also features high-voltage capability, which allows the
device to be used in ±15-V supply circuits without any additional voltage clamping or regulators. This feature
enables a direct, single amplifier for a 24-dBm differential output drive (commonly found on mixers and digital
audio interfaces) without any additional amplification.
8.2 Functional Block Diagram
VS+
OUT+
IN±
±
Low Noise +
Differential I/O
Amplifier
±
IN+
+
OUT±
VS±
VS+
5M
1 µA
±
VCM
Error
Amplifier
+
VOCM
PD
5M
VS±
16
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8.3 Feature Description
8.3.1 Super-Beta Input Bipolar Transistors
The OPA1637 is designed on a modern bipolar process that features TI's super-beta input transistors. Traditional
bipolar transistors feature excellent voltage noise and offset drift, but suffer a tradeoff in high input bias current
(IB) and high input bias current noise. Super-beta transistors offer the benefits of low voltage noise and low offset
drift with an order of magnitude reduction in input bias current and reduction in input bias current noise. For
audio circuits, input bias current noise can dominate in circuits where higher resistance input resistors are used.
The OPA1637 enables a fully-differential, low-noise amplifier design without restrictions of low input resistance at
a power level unmatched by traditional single-ended amplifiers.
8.3.2 Power Down
The OPA1637 features a power-down circuit to disable the amplifier when a low-power mode is required by the
system. In the power-down state, the amplifier outputs are in a high-impedance state, and the amplifier total
quiescent current is reduced to less than 20 µA.
8.3.3 Flexible Gain Setting
The OPA1637 offers considerable flexibility in the configuration and selection of resistor values. Low input bias
current and bias current noise allows for larger gain resistor values with minimal impact to noise or offset. The
design starts with the selection of the feedback resistor value. The 2-kΩ feedback resistor value used for the
characterization curves is a good compromise among power, noise, and phase margin considerations. With the
feedback resistor values selected (and set equal on each side), the input resistors are set to obtain the desired
gain, with the input impedance also set with these input resistors. Differential I/O designs provide an input
impedance that is the sum of the two input resistors. Single-ended input to differential output designs present a
more complicated input impedance. Most characteristic curves implement the single-ended to differential design
as the more challenging requirement over differential-to-differential I/O.
8.3.4 Amplifier Overload Power Limit
In many bipolar-based amplifiers, the output stage of the amplifier can draw significant (several milliamperes) of
quiescent current if the output voltage becomes clipped (meaning the output voltage becomes limited by the
negative or positive supply voltage). This condition can cause the system to enter a high-power consumption
state, and potentially cause oscillations between the power supply and signal chain. The OPA1637 has an
advanced output stage design that eliminates this problem. When the output voltage reaches the VVS+ or VVS–
voltage, there is virtually no additional current consumption from the nominal quiescent current. This feature
helps eliminate any potential system problems when the signal chain is disrupted by a large external transient
voltage.
8.4 Device Functional Modes
The OPA1637 has two functional modes: normal operation and power-down. The power-down state is enabled
when the voltage on the power-down pin is lowered to less than the power-down threshold. In the power-down
state, the quiescent current is significantly reduced, and the output voltage is high-impedance. This high
impedance can lead to the input voltages (+IN and –IN) separating, and forward-biasing the ESD protection
diodes. See Section 9 for guidance on power-down operation.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
Most applications for the OPA1637 strive to deliver the best dynamic range in a design that delivers the desired
signal processing along with adequate phase margin for the amplifier. The following sections detail some of the
design issues with analysis and guidelines for improved performance.
9.1.1 Driving Capacitive Loads
The capacitive load of an ADC, or some other next-stage device, is commonly required to be driven. Directly
connecting a capacitive load to the output pins of a closed-loop amplifier such as the OPA1637 can lead to an
unstable response. One typical remedy to this instability is to add two small series resistors (RISO) at the outputs
of the OPA1637 before the capacitive load. Good practice is to leave a place for the RISO elements in a board
layout (a 0-Ω value initially) for later adjustment, in case the response appears unacceptable.
For applications where the OPA1637 is used as an output device to drive an unknown capacitive load, such as a
cable, RISO is required. Figure 9-1 shows the required RISO value for a 40-degree phase-margin response. The
peak required RISO value occurs when CL is between 500 pF and 1 nF. As CL increases beyond 1 nF, the
bandwidth response of the device reduces, resulting in a slower response but no major degradation in phase
margin. For a typical cable type, such as Belden 8451, capacitive loading can vary from 340 pF (10-foot cable) to
1.7 nF (50-foot cable). Selecting RISO to be 100 Ω provides sufficient phase margin regardless of the cable
length. RISO can also be used within the loop feedback of the amplifier; however, simulation must be used to
verify the stability of the system.
100
Isolation Resistance, RISO (:)
90
80
70
60
50
40
30
20
10
0
100 p
1n
10 n
Load Capacitance, CL (F)
100 n
D069
Figure 9-1. Required Isolation Resistance vs Capacitive Load for a 40° Phase Margin
18
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9.1.2 Operating the Power-Down Feature
The power-down feature on the OPA1637 allows the device to be put into a low power-consumption state, in
which quiescent current is minimized. To force the device into the low-power state, drive the PD pin lower than
the power-down threshold voltage (VVS+ – 2 V). Driving the PD pin lower than the power-down threshold voltage
forces the internal logic to disable both the differential and common-mode amplifiers. The PD pin has an internal
pullup current that allows the pin to be used in an open-drain MOSFET configuration without an additional pullup
resistor, as seen in Figure 9-2. In this configuration, the logic level can be referenced to the MOSFET, and the
voltage at the PD pin is level-shifted to account for use with high supply voltages. Be sure to select an N-type
MOSFET with a maximum BVDSS greater than the total supply voltage. For applications that do not use the
power-down feature, tie the PD pin to the positive supply voltage.
VS+
1 µA
PD
Enabled
MOSFET
THRESHOLD
To
amplifier
core
Powerdown
OPA1637
GND
Figure 9-2. Power-Down ( PD) Pin Interface With Low-Voltage Logic Level Signals
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When PD is low (device is in power down) the output pins will be in a high-impedance state. When the device is
in the power-down state, the outputs are high impedance, and the output voltage is no longer controlled by the
amplifier, but dependant on the input and load configuration. In this case, the input voltage between IN– and IN+
can drift to a voltage that may forward-bias the input protection diodes. Take care to avoid high currents flowing
through the input diodes by using an input resistor to limit the current to less than 10 mA. In Figure 9-3, the
OPA1637 is configured in a differential gain of 5 with 100-Ω input resistors. When the device enters power down,
the voltage between IN– and IN+ increases until the internal protection diode is forward-biased. In this case,
exceeding a voltage on VIN with RIN= 0 Ω of 2.5 V (diode forward voltage estimated at 0.5 V) results in a current
greater than 10 mA. To avoid this high current, select RIN so that the maximum current flow is less than 10 mA
when VIN is at maximum voltage.
500
100
+10 V
RIN
VIN
±
High± Z
+
VOCM
±
+
RIN
PD
High± Z
±10 V
100
500
Figure 9-3. Path of Input Current Flow When PD = Low
9.1.3 I/O Headroom Considerations
The starting point for most designs is to assign an output common-mode voltage for the OPA1637. For accoupled signal paths, this voltage is often the default midsupply voltage to retain the most available output swing
around the voltage centered at the VOCM voltage. For dc-coupled designs, set this voltage with consideration to
the required minimum headroom to the supplies, as described in the specifications for the VOCM control. For
precision ADC drivers, this VOCM output becomes the VCM input to the ADC. Often, VCM is set to VREF / 2 to
center the differential input on the available input when precision ADCs are being driven.
From target output VOCM, the next step is to verify that the desired output differential peak-to-peak voltage,
VOUTPP, stays within the supplies. For any desired differential VOUTPP, make sure that the absolute maximum
voltage at the output pins swings with Equation 1 and Equation 2, and confirm that these expressions are within
the supply rails minus the output headroom required for the RRO device.
VOUTMIN = VOCM ±
VOUTPP
4
(1)
VOUTMAX = VOCM +
VOUTPP
4
(2)
With the output headroom confirmed, the input junctions must also stay within the operating range. The input
range limitations require a maximum 1.0-V headroom from the supply voltages (VS+ and VS–) over the full
temperature range.
20
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9.1.4 Noise Performance
The first step in the output noise analysis is to reduce the application circuit to the simplest form with equal
feedback and gain setting elements to ground. Figure 9-4 shows the simplest analysis circuit with the FDA and
resistor noise terms to be considered.
enRg2
enRf2
RG
RF
r
r
In+2
+
In±
2
eno2
±
eni2
enRg2
enRf2
RG
RF
r
r
Figure 9-4. FDA Noise Analysis Circuit
The noise powers are shown in Figure 9-4 for each term. When the RF and RG (or RI) terms are matched on
each side, the total differential output noise is the root sum squared (RSS) of these separate terms. Using NG ≡
1 + RF / RG, the total output noise is given by Equation 3. Each resistor noise term is a 4kT × R power (4kT =
1.6E-20 J at 290 K).
eo
eniNG
2
2 iNRF
2
2 4kTRFNG
(3)
The first term is simply the differential input spot noise times the noise gain. The second term is the input current
noise terms times the feedback resistor (and because there are two uncorrelated current noise terms, the power
is two times one of them). The last term is the output noise resulting from both the RF and RG resistors, at again,
twice the value for the output noise power of each side added together. Running a wide sweep of gains when
holding RF to 2 kΩ gives the standard values and resulting noise listed in Table 9-1. When the gain increases,
the input-referred noise approaches only the gain of the FDA input voltage noise term at 3.7 nV/√ Hz.
Table 9-1. Swept Gain of the Output- and Input-Referred Spot Noise Calculations
GAIN (V/V)
RF (Ω)
RG1 (Ω)
AV
EO (nV/√ Hz)
EI (nV/√ Hz)
0.1
2000
20000
0.1
9.4
93.9
1
2000
2000
1
13.6
13.6
2
2000
1000
2
17.8
8.9
5
2000
402
4.98
29.5
5.9
10
2000
200
10
48.6
4.9
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9.2 Typical Applications
9.2.1 Current-Output Audio DAC Buffer to Class-D Amplifier
RF1
1k
CF1
3.3 nF
RISO1
75
RI1
49
5V
C2
1 µF
INPUT_A
5V
±
PCM1795
Audio DAC
IOUTL/R+
IOUTL/R±
C5
1 µF
GND
± 3.5 V
RI2
49
±10 V
RF2
1k
+
OPA1637
±
+
PD
CDF
10 nF
C3
1 µF
±10 V 5 V
CF2
3.3 nF
TPA3251
Class D
ADC
Amplifier
INPUT_B
RISO2
75
GND
Figure 9-5. Differential Current-to-Voltage Converter
9.2.1.1 Design Requirements
The requirements for this application are:
•
•
•
•
Differential current-to-voltage conversion and filtering
1-kmho transimpedance gain
40-kHz Butterworth response filter
0-V dc common-mode voltage at DAC output
9.2.1.2 Detailed Design Procedure
This design provides current-to-voltage conversion from a current-output audio DAC into a voltage-input, class-D
amplifier. The order of design priorities are as follows:
•
•
•
•
•
22
Select feedback-resistor values based on the gain required from the current-output stage to the voltage-input
stage. For this design, the full-scale, peak-to-peak output current of the PCM1795 ( IOUTL/R+ – IOUTL/R–) is ±4
mA. A gain of 1k gives a wide voltage swing of ±4 V, allowing for high SNR without exceeding the input
voltage limit of the TPA3251.
After the gain is fixed, select the output common-mode voltage. The output common-mode voltage
determines the input common-mode voltage in this configuration. To set the nominal output voltage of the
PCM1795 to 0 V (which corresponds to the input common mode voltage of the OPA1637), shift the output
negatively from the desired common-mode input voltage by the gain multiplied by the dc center current value
of the PCM1795 (3.5 mA). In this case, –3.5 V satisfies the design goal.
A bypass capacitor from the VOCM pin to ground must be selected to filter noise from the voltage divider.
The capacitor selection is determined by balancing the startup time of the system with the output commonmode noise. A higher capacitance gives a lower frequency filter cutoff on the VOCM pin, thus giving lower
noise performance, but also slows down the initial startup time of the circuit as a result of the RC delay from
the resistor divider in combination with the filter capacitor.
Select CF so that the desired bandwidth of the active filter is achieved. The 3-dB frequency is determined by
the reciprocal of the product of RF and CF.
Use a passive filter on the output to increase noise filtering beyond the desired bandwidth. The passive filter
formed by RD1,2 and CDF adds an additional real pole to the filter response. If the pole is designed at the
same frequency as the active filter pole, the overall 3-dB frequency shifts to a lower frequency value, and the
step response is overdamped. A trade-off must be made to give optimal transient response versus increased
filter attenuation at higher frequencies. For this design, the second pole is set to 106 kHz.
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9.2.1.3 Application Curves
The simulated response of the current-to-voltage audio DAC buffer can be seen in Figure 9-6 and Figure 9-7.
90
0
Gain
Phase
60
-60
45
-90
30
-120
15
-150
0
-180
-15
-210
-30
-240
-45
-270
-60
100
1k
10k
Frequency (Hz)
100k
-300
1M
C105
Figure 9-6. Gain and Phase Response for Currentto-Voltage Buffer
Voltage (V)
-30
Phase (q)
Gain (dB)
75
1.2
1.05
0.9
0.75
0.6
0.45
0.3
0.15
0
-0.15
-0.3
-0.45
-0.6
-0.75
-0.9
-1.05
-1.2
VOUT
VIN
0
20
40
60
80
100 120
Time (Ps)
140
160
180
200
C105
Figure 9-7. Transient Response for Current-toVoltage Buffer
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9.2.2 An MFB Filter Driving an ADC Application
A common application use case for fully-differential amplifiers is to easily convert a single-ended signal into a
differential signal to drive a differential input source, such as an ADC or class-D amplifier. Figure 9-8 shows an
example of the OPA1637 used to convert a single-ended, low-voltage signal audio source, such as a small
electret microphone, and deliver a low-noise differential signal that is common-mode shifted to the center of the
ADC input range. A multiple-feedback (MFB) configuration is used to provide a Butterworth filter response, giving
a 40-dB/decade rolloff with a –3-dB frequency of 30 kHz.
RF1
3.65 k
RI1
732
CF1
1 nF
RG1
604
RO1
20
CA1
47 pF
RA1
100
+5 V
VIN
±
VOCM
6.2 nF
FDA
+
CA2
1 nF
±
+
ADC
PD
±5 V VS+
RI2
732
RG2
604
RF2
3.65 k
CF2
1 nF
RO2
20
RA2
100
CA3
47 pF
Figure 9-8. Example 30-kHz Butterworth Filter
9.2.2.1 Design Requirements
The requirements for this application are:
•
•
•
•
•
Single-ended to differential conversion
5-V/V gain
Active filter set to a Butterworth, 30-kHz response shape
Output RC elements set by SAR input requirements (not part of the filter design)
Filter element resistors and capacitors are set to limit added noise over the OPA1637 and noise peaking
9.2.2.2 Detailed Design Procedure
The design proceeds using the techniques and tools suggested in the Design Methodology for MFB Filters in
ADC Interface Applications application note. The process includes:
•
•
•
•
•
24
Scale the resistor values to not meaningfully contribute to the output noise produced by the OPA1637.
Select the RC ratios to hit the filter targets when reducing the noise gain peaking within the filter design.
Set the output resistor to 100 Ω into a 1-nF differential capacitor.
Add 47-pF common-mode capacitors to the load capacitor to improve common noise filtering.
Inside the loop, add 20-Ω output resistors after the filter feedback capacitor to increase the isolation to the
load capacitor.
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9.2.2.3 Application Curves
20
120
16
90
12
60
8
30
4
0
0
-30
-4
-60
-8
-90
-12
-16
Phase (q)
Gain (dB)
The gain and phase plots are shown in Figure 9-9. The MFB filter features a Butterworth responses feature very
flat passband gain, with a 2-pole roll-off at 30 kHz to eliminate any higher-frequency noise from contaminating
the signal chain, and potentially alias back into the audio band.
-120
Gain
Phase
-150
-20
100
1k
Frequency (Hz)
10k
-180
100k
C100
Figure 9-9. Gain and Phase Plot for a 30-kHz Butterworth Filter
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9.2.3 Differential Microphone Input to Line Level
Professional dynamic microphones typically feature low output impedance to minimize noise coupling on the
microphone cable. Interfacing the microphone with high-impedance circuitry typically requires the use of an
impedance conversion stage, often done with a transformer or discrete amplifiers. The flexibility of the OPA1637
allows the device to be configured with a low differential input impedance and 20 dB of gain, simplifying the
impedance conversion and gain stage into a single device. Figure 9-10 shows an example of a differential, low
input impedance, microphone level voltage (10 mV to 100 mV) amplifier to a line-level amplitude signal that also
has adjustable dc common-mode shift capability. This design example shows how the OPA1637 makes a great
choice for driving an ADC class-D amplifier.
RF1
750
Dynamic
Microphone
CF1
4.7 nF
RG1
75
RISO1
100
+15
XLR
Cable
±
1
1
VOCM
2
2
3
3
VIN
FDA
To ADC/
Class D Amplifier/
XLR output
+
±
+
PD
-15 +15
RG2
75
RISO2
100
CF2
4.7 nF
RF2
750
Figure 9-10. Fully Differential, Low-Noise, 20-dB Microphone Gain Block With DC Shift
9.2.3.1 Application Curves
2.5
VOUTVOUT+
2
Output Voltage (V)
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
0.2
0.4
0.6
0.8
1
1.2
Time (ms)
1.4
1.6
1.8
2
D075
VOCM = 0 V
Figure 9-11. Output Waveform of the Microphone Amplifier
26
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10 Power Supply Recommendations
The OPA1637 operates from supply voltages of 3.0 V to 36 V (±1.5 V to ±18 V, dual supply). Connect ceramic
bypass capacitors from both VS+ and VS– to GND.
11 Layout
11.1 Layout Guidelines
11.1.1 Board Layout Recommendations
•
•
•
•
•
Keep differential signals routed together to minimize parasitic impedance mismatch.
Connect a 0.1-µF capacitor to the supply nodes through a via.
Connect a 0.1-µF capacitor to the VOCM pin if no external voltage is used.
Keep any high-frequency nodes that can couple through parasitic paths away from the VOCM node.
Clean the PCB board after assembly to minimize any leakage paths from excess flux into the VOCM node.
11.2 Layout Example
Connect IN+/IN± through
input resistors on the top
layer. Maintain symmetry
between traces and
RIN
routing to minimize
common mode coupling.
VIN
RIN
Route the VOCM pin
connection through a via.
Connect a 0.1 µF
capacitor to VOCM if no
external voltage is used
to set the output common
mode voltage.
RF
CCM
CBYPASS
IN±
IN+
VOCM
PD
VS+
VS±
OUT+
OUT±
RF
Connect the powerdown
pin through a via. If
powerdown is not
needed, leave floating.
CBYPASS
Connect bypass
capacitors through a via.
VOUT
Figure 11-1. Example Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
•
•
•
•
OPA1637 TINA-TI™ model
TINA-TI Gain of 0.2 100kHz Butterworth MFB Filter
TINA-TI 100kHz MFB filter LG test
TINA-TI Differential Transimpedance LG Sim
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias
Current Op Amp with e-trim™ data sheet
• Texas Instruments, OPA161x SoundPlus™ High-Performance, Bipolar-Input Audio Operational Amplifiers
data sheet
• Texas Instruments, Design Methodology for MFB Filters in ADC Interface Applications application report
• Texas Instruments, Design for Wideband Differential Transimpedance DAC Output application report
• Texas Instruments, PCM1795 32-Bit, 192-kHz Sampling, Advanced Segment, Stereo Audio Digital-to-Analog
Converter data sheet
• Texas Instruments, TPA3251 175-W Stereo, 350-W Mono PurePath™ Ultra-HD Analog Input Class-D
Amplifier data sheet
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
Burr-Brown™ and TI E2E™ are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA1637DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1637
OPA1637DGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1637
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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